From patchwork Thu May 30 10:15:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13680076 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E6B618398E for ; Thu, 30 May 2024 10:00:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717063230; cv=none; b=SM87AjNO3Hs3yJ1Pybs6NaI2uObQ90uNcMoXFKkYsZw3xRv9+fe1r2ouDFXUosTnUhy5SNCAewig0leOtL+5hVU+Ru2NOYDRPy1wVd6ehIFtHHY7Ds1sowIRKvbwc3TFKUHGSC/H9UXhvK6J3TABkfp3D8uX2i+TDZUIQAElgYo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717063230; c=relaxed/simple; bh=++BnYcoBcNAMGwyagrFEnDwmOHTuHk7IscfvAsNyKo8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=r+uhwUnSQLqEsgre4nqQR8etYwheOn87ZwKB27HZBsTtsJQV/kw+6aoKz8TF5oNwzTiIU4Rk+RPOyCK9RycNNeG4LaOmyyv86ztSA6pyz29+lcSYsn95lcOJHqB/B+xtqLqNntPb6t4Zh+hrw1oE0VvYA4asWSICl6W0ED7ue+g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YgY1Khri; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YgY1Khri" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717063229; x=1748599229; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=++BnYcoBcNAMGwyagrFEnDwmOHTuHk7IscfvAsNyKo8=; b=YgY1KhriG5OvebP9OTHGKXJKfEx7U1T+5XIZWDmURT2/T5hax/nliZ2K 2h/NOw/lNzX4mbPB+B/4/bYLVdSW3+NOQNTinEbiDTJCgBfXD6qRbLxCP w/BmZfBEsSbNKFYVfZlGVr3q8+tpbYdddNgBC+Oe9jw31REFTU5eASN2O gPSDwngFvd93sSQ76hh3Y/BwQMjsbPzJb1CZJReunDMNpFSZ8/1aoe+/K 6PGm7X91KqYtImCso9QCCGBPc0tz73XVW0gj4hc0Sbi3thPCP85vxstrt y5eTxSQLbWzY67aZsShQdwU7fFeqe8ftOg/mewj8Q1kDs1DXYxJlJGuyF A==; X-CSE-ConnectionGUID: s1OeoQe/T7ax3e8/curqxA== X-CSE-MsgGUID: W7ryGwS6Sf2uWdtK9vco/w== X-IronPort-AV: E=McAfee;i="6600,9927,11087"; a="31032416" X-IronPort-AV: E=Sophos;i="6.08,201,1712646000"; d="scan'208";a="31032416" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2024 03:00:28 -0700 X-CSE-ConnectionGUID: 2d6OwtX6Q7utcO6iS5tUWQ== X-CSE-MsgGUID: Cq1pm51+TiWOBn8Wfc6VnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,201,1712646000"; d="scan'208";a="35704936" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa010.jf.intel.com with ESMTP; 30 May 2024 03:00:23 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC v2 1/7] hw/core: Make CPU topology enumeration arch-agnostic Date: Thu, 30 May 2024 18:15:33 +0800 Message-Id: <20240530101539.768484-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240530101539.768484-1-zhao1.liu@intel.com> References: <20240530101539.768484-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Cache topology needs to be defined based on CPU topology levels. Thus, define CPU topology enumeration in qapi/machine.json to make it generic for all architectures. To match the general topology naming style, rename CPU_TOPO_LEVEL_SMT and CPU_TOPO_LEVEL_PACKAGE to CPU_TOPO_LEVEL_THREAD and CPU_TOPO_LEVEL_SOCKET. Also, enumerate additional topology levels for non-i386 arches, and add helpers for topology enumeration and string conversion. Signed-off-by: Zhao Liu --- Changes since RFC v1: * Use QAPI to enumerate CPU topology levels. * Drop string_to_cpu_topo() since QAPI will help to parse the topo levels. --- MAINTAINERS | 2 ++ hw/core/cpu-topology.c | 36 ++++++++++++++++++++++++++++++ hw/core/meson.build | 1 + include/hw/core/cpu-topology.h | 20 +++++++++++++++++ include/hw/i386/topology.h | 18 +-------------- qapi/machine.json | 40 ++++++++++++++++++++++++++++++++++ target/i386/cpu.c | 30 ++++++++++++------------- target/i386/cpu.h | 4 ++-- 8 files changed, 117 insertions(+), 34 deletions(-) create mode 100644 hw/core/cpu-topology.c create mode 100644 include/hw/core/cpu-topology.h diff --git a/MAINTAINERS b/MAINTAINERS index 448dc951c509..09173e8c953d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1875,6 +1875,7 @@ R: Yanan Wang S: Supported F: hw/core/cpu-common.c F: hw/core/cpu-sysemu.c +F: hw/core/cpu-topology.c F: hw/core/machine-qmp-cmds.c F: hw/core/machine.c F: hw/core/machine-smp.c @@ -1886,6 +1887,7 @@ F: qapi/machine-common.json F: qapi/machine-target.json F: include/hw/boards.h F: include/hw/core/cpu.h +F: include/hw/core/cpu-topology.h F: include/hw/cpu/cluster.h F: include/sysemu/numa.h F: tests/unit/test-smp-parse.c diff --git a/hw/core/cpu-topology.c b/hw/core/cpu-topology.c new file mode 100644 index 000000000000..20b5d708cb54 --- /dev/null +++ b/hw/core/cpu-topology.c @@ -0,0 +1,36 @@ +/* + * QEMU CPU Topology Representation + * + * Copyright (c) 2024 Intel Corporation + * + * Authors: + * Zhao Liu + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * later. See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/core/cpu-topology.h" + +typedef struct CPUTopoInfo { + const char *name; +} CPUTopoInfo; + +CPUTopoInfo cpu_topo_descriptors[] = { + [CPU_TOPO_LEVEL_INVALID] = { .name = "invalid", }, + [CPU_TOPO_LEVEL_THREAD] = { .name = "thread", }, + [CPU_TOPO_LEVEL_CORE] = { .name = "core", }, + [CPU_TOPO_LEVEL_MODULE] = { .name = "module", }, + [CPU_TOPO_LEVEL_CLUSTER] = { .name = "cluster", }, + [CPU_TOPO_LEVEL_DIE] = { .name = "die", }, + [CPU_TOPO_LEVEL_SOCKET] = { .name = "socket", }, + [CPU_TOPO_LEVEL_BOOK] = { .name = "book", }, + [CPU_TOPO_LEVEL_DRAWER] = { .name = "drawer", }, + [CPU_TOPO_LEVEL__MAX] = { .name = NULL, }, +}; + +const char *cpu_topo_to_string(CPUTopoLevel topo) +{ + return cpu_topo_descriptors[topo].name; +} diff --git a/hw/core/meson.build b/hw/core/meson.build index a3d9bab9f42a..71dc396e9bfc 100644 --- a/hw/core/meson.build +++ b/hw/core/meson.build @@ -13,6 +13,7 @@ hwcore_ss.add(files( )) common_ss.add(files('cpu-common.c')) +common_ss.add(files('cpu-topology.c')) common_ss.add(files('machine-smp.c')) system_ss.add(when: 'CONFIG_FITLOADER', if_true: files('loader-fit.c')) system_ss.add(when: 'CONFIG_GENERIC_LOADER', if_true: files('generic-loader.c')) diff --git a/include/hw/core/cpu-topology.h b/include/hw/core/cpu-topology.h new file mode 100644 index 000000000000..0e21fe8a9bf8 --- /dev/null +++ b/include/hw/core/cpu-topology.h @@ -0,0 +1,20 @@ +/* + * QEMU CPU Topology Representation Header + * + * Copyright (c) 2024 Intel Corporation + * + * Authors: + * Zhao Liu + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * later. See the COPYING file in the top-level directory. + */ + +#ifndef CPU_TOPOLOGY_H +#define CPU_TOPOLOGY_H + +#include "qapi/qapi-types-machine.h" + +const char *cpu_topo_to_string(CPUTopoLevel topo); + +#endif /* CPU_TOPOLOGY_H */ diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index dff49fce1154..c6ff75f23991 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -39,7 +39,7 @@ * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width(). */ - +#include "hw/core/cpu-topology.h" #include "qemu/bitops.h" /* @@ -62,22 +62,6 @@ typedef struct X86CPUTopoInfo { unsigned threads_per_core; } X86CPUTopoInfo; -/* - * CPUTopoLevel is the general i386 topology hierarchical representation, - * ordered by increasing hierarchical relationship. - * Its enumeration value is not bound to the type value of Intel (CPUID[0x1F]) - * or AMD (CPUID[0x80000026]). - */ -enum CPUTopoLevel { - CPU_TOPO_LEVEL_INVALID, - CPU_TOPO_LEVEL_SMT, - CPU_TOPO_LEVEL_CORE, - CPU_TOPO_LEVEL_MODULE, - CPU_TOPO_LEVEL_DIE, - CPU_TOPO_LEVEL_PACKAGE, - CPU_TOPO_LEVEL_MAX, -}; - /* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) { diff --git a/qapi/machine.json b/qapi/machine.json index bce6e1bbc412..7ac5a05bb9c9 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -1667,6 +1667,46 @@ '*reboot-timeout': 'int', '*strict': 'bool' } } +## +# @CPUTopoLevel: +# +# An enumeration of CPU topology levels. +# +# @invalid: Invalid topology level, used as a placeholder. +# +# @thread: thread level, which would also be called SMT level or logical +# processor level. The @threads option in -smp is used to configure +# the topology of this level. +# +# @core: core level. The @cores option in -smp is used to configure the +# topology of this level. +# +# @module: module level. The @modules option in -smp is used to +# configure the topology of this level. +# +# @cluster: cluster level. The @clusters option in -smp is used to +# configure the topology of this level. +# +# @die: die level. The @dies option in -smp is used to configure the +# topology of this level. +# +# @socket: socket level, which would also be called package level. The +# @sockets option in -smp is used to configure the topology of this +# level. +# +# @book: book level. The @books option in -smp is used to configure the +# topology of this level. +# +# @drawer: drawer level. The @drawers option in -smp is used to +# configure the topology of this level. +# +# Since: 9.1 +## +{ 'enum': 'CPUTopoLevel', + 'prefix': 'CPU_TOPO_LEVEL', + 'data': [ 'invalid', 'thread', 'core', 'module', 'cluster', + 'die', 'socket', 'book', 'drawer' ] } + ## # @SMPConfiguration: # diff --git a/target/i386/cpu.c b/target/i386/cpu.c index bc2dceb647fa..b11097b5bafd 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -247,12 +247,12 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, case CPU_TOPO_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPO_LEVEL_SOCKET: num_ids = 1 << apicid_pkg_offset(topo_info); break; default: /* - * Currently there is no use case for SMT and MODULE, so use + * Currently there is no use case for THREAD and MODULE, so use * assert directly to facilitate debugging. */ g_assert_not_reached(); @@ -304,7 +304,7 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, enum CPUTopoLevel topo_level) { switch (topo_level) { - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPO_LEVEL_THREAD: return 1; case CPU_TOPO_LEVEL_CORE: return topo_info->threads_per_core; @@ -313,7 +313,7 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, case CPU_TOPO_LEVEL_DIE: return topo_info->threads_per_core * topo_info->cores_per_module * topo_info->modules_per_die; - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPO_LEVEL_SOCKET: return topo_info->threads_per_core * topo_info->cores_per_module * topo_info->modules_per_die * topo_info->dies_per_pkg; default: @@ -326,7 +326,7 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, enum CPUTopoLevel topo_level) { switch (topo_level) { - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPO_LEVEL_THREAD: return 0; case CPU_TOPO_LEVEL_CORE: return apicid_core_offset(topo_info); @@ -334,7 +334,7 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, return apicid_module_offset(topo_info); case CPU_TOPO_LEVEL_DIE: return apicid_die_offset(topo_info); - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPO_LEVEL_SOCKET: return apicid_pkg_offset(topo_info); default: g_assert_not_reached(); @@ -347,7 +347,7 @@ static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) switch (topo_level) { case CPU_TOPO_LEVEL_INVALID: return CPUID_1F_ECX_TOPO_LEVEL_INVALID; - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPO_LEVEL_THREAD: return CPUID_1F_ECX_TOPO_LEVEL_SMT; case CPU_TOPO_LEVEL_CORE: return CPUID_1F_ECX_TOPO_LEVEL_CORE; @@ -371,7 +371,7 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, unsigned long level, next_level; uint32_t num_threads_next_level, offset_next_level; - assert(count + 1 < CPU_TOPO_LEVEL_MAX); + assert(count + 1 < CPU_TOPO_LEVEL__MAX); /* * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. @@ -380,7 +380,7 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, level = CPU_TOPO_LEVEL_INVALID; for (int i = 0; i <= count; i++) { level = find_next_bit(env->avail_cpu_topo, - CPU_TOPO_LEVEL_PACKAGE, + CPU_TOPO_LEVEL_SOCKET, level + 1); /* @@ -388,7 +388,7 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, * and it just encodes the invalid level (all fields are 0) * into the last subleaf of 0x1f. */ - if (level == CPU_TOPO_LEVEL_PACKAGE) { + if (level == CPU_TOPO_LEVEL_SOCKET) { level = CPU_TOPO_LEVEL_INVALID; break; } @@ -399,7 +399,7 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, offset_next_level = 0; } else { next_level = find_next_bit(env->avail_cpu_topo, - CPU_TOPO_LEVEL_PACKAGE, + CPU_TOPO_LEVEL_SOCKET, level + 1); num_threads_next_level = num_threads_by_topo_level(topo_info, next_level); @@ -6435,7 +6435,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, /* Share the cache at package level. */ *eax |= max_thread_ids_for_cache(&topo_info, - CPU_TOPO_LEVEL_PACKAGE) << 14; + CPU_TOPO_LEVEL_SOCKET) << 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { @@ -7935,10 +7935,10 @@ static void x86_cpu_init_default_topo(X86CPU *cpu) env->nr_modules = 1; env->nr_dies = 1; - /* SMT, core and package levels are set by default. */ - set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); + /* thread, core and socket levels are set by default. */ + set_bit(CPU_TOPO_LEVEL_THREAD, env->avail_cpu_topo); set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); - set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); + set_bit(CPU_TOPO_LEVEL_SOCKET, env->avail_cpu_topo); } static void x86_cpu_initfn(Object *obj) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c64ef0c1a287..c6d07f38a1e8 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1606,7 +1606,7 @@ typedef struct CPUCacheInfo { * Used to encode CPUID[4].EAX[bits 25:14] or * CPUID[0x8000001D].EAX[bits 25:14]. */ - enum CPUTopoLevel share_level; + CPUTopoLevel share_level; } CPUCacheInfo; @@ -1921,7 +1921,7 @@ typedef struct CPUArchState { unsigned nr_modules; /* Bitmap of available CPU topology levels for this CPU. */ - DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX); + DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL__MAX); } CPUX86State; struct kvm_msrs; From patchwork Thu May 30 10:15:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13680077 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 804BE176190 for ; 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a="31032448" X-IronPort-AV: E=Sophos;i="6.08,201,1712646000"; d="scan'208";a="31032448" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2024 03:00:37 -0700 X-CSE-ConnectionGUID: TKXLj6QZRxOqLu9u46k3EQ== X-CSE-MsgGUID: dl3u8jibTlSRrNV7RvOg9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,201,1712646000"; d="scan'208";a="35705007" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa010.jf.intel.com with ESMTP; 30 May 2024 03:00:29 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC v2 2/7] hw/core: Define cache topology for machine Date: Thu, 30 May 2024 18:15:34 +0800 Message-Id: <20240530101539.768484-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240530101539.768484-1-zhao1.liu@intel.com> References: <20240530101539.768484-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Define the cache topology based on CPU topology level for two reasons: 1. In practice, a cache will always be bound to the CPU container (either private in the CPU container or shared among multiple containers), and CPU container is often expressed in terms of CPU topology level. 2. The x86's cache-related CPUIDs encode cache topology based on APIC ID's CPU topology layout. And the ACPI PPTT table that ARM/RISCV relies on also requires CPU containers to help indicate the private shared hierarchy of the cache. Therefore, for SMP systems, it is natural to use the CPU topology hierarchy directly in QEMU to define the cache topology. Currently, separated L1 cache (L1 data cache and L1 instruction cache) with unified higher-level cache (e.g., unified L2 and L3 caches), is the most common cache architectures. Therefore, define the topology for L1 D-cache, L1 I-cache, L2 cache and L3 cache in machine as the basic cache topology support. Signed-off-by: Zhao Liu --- hw/core/machine.c | 5 +++++ include/hw/boards.h | 25 +++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/hw/core/machine.c b/hw/core/machine.c index 8087026b45da..e31d0f3cb4b0 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1175,6 +1175,11 @@ static void machine_initfn(Object *obj) ms->smp.cores = 1; ms->smp.threads = 1; + ms->smp_cache.l1d = CPU_TOPO_LEVEL_INVALID; + ms->smp_cache.l1i = CPU_TOPO_LEVEL_INVALID; + ms->smp_cache.l2 = CPU_TOPO_LEVEL_INVALID; + ms->smp_cache.l3 = CPU_TOPO_LEVEL_INVALID; + machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); } diff --git a/include/hw/boards.h b/include/hw/boards.h index c1737f2a5736..e70b2a1bdca2 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -10,6 +10,7 @@ #include "qemu/module.h" #include "qom/object.h" #include "hw/core/cpu.h" +#include "hw/core/cpu-topology.h" #define TYPE_MACHINE_SUFFIX "-machine" @@ -145,6 +146,12 @@ typedef struct { * @books_supported - whether books are supported by the machine * @drawers_supported - whether drawers are supported by the machine * @modules_supported - whether modules are supported by the machine + * @l1_separated_cache_supported - whether l1 data and instruction cache + * topology are supported by the machine + * @l2_unified_cache_supported - whether l2 unified cache topology are + * supported by the machine + * @l3_unified_cache_supported - whether l3 unified cache topology are + * supported by the machine */ typedef struct { bool prefer_sockets; @@ -154,6 +161,9 @@ typedef struct { bool books_supported; bool drawers_supported; bool modules_supported; + bool l1_separated_cache_supported; + bool l2_unified_cache_supported; + bool l3_unified_cache_supported; } SMPCompatProps; /** @@ -359,6 +369,20 @@ typedef struct CPUTopology { unsigned int max_cpus; } CPUTopology; +/** + * CPUTopology: + * @l1d: the CPU topology hierarchy the L1 data cache is shared at. + * @l1i: the CPU topology hierarchy the L1 instruction cache is shared at. + * @l2: the CPU topology hierarchy the L2 (unified) cache is shared at. + * @l3: the CPU topology hierarchy the L3 (unified) cache is shared at. + */ +typedef struct CacheTopology { + CPUTopoLevel l1d; + CPUTopoLevel l1i; + CPUTopoLevel l2; + CPUTopoLevel l3; +} CacheTopology; + /** * MachineState: */ @@ -410,6 +434,7 @@ struct MachineState { AccelState *accelerator; CPUArchIdList *possible_cpus; CPUTopology smp; + CacheTopology smp_cache; struct NVDIMMState *nvdimms_state; struct NumaState *numa_state; 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30 May 2024 03:00:36 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC v2 3/7] hw/core: Add cache topology options in -smp Date: Thu, 30 May 2024 18:15:35 +0800 Message-Id: <20240530101539.768484-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240530101539.768484-1-zhao1.liu@intel.com> References: <20240530101539.768484-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add "l1d-cache", "l1i-cache". "l2-cache", and "l3-cache" options in -smp to define the cache topology for SMP system. Signed-off-by: Zhao Liu --- Changes since RFC v1: * Set has_*_cache field in machine_get_smp(). (JeeHeng) * Adjust string breaking style in error_setg() for more semantic sentence breaking conventions. (Jonathan) * Add more description about cache options. (Markus) * Now in v2, config->*_cache field stores topology enumeration instead of string, no need to parse, so just make machine_check_cache_topo() return boolean. --- hw/core/machine-smp.c | 146 +++++++++++++++++++++++++++++++++++++++++ hw/core/machine.c | 20 ++++++ qapi/machine.json | 23 ++++++- system/vl.c | 12 ++++ tests/unit/meson.build | 3 +- 5 files changed, 202 insertions(+), 2 deletions(-) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 5d8d7edcbd3f..c79464cf3d2c 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -61,6 +61,150 @@ static char *cpu_hierarchy_to_string(MachineState *ms) return g_string_free(s, false); } +static bool machine_check_topo_support(MachineState *ms, + CPUTopoLevel topo) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + + if (topo == CPU_TOPO_LEVEL_MODULE && !mc->smp_props.modules_supported) { + return false; + } + + if (topo == CPU_TOPO_LEVEL_CLUSTER && !mc->smp_props.clusters_supported) { + return false; + } + + if (topo == CPU_TOPO_LEVEL_DIE && !mc->smp_props.dies_supported) { + return false; + } + + if (topo == CPU_TOPO_LEVEL_BOOK && !mc->smp_props.books_supported) { + return false; + } + + if (topo == CPU_TOPO_LEVEL_DRAWER && !mc->smp_props.drawers_supported) { + return false; + } + + return true; +} + +static bool machine_check_cache_topo(MachineState *ms, + CPUTopoLevel topo, + Error **errp) +{ + if (topo == CPU_TOPO_LEVEL__MAX || topo == CPU_TOPO_LEVEL_INVALID) { + error_setg(errp, + "Invalid cache topology level: %s. " + "The cache topology should match the " + "valid CPU topology level", + cpu_topo_to_string(topo)); + return false; + } + + if (!machine_check_topo_support(ms, topo)) { + error_setg(errp, + "Invalid cache topology level: %s. " + "The topology level is not supported by this machine", + cpu_topo_to_string(topo)); + return false; + } + + return true; +} + +static void machine_parse_smp_cache_config(MachineState *ms, + const SMPConfiguration *config, + Error **errp) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + + /* + * The cache topology does not support a default entry similar to + * CPU topology with parameters=1. So when the machine explicitly + * does not support cache topology, return the error. + */ + if (config->has_l1d_cache) { + if (!mc->smp_props.l1_separated_cache_supported) { + error_setg(errp, + "L1 D-cache topology not supported by this machine"); + return; + } + + if (!machine_check_cache_topo(ms, config->l1d_cache, errp)) { + return; + } + + ms->smp_cache.l1d = config->l1d_cache; + } + + if (config->has_l1i_cache) { + if (!mc->smp_props.l1_separated_cache_supported) { + error_setg(errp, + "L1 I-cache topology not supported by this machine"); + return; + } + + if (!machine_check_cache_topo(ms, config->l1i_cache, errp)) { + return; + } + + ms->smp_cache.l1i = config->l1i_cache; + } + + if (config->has_l2_cache) { + if (!mc->smp_props.l2_unified_cache_supported) { + error_setg(errp, + "L2 cache topology not supported by this machine"); + return; + } + + if (!machine_check_cache_topo(ms, config->l2_cache, errp)) { + return; + } + + ms->smp_cache.l2 = config->l2_cache; + + /* + * Cache topology is initialized by default to CPU_TOPO_LEVEL_INVALID, + * which is the lowest level, so such a check is OK, even if the config + * doesn't override that field. + */ + if (ms->smp_cache.l1d > ms->smp_cache.l2 || + ms->smp_cache.l1i > ms->smp_cache.l2) { + error_setg(errp, + "Invalid L2 cache topology. " + "L2 cache topology level should not be lower than " + "L1 D-cache/L1 I-cache"); + return; + } + } + + if (config->has_l3_cache) { + if (!mc->smp_props.l2_unified_cache_supported) { + error_setg(errp, + "L3 cache topology not supported by this machine"); + return; + } + + if (!machine_check_cache_topo(ms, config->l3_cache, errp)) { + return; + } + + ms->smp_cache.l3 = config->l3_cache; + + if (ms->smp_cache.l1d > ms->smp_cache.l3 || + ms->smp_cache.l1i > ms->smp_cache.l3 || + ms->smp_cache.l2 > ms->smp_cache.l3) { + error_setg(errp, + "Invalid L3 cache topology. " + "L3 cache topology level should not be lower than " + "L1 D-cache/L1 I-cache/L2 cache"); + return; + } + } +} + /* * machine_parse_smp_config: Generic function used to parse the given * SMP configuration @@ -259,6 +403,8 @@ void machine_parse_smp_config(MachineState *ms, mc->name, mc->max_cpus); return; } + + machine_parse_smp_cache_config(ms, config, errp); } unsigned int machine_topo_get_cores_per_socket(const MachineState *ms) diff --git a/hw/core/machine.c b/hw/core/machine.c index e31d0f3cb4b0..f705485f83c0 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -900,6 +900,26 @@ static void machine_get_smp(Object *obj, Visitor *v, const char *name, .has_maxcpus = true, .maxcpus = ms->smp.max_cpus, }; + if (ms->smp_cache.l1d != CPU_TOPO_LEVEL_INVALID) { + config->has_l1d_cache = true; + config->l1d_cache = ms->smp_cache.l1d; + } + + if (ms->smp_cache.l1i != CPU_TOPO_LEVEL_INVALID) { + config->has_l1i_cache = true; + config->l1i_cache = ms->smp_cache.l1i; + } + + if (ms->smp_cache.l2 != CPU_TOPO_LEVEL_INVALID) { + config->has_l2_cache = true; + config->l2_cache = ms->smp_cache.l2; + } + + if (ms->smp_cache.l3 != CPU_TOPO_LEVEL_INVALID) { + config->has_l3_cache = true; + config->l3_cache = ms->smp_cache.l3; + } + if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) { return; } diff --git a/qapi/machine.json b/qapi/machine.json index 7ac5a05bb9c9..8fa5af69b1bf 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -1746,6 +1746,23 @@ # # @threads: number of threads per core # +# @l1d-cache: topology hierarchy of L1 data cache. It accepts the CPU +# topology enumeration as the parameter, i.e., CPUs in the same +# topology container share the same L1 data cache. (since 9.1) +# +# @l1i-cache: topology hierarchy of L1 instruction cache. It accepts +# the CPU topology enumeration as the parameter, i.e., CPUs in the +# same topology container share the same L1 instruction cache. +# (since 9.1) +# +# @l2-cache: topology hierarchy of L2 unified cache. It accepts the CPU +# topology enumeration as the parameter, i.e., CPUs in the same +# topology container share the same L2 unified cache. (since 9.1) +# +# @l3-cache: topology hierarchy of L3 unified cache. It accepts the CPU +# topology enumeration as the parameter, i.e., CPUs in the same +# topology container share the same L3 unified cache. (since 9.1) +# # Since: 6.1 ## { 'struct': 'SMPConfiguration', 'data': { @@ -1758,7 +1775,11 @@ '*modules': 'int', '*cores': 'int', '*threads': 'int', - '*maxcpus': 'int' } } + '*maxcpus': 'int', + '*l1d-cache': 'CPUTopoLevel', + '*l1i-cache': 'CPUTopoLevel', + '*l2-cache': 'CPUTopoLevel', + '*l3-cache': 'CPUTopoLevel' } } ## # @x-query-irq: diff --git a/system/vl.c b/system/vl.c index a3eede5fa5b8..c7c94d41bd01 100644 --- a/system/vl.c +++ b/system/vl.c @@ -753,6 +753,18 @@ static QemuOptsList qemu_smp_opts = { }, { .name = "maxcpus", .type = QEMU_OPT_NUMBER, + }, { + .name = "l1d-cache", + .type = QEMU_OPT_STRING, + }, { + .name = "l1i-cache", + .type = QEMU_OPT_STRING, + }, { + .name = "l2-cache", + .type = QEMU_OPT_STRING, + }, { + .name = "l3-cache", + .type = QEMU_OPT_STRING, }, { /*End of list */ } }, diff --git a/tests/unit/meson.build b/tests/unit/meson.build index 26c109c968ce..8877dbbc00c9 100644 --- a/tests/unit/meson.build +++ b/tests/unit/meson.build @@ -138,7 +138,8 @@ if have_system 'test-util-sockets': ['socket-helpers.c'], 'test-base64': [], 'test-bufferiszero': [], - 'test-smp-parse': [qom, meson.project_source_root() / 'hw/core/machine-smp.c'], + 'test-smp-parse': [qom, meson.project_source_root() / 'hw/core/machine-smp.c', + meson.project_source_root() / 'hw/core/cpu-topology.c'], 'test-vmstate': [migration, io], 'test-yank': ['socket-helpers.c', qom, io, chardev] } From patchwork Thu May 30 10:15:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13680079 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2BE46F2FB for ; Thu, 30 May 2024 10:00:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717063248; cv=none; b=lwB/cmGxqHHvVvHbpBOv2KPKCsUosOBFArzVJB2BYfZzE1dHXoofwieF7tgcxfz6GWpAy9WoXP5H4s4kE9SRHQTZlhxPpiCF1I+IOicbZMvYh+RN4BOH2LDlGlzk0r+vsOFkE7VYAeMTa8BQCZJxEEqR+cN7+qWy3b3IogqWmDQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717063248; c=relaxed/simple; bh=iUVuwDv8IlCBNKOZ1ofL/GWf0HNwQI4LTyFUGM4Cs7g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=btt3SRSrCWo1Z12tX7cEj5OYSzgtUpNB+jzg+C0jn6vuopZzj+JAB1o8vo/SUSkMCFcTlIssOsmGUG6PaVXE0wdMUDoQuTmS1mw40HG5CftEIPi+k17b7dYVQit+t6zhB+aWCthMfJ3IFWisDCdqYkdPlonFW0Z/96hoZRPitM0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Lx+aizFs; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Lx+aizFs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717063247; x=1748599247; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iUVuwDv8IlCBNKOZ1ofL/GWf0HNwQI4LTyFUGM4Cs7g=; b=Lx+aizFs8WI99xcR0QfELw3tldteGxOrJIjnepDsk+XJk/9EOAdwlvVz riKNb/uiktfLP1sYxxch5NPu4Ra+zgFk9HgeFsd5tnZb6bybpgZtZc7m5 lCdmAK0tD5vruQsFpyW+xaG9PFg9FBT+tcFZb4yCy7anVAIMRHpGbqyoM pDl3HA4YA7ZmkXHIDzkaoiqyj4LrNgy8OGrSsK36ZNSHWd0MAQbgft11o Hec018Yzu32kcVyVISUlF4jnXUoViGJW5L6cHWi5RGbHykbjxtw2jCXNe SSCFRf0nvFgIcndaQ4V/QhLAAOUV2Pv8s7nSp6UkHXbud3AgIJ+4N/pte g==; X-CSE-ConnectionGUID: vBIEqF1+TPanKFkKLBNjRQ== X-CSE-MsgGUID: RzklqnwcSLaJ6PABT8gt/w== X-IronPort-AV: E=McAfee;i="6600,9927,11087"; a="31032540" X-IronPort-AV: E=Sophos;i="6.08,201,1712646000"; d="scan'208";a="31032540" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2024 03:00:47 -0700 X-CSE-ConnectionGUID: 9uWka8WTQZqxrJEPByh1OA== X-CSE-MsgGUID: 5Q3UyZ3qRfeH+DYgEY/FpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,201,1712646000"; d="scan'208";a="35705073" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa010.jf.intel.com with ESMTP; 30 May 2024 03:00:42 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC v2 4/7] i386/cpu: Support thread and module level cache topology Date: Thu, 30 May 2024 18:15:36 +0800 Message-Id: <20240530101539.768484-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240530101539.768484-1-zhao1.liu@intel.com> References: <20240530101539.768484-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Allows cache to be defined at the thread and module level. This increases flexibility for x86 users to customize their cache topology. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b11097b5bafd..3a2dadb4bce0 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -241,9 +241,15 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, uint32_t num_ids = 0; switch (share_level) { + case CPU_TOPO_LEVEL_THREAD: + num_ids = 1; + break; case CPU_TOPO_LEVEL_CORE: num_ids = 1 << apicid_core_offset(topo_info); break; + case CPU_TOPO_LEVEL_MODULE: + num_ids = 1 << apicid_module_offset(topo_info); + break; case CPU_TOPO_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; @@ -251,10 +257,6 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, num_ids = 1 << apicid_pkg_offset(topo_info); break; default: - /* - * Currently there is no use case for THREAD and MODULE, so use - * assert directly to facilitate debugging. - */ g_assert_not_reached(); } From patchwork Thu May 30 10:15:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13680080 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 573056F2FB for ; Thu, 30 May 2024 10:00:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717063253; cv=none; b=hDP2P+2Qt7OJlqPphTTrurdqXvvGml9yKvxfkZiLpWvxWxOD8Nu9+ygue13fAxlB64pA/TY1nosDjl0hgbd0wXHDoC4lytdyzEvwUKSrR4Zn8dxfKkjdnewdu4G1nfgpgm7LXivbsUdccrFGVjDUd/11GWKW1drTwwcXUe01Nk0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717063253; c=relaxed/simple; bh=TkFL4JGvaBtqT8WMIo99wxT4H70mghAQsEG6xdgy1EE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OMfriFCddonGaU7/LQ+ENQnNcahUvtYtDjMkIuPilqGHfHCGq1X8fZOFimD7DVeclCd64BrBkRoFrcAF05qwTG/5OlsU5sADx6O/pt58NnXSV0eKvNn99VZyBVX7XGqb//BR3k2vSpiXQXL9B3EWRr07FT2U9o1LOwCZ9Vt1uU4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YDRMQE0D; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YDRMQE0D" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717063253; x=1748599253; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TkFL4JGvaBtqT8WMIo99wxT4H70mghAQsEG6xdgy1EE=; b=YDRMQE0D0rsUaWlKQXn6E1OBHsxarrJ8oH6kzIguY3SZx3GhtaFwNIku BU4uia9Q+xKETIW393kpWM8zyigdqT5c+BhHPAhlLEtH0YJgM4TcUnmTK nYaTTLbjuTtRgsy8EiBVwH2GX4jNoZm79E7UA+Fl8TN4kppff828/5LtH QI009mtdVnGQT+p4bsPiIp+z5HvnVXd2lNWrEFnisjOFZEhMfl9SxwBXh zE72s2AC1M/5mpwrSTmCDC+p+czFjTUbZfwbwwY0EjypxcHXEkeuyDkcx uL15/qOmLlmYdI/SgaimBj0/s8+2wSgcFhcTMHJkXHVpk6zYJq1evUIZE A==; X-CSE-ConnectionGUID: nJxJl0aoSfKGYJajJmpYqA== X-CSE-MsgGUID: rfipyUKOQTOm4mDMwVaJhw== X-IronPort-AV: E=McAfee;i="6600,9927,11087"; a="31032560" X-IronPort-AV: E=Sophos;i="6.08,201,1712646000"; d="scan'208";a="31032560" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2024 03:00:52 -0700 X-CSE-ConnectionGUID: /YQgvYFURk+y03VbFGoVyw== X-CSE-MsgGUID: DC+EoqJ5R4+XMosDINLHMg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,201,1712646000"; d="scan'208";a="35705107" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa010.jf.intel.com with ESMTP; 30 May 2024 03:00:47 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC v2 5/7] i386/cpu: Update cache topology with machine's configuration Date: Thu, 30 May 2024 18:15:37 +0800 Message-Id: <20240530101539.768484-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240530101539.768484-1-zhao1.liu@intel.com> References: <20240530101539.768484-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User will configure SMP cache topology via -smp. For this case, update the x86 CPUs' cache topology with user's configuration in MachineState. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3a2dadb4bce0..1bd1860ae625 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7764,6 +7764,27 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY MachineState *ms = MACHINE(qdev_get_machine()); + + if (ms->smp_cache.l1d != CPU_TOPO_LEVEL_INVALID) { + env->cache_info_cpuid4.l1d_cache->share_level = ms->smp_cache.l1d; + env->cache_info_amd.l1d_cache->share_level = ms->smp_cache.l1d; + } + + if (ms->smp_cache.l1i != CPU_TOPO_LEVEL_INVALID) { + env->cache_info_cpuid4.l1i_cache->share_level = ms->smp_cache.l1i; + env->cache_info_amd.l1i_cache->share_level = ms->smp_cache.l1i; + } + + if (ms->smp_cache.l2 != CPU_TOPO_LEVEL_INVALID) { + env->cache_info_cpuid4.l2_cache->share_level = ms->smp_cache.l2; + env->cache_info_amd.l2_cache->share_level = ms->smp_cache.l2; + } + + if (ms->smp_cache.l3 != CPU_TOPO_LEVEL_INVALID) { + env->cache_info_cpuid4.l3_cache->share_level = ms->smp_cache.l3; + env->cache_info_amd.l3_cache->share_level = ms->smp_cache.l3; + } + qemu_register_reset(x86_cpu_machine_reset_cb, cpu); if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { From patchwork Thu May 30 10:15:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13680081 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A41D6F2FB for ; Thu, 30 May 2024 10:00:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717063259; cv=none; b=hubbAjXHDptWeyC0HMK0xW4kTYtA3h5M3XjX66ncacUzyPgrE9OGkLs3LZWdUQpNB6YNZi9UyfYJuD8+g66zOR0zSEF88WHRuKarPXsPpXGWt5T75vXzJ0g5ZHUfY6jWvvRXvFvOytEqzTnLiZZS1uq4UwgCMK2sJ69sZ890Uzo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717063259; c=relaxed/simple; bh=znO68kctoXTm05SXOnOkWCHEq8CPUvXamn9nrKcDybU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mi4f6hIQ/i1Vtq+Fa0n7OZvJoA/36bqp6HatE2bThKqycKu7xopoK9uyz6M2b9tuz/yae0k54XbIjhyK7tE5ETmMSF1xYKKCPAt4OjsZBXhE7QaYTfVmdGEWXN8GfMHEW3C/ZtSK6s+Vb1DK1rGviyudegEdzFEroeTE7KaYc3E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RrIOqPNT; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RrIOqPNT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717063258; x=1748599258; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=znO68kctoXTm05SXOnOkWCHEq8CPUvXamn9nrKcDybU=; b=RrIOqPNTjm+L32+qqQrMmRb8ASiYdwqAf8sOxJRqxWQ68Kr2xcgR0uAS 02WLHEznnDdyf23/LCvpxT+jiN0WL0TY3Uy/XxJBN7N4IikD87ItmrPfn 8zXS5vjaxs+/2t5FBJZ0svt8Y7smLvphSOhrbPZrvpk4+1gBjYWIz7dL9 M30YE/dm7Up0MBXV68IgudmFeczt7BJbfyxRnd8fWfhpt5Bs4MC4zHdOp aEYY/mVfszM62pAxf+z5aDff2ZQzix8nH8wWE+JOwGp0MowQkRJSNSXPz KXWBFha2gM19KbelJ7GWL0nS+/wbM1uUJEFNiJ1WOOQPHcvQQivoThgMV Q==; X-CSE-ConnectionGUID: VIyekKxhTqGl1o7w+255Ow== X-CSE-MsgGUID: Lt/liS93Tkik+CMu31MgyQ== X-IronPort-AV: E=McAfee;i="6600,9927,11087"; a="31032598" X-IronPort-AV: E=Sophos;i="6.08,201,1712646000"; d="scan'208";a="31032598" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2024 03:00:58 -0700 X-CSE-ConnectionGUID: neXIx/biQuuMsRJXYFHhLw== X-CSE-MsgGUID: vImgdb6DR5m+pUdi65nqSg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,201,1712646000"; d="scan'208";a="35705138" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa010.jf.intel.com with ESMTP; 30 May 2024 03:00:53 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC v2 6/7] i386/pc: Support cache topology in -smp for PC machine Date: Thu, 30 May 2024 18:15:38 +0800 Message-Id: <20240530101539.768484-7-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240530101539.768484-1-zhao1.liu@intel.com> References: <20240530101539.768484-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Signed-off-by: Zhao Liu --- hw/i386/pc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 7b638da7aaa8..2e03b33a4116 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1844,6 +1844,9 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) mc->nvdimm_supported = true; mc->smp_props.dies_supported = true; mc->smp_props.modules_supported = true; + mc->smp_props.l1_separated_cache_supported = true; + mc->smp_props.l2_unified_cache_supported = true; + mc->smp_props.l3_unified_cache_supported = true; mc->default_ram_id = "pc.ram"; pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; From patchwork Thu May 30 10:15:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13680082 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D25926F2E6 for ; Thu, 30 May 2024 10:01:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717063266; cv=none; b=GydcRALoWY3oSlyajVaskJuRZtbVpVeTs+SnM5+2Fzlcsi6rynHXuyIaVfwUt8pV1+gVSjjeIzbOeMSmYpYyZSvvecE8PN4AVIMCWbLS5xsOUlDAlLZalGmccHOaT4xyItSvnmz696UnlyOkBTgc+HXoKUUdbzqMgWA1LJDTBYQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717063266; c=relaxed/simple; bh=kd8Iqz6IxYjau87nIpOYyMS3R+5juiDyGSjeB2FuXwE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YzBsfejl4xsJM8FEzJ7v5NOQJzPgfSDuaML2eByPrI5ViaxdnyMQ6NW05uHnJ/RHFyvuwCQM8Rz6wUfVyQ5/YY6DDUtbg+fupq/+Z5ggMya11vyGYSEZHtjFEb0z7RQfFzNj6zk9O+Nr7HeY+mycUes0RnZuhyzGP9v8fw4DxxY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=SEnRcd1h; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="SEnRcd1h" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717063264; x=1748599264; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kd8Iqz6IxYjau87nIpOYyMS3R+5juiDyGSjeB2FuXwE=; b=SEnRcd1hqUHNdT6aSEyj7j8KIYEEtEPZSHVoSBXobY3Xovo2sROBkIPH Ek3Ox21ZyuNVFvKkkZoCx9+ZCR/dkdf7ZV4LId3I3YIhQ4iej9CJEX6de wMLLacM9O7vIb5BZ9jmr9EXvRUaIXfyzLl4TfruZlkPqPcCnEBoKK1fzV Byicw4bkcHAkug/ueS/f2Iap4IxZL3yUNv8Ew8lwMwstPYbg55TaIZxxi KZWXTnoYnd8ep+Di20jClZ7N5AFGGl8bog5gIEku+VyM3BdmMKKUU6c8J DAlheBvlPUcqHbOEJq6mKzlES6uBfKaWDzsKr5W9D00zV1f1pct26tWqr Q==; X-CSE-ConnectionGUID: ULvn4H3IQbWDOtpLi9OxAQ== X-CSE-MsgGUID: R01b5odOQFy9fhOQaLbI1g== X-IronPort-AV: E=McAfee;i="6600,9927,11087"; a="31032641" X-IronPort-AV: E=Sophos;i="6.08,201,1712646000"; d="scan'208";a="31032641" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2024 03:01:04 -0700 X-CSE-ConnectionGUID: SyRY+RB0TV6YokdKL/13XA== X-CSE-MsgGUID: aFRS7jt6QPWbeEZPIX3Qmw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,201,1712646000"; d="scan'208";a="35705172" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa010.jf.intel.com with ESMTP; 30 May 2024 03:00:58 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC v2 7/7] qemu-options: Add the cache topology description of -smp Date: Thu, 30 May 2024 18:15:39 +0800 Message-Id: <20240530101539.768484-8-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240530101539.768484-1-zhao1.liu@intel.com> References: <20240530101539.768484-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Signed-off-by: Zhao Liu --- Changes since RFC v1: * Use "*_cache=topo_level" as -smp example as the original "level" term for a cache has a totally different meaning. (Jonathan) --- qemu-options.hx | 50 +++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 44 insertions(+), 6 deletions(-) diff --git a/qemu-options.hx b/qemu-options.hx index 8ca7f34ef0c8..29d8a4b9b68b 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -282,7 +282,8 @@ ERST DEF("smp", HAS_ARG, QEMU_OPTION_smp, "-smp [[cpus=]n][,maxcpus=maxcpus][,drawers=drawers][,books=books][,sockets=sockets]\n" " [,dies=dies][,clusters=clusters][,modules=modules][,cores=cores]\n" - " [,threads=threads]\n" + " [,threads=threads][,l1d-cache=topo_level][,l1i-cache=topo_level]\n" + " [,l2-cache=topo_level][,l3-cache=topo_level]\n" " set the number of initial CPUs to 'n' [default=1]\n" " maxcpus= maximum number of total CPUs, including\n" " offline CPUs for hotplug, etc\n" @@ -294,7 +295,11 @@ DEF("smp", HAS_ARG, QEMU_OPTION_smp, " modules= number of modules in one cluster\n" " cores= number of cores in one module\n" " threads= number of threads in one core\n" - "Note: Different machines may have different subsets of the CPU topology\n" + " l1d-cache= topology level of L1 D-cache\n" + " l1i-cache= topology level of L1 I-cache\n" + " l2-cache= topology level of L2 cache\n" + " l3-cache= topology level of L3 cache\n" + "Note: Different machines may have different subsets of the CPU and cache topology\n" " parameters supported, so the actual meaning of the supported parameters\n" " will vary accordingly. For example, for a machine type that supports a\n" " three-level CPU hierarchy of sockets/cores/threads, the parameters will\n" @@ -308,7 +313,7 @@ DEF("smp", HAS_ARG, QEMU_OPTION_smp, " must be set as 1 in the purpose of correct parsing.\n", QEMU_ARCH_ALL) SRST -``-smp [[cpus=]n][,maxcpus=maxcpus][,drawers=drawers][,books=books][,sockets=sockets][,dies=dies][,clusters=clusters][,modules=modules][,cores=cores][,threads=threads]`` +``-smp [[cpus=]n][,maxcpus=maxcpus][,drawers=drawers][,books=books][,sockets=sockets][,dies=dies][,clusters=clusters][,modules=modules][,cores=cores][,threads=threads][,l1d-cache=topo_level][,l1i-cache=topo_level][,l2-cache=topo_level][,l3-cache=topo_level]`` Simulate a SMP system with '\ ``n``\ ' CPUs initially present on the machine type board. On boards supporting CPU hotplug, the optional '\ ``maxcpus``\ ' parameter can be set to enable further CPUs to be @@ -322,15 +327,34 @@ SRST Both parameters are subject to an upper limit that is determined by the specific machine type chosen. + CPU topology parameters include '\ ``drawers``\ ', '\ ``books``\ ', + '\ ``sockets``\ ', '\ ``dies``\ ', '\ ``clusters``\ ', '\ ``modules``\ ', + '\ ``cores``\ ' and '\ ``threads``\ '. These CPU parameters accept only + integers and are used to specify the number of specific topology domains + under the corresponding topology level. + To control reporting of CPU topology information, values of the topology parameters can be specified. Machines may only support a subset of the - parameters and different machines may have different subsets supported - which vary depending on capacity of the corresponding CPU targets. So - for a particular machine type board, an expected topology hierarchy can + CPU topology parameters and different machines may have different subsets + supported which vary depending on capacity of the corresponding CPU targets. + So for a particular machine type board, an expected topology hierarchy can be defined through the supported sub-option. Unsupported parameters can also be provided in addition to the sub-option, but their values must be set as 1 in the purpose of correct parsing. + Cache topology parameters include '\ ``l1d-cache``\ ', '\ ``l1i-cache``\ ', + '\ ``l2-cache``\ ' and '\ ``l3-cache``\ '. These cache topology parameters + accept the strings of CPU topology levels (such as '\ ``drawer``\ ', '\ ``book``\ ', + '\ ``socket``\ ', '\ ``die``\ ', '\ ``cluster``\ ', '\ ``module``\ ', + '\ ``core``\ ' or '\ ``thread``\ '). Exactly which topology level strings + could be accepted as the parameter depends on the machine's support for the + corresponding CPU topology level. + + Machines may also only support a subset of the cache topology parameters. + Unsupported cache topology parameters will be omitted, and correspondingly, + the target CPU's cache topology will use the its default cache topology + setting. + Either the initial CPU count, or at least one of the topology parameters must be specified. The specified parameters must be greater than zero, explicit configuration like "cpus=0" is not allowed. Values for any @@ -356,6 +380,20 @@ SRST -smp 32,sockets=2,dies=2,modules=2,cores=2,threads=2,maxcpus=32 + The following sub-option defines a CPU topology hierarchy (2 sockets + totally on the machine, 2 dies per socket, 2 modules per die, 2 cores per + module, 2 threads per core) with 3-level cache topology hierarchy (L1 + D-cache per core, L1 I-cache per core, L2 cache per core and L3 cache per + die) for PC machines which support sockets/dies/modules/cores/threads. + Some members of the CPU topology option can be omitted but their values + will be automatically computed. Some members of the cache topology + option can also be omitted and target CPU will use the default topology.: + + :: + + -smp 32,sockets=2,dies=2,modules=2,cores=2,threads=2,maxcpus=32,\ + l1d-cache=core,l1i-cache=core,l2-cache=core,l3-cache=die + The following sub-option defines a CPU topology hierarchy (2 sockets totally on the machine, 2 clusters per socket, 2 cores per cluster, 2 threads per core) for ARM virt machines which support sockets/clusters