From patchwork Thu May 30 19:27:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chang S. Bae" X-Patchwork-Id: 13680693 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B8011581E6; Thu, 30 May 2024 19:44:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717098248; cv=none; b=OU6wcZCtE/h15Wrvl4njNA560ILBxqmbz1V/TnAdCrYjyVcswJTZPc5upFys9DVZw48xidlmVzuBS/i2t7Z9jmevNy+lfVhVhqY9O0zYbxSdYydCL1TS/YgCWN1b8V+N++Kj8zzFA/EC9R8cbqPiBq9BMoEi50SMJGkRB+gZ8Vo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717098248; c=relaxed/simple; bh=CnFfuT0jo0I1WjsR5p2mZIX46ezAkhpyqYpDYsd/kAs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DXM0YcPhG42hlvv4NouJ7ilhwhRzKp6SCjNd2IlMXyHHF0wYZ1/y3SdABAndWWAbQMQFTizj0Ctl03bwSZ/cxlHfpxPWTLRWIm7DR0R60fJnKHS1H7CD5FE9M9vtdH2Gqnh0afAT4djD3TCvplWmOy83E3aWHCE7+07v/CYdGd0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RDxI+qfb; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RDxI+qfb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717098247; x=1748634247; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CnFfuT0jo0I1WjsR5p2mZIX46ezAkhpyqYpDYsd/kAs=; b=RDxI+qfb1A/bLnDjAQPAsz1pYqB9Q+eMcHTnJicx+ceiSzOV4qTs84Kb iWTVnJhrVhlzlgnM+T+O2eNlqghONJvlSRFEIOEWLdWg36AX6+KPAmSru hxm6U4r18vnI4sJPKq1Ie64XKCIrUZBUJ4+/jURmo34aaLwZQ0MjzvMJs 2Xust8N4ZH+nKQwzY4eS/3wm93b1CP8jcByh1LHGQ0Hq0NbbyD1Gh4NeA qgxpwIfVV/8TGEIJaX2Rbfz8jUojbAVQnra+bFO/X83n2tpF4etCI9LGE 7sKqUXuQdOgIdz+GOEYBqRgBmqmYYzOWt8jcLCjjLCCHXIDX2ofpyGlrf Q==; X-CSE-ConnectionGUID: fiwPgeySQOygrb9r82/YOA== X-CSE-MsgGUID: ITTbUd/KTiOBVU9uy97bgQ== X-IronPort-AV: E=McAfee;i="6600,9927,11088"; a="31143991" X-IronPort-AV: E=Sophos;i="6.08,202,1712646000"; d="scan'208";a="31143991" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2024 12:44:06 -0700 X-CSE-ConnectionGUID: zrMYwOzdQi26eBxHzSQIRQ== X-CSE-MsgGUID: ZF0bPGayRrKFF54U7vRZNw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,202,1712646000"; d="scan'208";a="36027622" Received: from chang-linux-3.sc.intel.com ([172.25.66.177]) by orviesa009.jf.intel.com with ESMTP; 30 May 2024 12:44:07 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, platform-driver-x86@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, tony.luck@intel.com, ashok.raj@intel.com, jithu.joseph@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH v3 1/3] x86/fpu: Rename fpu_reset_fpregs() to fpu_reset_fpstate_regs() Date: Thu, 30 May 2024 12:27:37 -0700 Message-Id: <20240530192739.172566-2-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240530192739.172566-1-chang.seok.bae@intel.com> References: <20240530192739.172566-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The term 'fpregs' typically refers to FPU registers. The function copies init values to the task's memory image, not hardware registers. Rename it to reflect what it does. Signed-off-by: Chang S. Bae --- V2 -> V3: New patch to avoids conflict with the upcoming new wrapper. --- arch/x86/kernel/fpu/core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 1209c7aebb21..2e6f43dfe98b 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -709,7 +709,7 @@ static inline void restore_fpregs_from_init_fpstate(u64 features_mask) /* * Reset current->fpu memory state to the init values. */ -static void fpu_reset_fpregs(void) +static void fpu_reset_fpstate_regs(void) { struct fpu *fpu = ¤t->thread.fpu; @@ -744,7 +744,7 @@ void fpu__clear_user_states(struct fpu *fpu) fpregs_lock(); if (!cpu_feature_enabled(X86_FEATURE_FPU)) { - fpu_reset_fpregs(); + fpu_reset_fpstate_regs(); fpregs_unlock(); return; } @@ -774,7 +774,7 @@ void fpu__clear_user_states(struct fpu *fpu) void fpu_flush_thread(void) { fpstate_reset(¤t->thread.fpu); - fpu_reset_fpregs(); + fpu_reset_fpstate_regs(); } /* * Load FPU context before returning to userspace. From patchwork Thu May 30 19:27:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chang S. Bae" X-Patchwork-Id: 13680694 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0454F15887B; Thu, 30 May 2024 19:44:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717098249; cv=none; b=FnogIsEP6cImgMihNpr9y9ZOUQyDFqyQ9XtBffr5AFCNyVppJwAUqrmFkjR+R/0cG0QWunhkWFUxC2ZVWReYbNBxOIsMKmmUUUbsEaIokQgfubuW7wpu3AfsoPRr+92Mw7bmU1QPOm0S5qMlGasAcgwVcgEB4HCYW94i2ymn5dw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717098249; c=relaxed/simple; bh=Ve5uS2VOqKr/0X4j3jr4Q5dfqnZMluXSSkgqpfK+d6A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=H75bIImaevGqTVGlFqnZnwHfjknSQU8o0NMhpennzz+v5xrzJS3R/gHbThqdf59CcAfC/zniXk4nOwr66uZy5PhO4/pWO8IvtnL4FlBSGj86B2m8D9jdXJcfmBCGS87KniVbYnELAVDtPkDwcgwO+LkV2VBTewBbrcq3wAq1u5c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=H4GL/ZIb; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="H4GL/ZIb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717098248; x=1748634248; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ve5uS2VOqKr/0X4j3jr4Q5dfqnZMluXSSkgqpfK+d6A=; b=H4GL/ZIbm6om8zVuuV8YHreWX/Vl7V82sa4eLRyhWCQ0kPcOG37BCIGr QQQQ8YsgeobACalW/GtV1BMFMBHdnSJFvT2XvvAzMtZX8l80mdOH+C9Bh n/ODdiz/p4/Ug0kU9It79W3lIn8kFVUh1ophESb9JW6MV8S9dy3JuEkij X1FuOa8+KRalAMU34n2QyDjebNxs2ak4rdTwWx4bA1iTuVysp1RpmfGvd 1fR/ujP7Q98PR/G+IUxocCCU4URk4TX0DO/IjonXwE5mYaC84VJ1Yj8Xl S13koN/3A1w6A5E98mwO/SwtYgNjsvlNFqqmQtev2ML55sn3AdnDjFLS4 A==; X-CSE-ConnectionGUID: 9enjT1ZERVCiigb7nI8XgQ== X-CSE-MsgGUID: 7W78a4BqQ2CES9eLsWrNRQ== X-IronPort-AV: E=McAfee;i="6600,9927,11088"; a="31143996" X-IronPort-AV: E=Sophos;i="6.08,202,1712646000"; d="scan'208";a="31143996" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2024 12:44:08 -0700 X-CSE-ConnectionGUID: 7HFhOa9MQuGNLDanNa1S9w== X-CSE-MsgGUID: SnnBpiY6TZOnajvzZ13Gfw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,202,1712646000"; d="scan'208";a="36027628" Received: from chang-linux-3.sc.intel.com ([172.25.66.177]) by orviesa009.jf.intel.com with ESMTP; 30 May 2024 12:44:08 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, platform-driver-x86@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, tony.luck@intel.com, ashok.raj@intel.com, jithu.joseph@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH v3 2/3] x86/fpu: Allow FPU users to initialize FPU state Date: Thu, 30 May 2024 12:27:38 -0700 Message-Id: <20240530192739.172566-3-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240530192739.172566-1-chang.seok.bae@intel.com> References: <20240530192739.172566-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The In-Field Scan (IFS) test [1] is a destructive process that overwrites the existing state to test the logic on the fly. As part of this test, the architectural state should be saved before the test begins and then restored upon completion. Unfortunately, AMX state is excluded from the scope of state recovery. This exclusion prohibits the IFS process from supporting any software context when running the test. The kernel generally runs with live user FPU states, including AMX. Provide fpu_reset_fpregs() for the IFS driver to reset FPU states, which is much simpler than specifying state components and is affordable in the non-critical path. This, along with kernel_fpu_begin(), can allow the IFS test to proceed. Alternatively, system administrators may attempt to mitigate this IFS issue by arranging some workloads not to run on CPUs selected for the tests. But, this approach is disruptive for managing large-scaled systems. [1]: https://docs.kernel.org/arch/x86/ifs.html Suggested-by: Dave Hansen Signed-off-by: Chang S. Bae --- V2 -> V3: Switch to a simpler solution and clarify the hardware problem (Dave Hansen). V1 -> V2: Revise the changelog (Dave and Ashok) The IFS Tech Paper [2] elaborates its purpose and the requirements of the context restoration after the scan test. Additionally, the necessity for AMX initialization is emphasized in the Intel Software Development Manual as of March 2024, in Section 18.2 of Vol.1. [2]: https://www.intel.com/content/www/us/en/content-details/822279/finding-faulty-components-in-a-live-fleet-environment.html --- arch/x86/include/asm/fpu/api.h | 2 ++ arch/x86/kernel/fpu/core.c | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/x86/include/asm/fpu/api.h b/arch/x86/include/asm/fpu/api.h index f86ad3335529..284304171003 100644 --- a/arch/x86/include/asm/fpu/api.h +++ b/arch/x86/include/asm/fpu/api.h @@ -179,4 +179,6 @@ extern long fpu_xstate_prctl(int option, unsigned long arg2); extern void fpu_idle_fpregs(void); +extern void fpu_reset_fpregs(void); + #endif /* _ASM_X86_FPU_API_H */ diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 2e6f43dfe98b..51d7689147f4 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -915,3 +915,14 @@ noinstr void fpu_idle_fpregs(void) __this_cpu_write(fpu_fpregs_owner_ctx, NULL); } } + +/* + * Allow FPU users to initialize the entire user FPU register state. The + * caller must invoke kernel_fpu_begin() beforehand. + */ +void fpu_reset_fpregs(void) +{ + WARN_ON_FPU(!this_cpu_read(in_kernel_fpu)); + restore_fpregs_from_fpstate(&init_fpstate, XFEATURE_MASK_USER_SUPPORTED); +} +EXPORT_SYMBOL_GPL(fpu_reset_fpregs); From patchwork Thu May 30 19:27:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chang S. Bae" X-Patchwork-Id: 13680695 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14BFC158A0D; Thu, 30 May 2024 19:44:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717098253; cv=none; b=XIM3vk6gSFctYVJD9VcLk3zFSQXvTCFyi6rjk7o4IG5P6fG67rCHgOR0lhIYYf6+xO/BL0GjaGz6NELKLIZPt8xsLvzQob0n01On16qClQ9VLNUJEtC6p8JlgnFn+yLDfsjei0hFhHSFQw5qLgVmZx65mP/2TJ/JCnqgXhye7FE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717098253; c=relaxed/simple; bh=Swv+nuFCro+i5I34h3+DF1nKDezzVeomXVrOHHcYQts=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gE7d842XP7ePbedXdrYbDHaoOfyeDH5o5bYPt8ktfPFSn1BKg3mVXbOXQT9nhmZwGdqVMKOqkKtWjZzhRbaa3+d88MOs+Pvi1NYaBxH5ur24YFSu/hB6pmPZwCLDtl/wk/PxSxeY4FVhVLqo6KtQ6T30yZvshXEvcqCwDFDMOP0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YbaAp5so; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YbaAp5so" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717098249; x=1748634249; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Swv+nuFCro+i5I34h3+DF1nKDezzVeomXVrOHHcYQts=; b=YbaAp5so237r19NgQ4XoeNejVu0BJm5Si0cw3P0L68NpFQ2/dfQih/Z1 6YHpLPfMeRnLX4XNuxZ/6MGEpLOSGrWjK1ZNyP+ajgy1qvBNeUAGZuK26 1NwRs01lGYXJsTAmrYHdbDmQ+zcZ+fsqX+cE0nFzSwlSLKBgsChAOYtNI s6Pj6EZ+xhzFdHuYxKT6T4CpVCRx5f80kDKDbwQ6brh3K3sjOCs7o1W25 ssDCVEbGBhkNiyCw/5a+1zhjAyUTxY6JH5ZYMTB14AMl95Jk4faivTBF7 y/CB9ayw3MA5Yw04ZzZMyzHh/dKAEJCjApjt2MSXbo8kpUihx7AOAB+3P g==; X-CSE-ConnectionGUID: Df67wi9iTTqt2bHbB14K/g== X-CSE-MsgGUID: PrnINVKETy+VJyQ5++Kf9A== X-IronPort-AV: E=McAfee;i="6600,9927,11088"; a="31144002" X-IronPort-AV: E=Sophos;i="6.08,202,1712646000"; d="scan'208";a="31144002" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2024 12:44:09 -0700 X-CSE-ConnectionGUID: iRRt9hkMRJmIPl5TPnGpjA== X-CSE-MsgGUID: yD599GxkQzaoqyI/8Q2KmQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,202,1712646000"; d="scan'208";a="36027635" Received: from chang-linux-3.sc.intel.com ([172.25.66.177]) by orviesa009.jf.intel.com with ESMTP; 30 May 2024 12:44:09 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, platform-driver-x86@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, tony.luck@intel.com, ashok.raj@intel.com, jithu.joseph@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH v3 3/3] platform/x86/intel/ifs: Initialize FPU states for the scan test Date: Thu, 30 May 2024 12:27:39 -0700 Message-Id: <20240530192739.172566-4-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240530192739.172566-1-chang.seok.bae@intel.com> References: <20240530192739.172566-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The In-Field Scan process aborts if AMX state is not in initialized state. Use fpu_reset_fpregs() to ensure AMX state is initialized before entering the rendezvous loop. Suggested-by: Dave Hansen Signed-off-by: Chang S. Bae Tested-by: Kuppuswamy Sathyanarayanan --- V2 -> V3: Use fpu_reset_user_fpregs(). Thanks to everyone who provided tags on previous versions. Due to the code change, I felt it necessary to revoke them, but the high-level logic remains the same. V1 -> V2: Revised the changelog (Ashok), added a space to the code comment (Ilpo), and included the header file explicitly (0-day). --- drivers/platform/x86/intel/ifs/ifs.h | 1 + drivers/platform/x86/intel/ifs/runtest.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h index 56b9f3e3cf76..5e7ba94b4054 100644 --- a/drivers/platform/x86/intel/ifs/ifs.h +++ b/drivers/platform/x86/intel/ifs/ifs.h @@ -129,6 +129,7 @@ */ #include #include +#include #define MSR_ARRAY_BIST 0x00000105 #define MSR_COPY_SCAN_HASHES 0x000002c2 diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c index 282e4bfe30da..68e128ea57ed 100644 --- a/drivers/platform/x86/intel/ifs/runtest.c +++ b/drivers/platform/x86/intel/ifs/runtest.c @@ -191,6 +191,10 @@ static int doscan(void *data) /* Only the first logical CPU on a core reports result */ first = cpumask_first(cpu_smt_mask(cpu)); + /* Prepare FPU state before entering the rendezvous loop */ + kernel_fpu_begin(); + fpu_reset_fpregs(); + wait_for_sibling_cpu(&scan_cpus_in, NSEC_PER_SEC); /* @@ -202,6 +206,9 @@ static int doscan(void *data) * are processed in a single pass) before it retires. */ wrmsrl(MSR_ACTIVATE_SCAN, params->activate->data); + + kernel_fpu_end(); + rdmsrl(MSR_SCAN_STATUS, status.data); trace_ifs_status(ifsd->cur_batch, start, stop, status.data);