From patchwork Fri May 31 11:53:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13681582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CED6C25B7C for ; Fri, 31 May 2024 11:54:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A6F2710E26D; Fri, 31 May 2024 11:54:07 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="jxkUY8s1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id ECD1410E3A2 for ; Fri, 31 May 2024 11:53:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717156428; x=1748692428; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=wW6wHbkN6a1BYklWavSPUeW3VpwrPhGBINDfuauuwQs=; b=jxkUY8s1/QeNwcT11iURardTpFj4kv5d161VhgjM573EXnFdEzs5h0pM zBHh8kCWFyndMLBsI1HsO7Khqn8lbJIMG4vRy6o2oyQDaYlsBNPdLolhy 8SyeMzJ5OB8WCzJEtbdsaQLYCmGuZIY6EdpGF1QXKQSd/RfIvJg4Fknge d/hVZZmGoMDRpxkEUt1YPYpi8s6I43WtmJ/s2ROEQMnNgxanNX5Q/+puR GzglvQ8TFw19QE0RIkBt/TI//TVkiVTSLy62YukiOJf48fmP2ADaZkOYo OGzu2sVaZqW1+mVOQs6Y0XV1orZ617cngUv0oMZ1SWKZp/ShuMwUllUMX A==; X-CSE-ConnectionGUID: BTeiqfDJSHiLmAGIT4UUvw== X-CSE-MsgGUID: aXYbVjrfQxa7B/g2fB0QDg== X-IronPort-AV: E=McAfee;i="6600,9927,11088"; a="13864654" X-IronPort-AV: E=Sophos;i="6.08,204,1712646000"; d="scan'208";a="13864654" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2024 04:53:48 -0700 X-CSE-ConnectionGUID: uQS74SaLQcihYtB1apOsdg== X-CSE-MsgGUID: J2x9tCxqTaOu0T0l0nlAiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,204,1712646000"; d="scan'208";a="36134997" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 31 May 2024 04:53:46 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 31 May 2024 14:53:45 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 1/7] drm/i915: Extract intel_pipe_crc_regs.h Date: Fri, 31 May 2024 14:53:36 +0300 Message-ID: <20240531115342.2763-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240531115342.2763-1-ville.syrjala@linux.intel.com> References: <20240531115342.2763-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The CRC registers are a pretty self contained bunch. Extract them to a separate header to declutter i915_reg.h. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- .../gpu/drm/i915/display/intel_display_irq.c | 1 + drivers/gpu/drm/i915/display/intel_pipe_crc.c | 1 + .../drm/i915/display/intel_pipe_crc_regs.h | 92 +++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 81 ---------------- 4 files changed, 94 insertions(+), 81 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 1674570dff1e..9c12cc0f2ed0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -18,6 +18,7 @@ #include "intel_fifo_underrun.h" #include "intel_gmbus.h" #include "intel_hotplug_irq.h" +#include "intel_pipe_crc_regs.h" #include "intel_pmdemand.h" #include "intel_psr.h" #include "intel_psr_regs.h" diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c index b3dcfee6ec0e..82ceede0b2b1 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c @@ -34,6 +34,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_pipe_crc.h" +#include "intel_pipe_crc_regs.h" static const char * const pipe_crc_sources[] = { [INTEL_PIPE_CRC_SOURCE_NONE] = "none", diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h new file mode 100644 index 000000000000..e684bc9ae1c0 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_PIPE_CRC_REGS_H__ +#define __INTEL_PIPE_CRC_REGS_H__ + +#include "intel_display_reg_defs.h" + +/* Pipe A CRC regs */ +#define _PIPE_CRC_CTL_A 0x60050 +#define PIPE_CRC_ENABLE REG_BIT(31) +/* skl+ source selection */ +#define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) +#define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) +#define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) +#define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) +#define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) +#define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) +#define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) +#define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) +#define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) +/* ivb+ source selection */ +#define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) +#define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) +#define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) +#define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) +/* ilk+ source selection */ +#define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) +#define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) +#define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) +#define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) +/* embedded DP port on the north display block */ +#define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) +#define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) +/* vlv source selection */ +#define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) +#define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) +#define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) +#define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) +/* with DP port the pipe source is invalid */ +#define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) +#define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) +#define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) +/* gen3+ source selection */ +#define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) +#define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) +#define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) +#define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) +/* with DP/TV port the pipe source is invalid */ +#define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) +#define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) +#define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) +#define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) +#define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) +/* gen2 doesn't have source selection bits */ +#define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) + +#define _PIPE_CRC_RES_1_A_IVB 0x60064 +#define _PIPE_CRC_RES_2_A_IVB 0x60068 +#define _PIPE_CRC_RES_3_A_IVB 0x6006c +#define _PIPE_CRC_RES_4_A_IVB 0x60070 +#define _PIPE_CRC_RES_5_A_IVB 0x60074 + +#define _PIPE_CRC_RES_RED_A 0x60060 +#define _PIPE_CRC_RES_GREEN_A 0x60064 +#define _PIPE_CRC_RES_BLUE_A 0x60068 +#define _PIPE_CRC_RES_RES1_A_I915 0x6006c +#define _PIPE_CRC_RES_RES2_A_G4X 0x60080 + +/* Pipe B CRC regs */ +#define _PIPE_CRC_RES_1_B_IVB 0x61064 +#define _PIPE_CRC_RES_2_B_IVB 0x61068 +#define _PIPE_CRC_RES_3_B_IVB 0x6106c +#define _PIPE_CRC_RES_4_B_IVB 0x61070 +#define _PIPE_CRC_RES_5_B_IVB 0x61074 + +#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) +#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) +#define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) +#define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) +#define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) +#define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) + +#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) +#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) +#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) +#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) +#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) + +#endif /* __INTEL_PIPE_CRC_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index be57812a6b07..b62adb1829f1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1069,87 +1069,6 @@ * Display engine regs */ -/* Pipe A CRC regs */ -#define _PIPE_CRC_CTL_A 0x60050 -#define PIPE_CRC_ENABLE REG_BIT(31) -/* skl+ source selection */ -#define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) -#define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) -#define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) -#define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) -#define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) -#define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) -#define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) -#define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) -#define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) -/* ivb+ source selection */ -#define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) -#define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) -#define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) -#define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) -/* ilk+ source selection */ -#define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) -#define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) -#define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) -#define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) -/* embedded DP port on the north display block */ -#define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) -#define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) -/* vlv source selection */ -#define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) -#define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) -#define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) -#define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) -/* with DP port the pipe source is invalid */ -#define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) -#define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) -#define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) -/* gen3+ source selection */ -#define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) -#define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) -#define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) -#define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) -/* with DP/TV port the pipe source is invalid */ -#define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) -#define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) -#define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) -#define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) -#define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) -/* gen2 doesn't have source selection bits */ -#define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) - -#define _PIPE_CRC_RES_1_A_IVB 0x60064 -#define _PIPE_CRC_RES_2_A_IVB 0x60068 -#define _PIPE_CRC_RES_3_A_IVB 0x6006c -#define _PIPE_CRC_RES_4_A_IVB 0x60070 -#define _PIPE_CRC_RES_5_A_IVB 0x60074 - -#define _PIPE_CRC_RES_RED_A 0x60060 -#define _PIPE_CRC_RES_GREEN_A 0x60064 -#define _PIPE_CRC_RES_BLUE_A 0x60068 -#define _PIPE_CRC_RES_RES1_A_I915 0x6006c -#define _PIPE_CRC_RES_RES2_A_G4X 0x60080 - -/* Pipe B CRC regs */ -#define _PIPE_CRC_RES_1_B_IVB 0x61064 -#define _PIPE_CRC_RES_2_B_IVB 0x61068 -#define _PIPE_CRC_RES_3_B_IVB 0x6106c -#define _PIPE_CRC_RES_4_B_IVB 0x61070 -#define _PIPE_CRC_RES_5_B_IVB 0x61074 - -#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) -#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) -#define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) -#define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) -#define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) -#define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) - -#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) -#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) -#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) -#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) -#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) - /* Pipe/transcoder A timing regs */ #define _TRANS_HTOTAL_A 0x60000 #define HTOTAL_MASK REG_GENMASK(31, 16) From patchwork Fri May 31 11:53:37 2024 Content-Type: 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ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2024 04:53:51 -0700 X-CSE-ConnectionGUID: sj4FvnVTRxOrFMSHdzVLfg== X-CSE-MsgGUID: 0CGXfY8RTq6tecAdXpOwKg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,204,1712646000"; d="scan'208";a="36134998" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 31 May 2024 04:53:48 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 31 May 2024 14:53:47 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/7] drm/i915: Switch PIPE_CRC_RES_*_IVB to _MMIO_PIPE() Date: Fri, 31 May 2024 14:53:37 +0300 Message-ID: <20240531115342.2763-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240531115342.2763-1-ville.syrjala@linux.intel.com> References: <20240531115342.2763-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä PIPE_CRC_RES_*_IVB are proper pipe registers, and only valid for IVB+ where pipe register blocks are equally spaced, so we can switch from _MMIO_TRANS2() to the simpler _MMIO_PIPE() for these. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 12 ++++++------ drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h | 10 +++++----- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 9c12cc0f2ed0..7db87dfcb12a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -357,7 +357,7 @@ static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) { display_pipe_crc_irq_handler(dev_priv, pipe, - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), 0, 0, 0, 0); } @@ -365,11 +365,11 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) { display_pipe_crc_irq_handler(dev_priv, pipe, - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(dev_priv, pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(dev_priv, pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(dev_priv, pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(dev_priv, pipe))); + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); } static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h index e684bc9ae1c0..66520c97bf1e 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -77,11 +77,11 @@ #define _PIPE_CRC_RES_5_B_IVB 0x61074 #define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) -#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) -#define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) -#define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) -#define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) -#define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) +#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) +#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) +#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) +#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) +#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) #define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) #define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) From patchwork Fri May 31 11:53:38 2024 Content-Type: text/plain; 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31 May 2024 04:53:53 -0700 X-CSE-ConnectionGUID: Inc9VYKUR5eyJeBwtC1zdw== X-CSE-MsgGUID: owVmcwHRRMurcGbh0be76w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,204,1712646000"; d="scan'208";a="36134999" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 31 May 2024 04:53:51 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 31 May 2024 14:53:50 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 3/7] drm/i915: Regroup pipe CRC regs Date: Fri, 31 May 2024 14:53:38 +0300 Message-ID: <20240531115342.2763-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240531115342.2763-1-ville.syrjala@linux.intel.com> References: <20240531115342.2763-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Put all the definitions related to a single pipe CRC register in one place, instead of the current approach where things are spread all over the place. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- .../drm/i915/display/intel_pipe_crc_regs.h | 43 ++++++++++--------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h index 66520c97bf1e..a1217a4d6f2e 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -8,8 +8,8 @@ #include "intel_display_reg_defs.h" -/* Pipe A CRC regs */ #define _PIPE_CRC_CTL_A 0x60050 +#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) #define PIPE_CRC_ENABLE REG_BIT(31) /* skl+ source selection */ #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) @@ -57,36 +57,39 @@ /* gen2 doesn't have source selection bits */ #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) -#define _PIPE_CRC_RES_1_A_IVB 0x60064 -#define _PIPE_CRC_RES_2_A_IVB 0x60068 -#define _PIPE_CRC_RES_3_A_IVB 0x6006c -#define _PIPE_CRC_RES_4_A_IVB 0x60070 -#define _PIPE_CRC_RES_5_A_IVB 0x60074 - #define _PIPE_CRC_RES_RED_A 0x60060 +#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) + #define _PIPE_CRC_RES_GREEN_A 0x60064 +#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) + #define _PIPE_CRC_RES_BLUE_A 0x60068 +#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) + #define _PIPE_CRC_RES_RES1_A_I915 0x6006c +#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) + #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 +#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) -/* Pipe B CRC regs */ +#define _PIPE_CRC_RES_1_A_IVB 0x60064 #define _PIPE_CRC_RES_1_B_IVB 0x61064 -#define _PIPE_CRC_RES_2_B_IVB 0x61068 -#define _PIPE_CRC_RES_3_B_IVB 0x6106c -#define _PIPE_CRC_RES_4_B_IVB 0x61070 -#define _PIPE_CRC_RES_5_B_IVB 0x61074 - -#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) + +#define _PIPE_CRC_RES_2_A_IVB 0x60068 +#define _PIPE_CRC_RES_2_B_IVB 0x61068 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) + +#define _PIPE_CRC_RES_3_A_IVB 0x6006c +#define _PIPE_CRC_RES_3_B_IVB 0x6106c #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) + +#define _PIPE_CRC_RES_4_A_IVB 0x60070 +#define _PIPE_CRC_RES_4_B_IVB 0x61070 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) + +#define _PIPE_CRC_RES_5_A_IVB 0x60074 +#define _PIPE_CRC_RES_5_B_IVB 0x61074 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) -#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) -#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) -#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) -#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) -#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) - #endif /* __INTEL_PIPE_CRC_REGS_H__ */ From patchwork Fri May 31 11:53:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13681585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5404BC27C4F for ; Fri, 31 May 2024 11:54:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF84D10E4E9; Fri, 31 May 2024 11:54:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ij4Oys9p"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0FA9710E3A2 for ; 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31 May 2024 04:53:56 -0700 X-CSE-ConnectionGUID: +7x0HSgnSSG5eRD/QrKRww== X-CSE-MsgGUID: TrBgeOXTRW+vvfanSlzqpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,204,1712646000"; d="scan'208";a="36135000" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 31 May 2024 04:53:54 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 31 May 2024 14:53:53 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 4/7] drm/i915: Add a separate defintiion for PIPE_CRC_RES_HSW Date: Fri, 31 May 2024 14:53:39 +0300 Message-ID: <20240531115342.2763-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240531115342.2763-1-ville.syrjala@linux.intel.com> References: <20240531115342.2763-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä On hsw+ we only have one CRC result registers, instead of the five we have on ivb, and some of the others have been repurposed to serve other CRC related purposed. Since the hsw+ vs. pre-hsw register operate quite diffently let's add a separate definition for the hsw+ variant to make the situation a bit more clear. Also since we only use this from a hsw+ codepath there is no real benefit to be had with reusing the ivb register definition. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +- drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 7db87dfcb12a..d2d70b81aef9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -357,7 +357,7 @@ static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) { display_pipe_crc_irq_handler(dev_priv, pipe, - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_HSW(pipe)), 0, 0, 0, 0); } diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h index a1217a4d6f2e..d06ff3516dbc 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -92,4 +92,9 @@ #define _PIPE_CRC_RES_5_B_IVB 0x61074 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) +/* hsw+ */ +#define _PIPE_CRC_RES_A_HSW 0x60064 +#define _PIPE_CRC_RES_B_HSW 0x61064 +#define PIPE_CRC_RES_HSW(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW) + #endif /* __INTEL_PIPE_CRC_REGS_H__ */ From patchwork Fri May 31 11:53:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13681586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BFB81C25B75 for ; Fri, 31 May 2024 11:54:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 14DE110E546; Fri, 31 May 2024 11:54:20 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="IdTEmUx3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id C31E110E00D for ; Fri, 31 May 2024 11:53:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717156439; x=1748692439; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=K60+2kWqjaW5kWugx/vd77s9IV9QfSpMBgF5CKXoa6A=; b=IdTEmUx3xSK+BGYYHt5b41I88mZH+HOy5hzFN7ULbhWEzshkt7TZPc4W a/SRbd7KNLajC7VODX4/QH3jKuxzZv5ElGr/K4b7+UcPCDCuyOn3FZAhT 1kQSHBtdzjh78A1OU5oORqGFFHnPG5ildKyFA4zEa0NG3ziF7eVyZC4kf uG1k9izMDEji4Bclmbr5ZfL/HL++71yJYCV0KngYZRVfIRUd2v7hzHo78 RnuK9Zo7XrZxsCU0UJWuYq4NRbqIcUPBUiBZ9nx2S51RYPY1dKHeCNFac 4h2yFlho4l5Z3KDIH2/cjd6E5JcJz9dkbOzlkxPv0H1v341Er8/mFPnz7 g==; X-CSE-ConnectionGUID: p1GdWQV5T52UVsH+xox5YQ== X-CSE-MsgGUID: zFBCitDxTOq7ZUv1rvs55w== X-IronPort-AV: E=McAfee;i="6600,9927,11088"; a="13864667" X-IronPort-AV: E=Sophos;i="6.08,204,1712646000"; d="scan'208";a="13864667" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2024 04:53:59 -0700 X-CSE-ConnectionGUID: h0eqjWsRSs6qRLJKen9OLA== X-CSE-MsgGUID: Vwr/iJZoTYC7MJjzuH1NeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,204,1712646000"; d="scan'208";a="36135005" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 31 May 2024 04:53:57 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 31 May 2024 14:53:56 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 5/7] drm/i915: Document which platforms have which CRC registers Date: Fri, 31 May 2024 14:53:40 +0300 Message-ID: <20240531115342.2763-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240531115342.2763-1-ville.syrjala@linux.intel.com> References: <20240531115342.2763-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Sprinkle some comments around to indicate which CRC registers are valid for which platforms. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h index d06ff3516dbc..4f4bf51e1940 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -66,28 +66,33 @@ #define _PIPE_CRC_RES_BLUE_A 0x60068 #define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) -#define _PIPE_CRC_RES_RES1_A_I915 0x6006c +#define _PIPE_CRC_RES_RES1_A_I915 0x6006c /* i915+ */ #define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) -#define _PIPE_CRC_RES_RES2_A_G4X 0x60080 +#define _PIPE_CRC_RES_RES2_A_G4X 0x60080 /* g4x+ */ #define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) +/* ivb */ #define _PIPE_CRC_RES_1_A_IVB 0x60064 #define _PIPE_CRC_RES_1_B_IVB 0x61064 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) +/* ivb */ #define _PIPE_CRC_RES_2_A_IVB 0x60068 #define _PIPE_CRC_RES_2_B_IVB 0x61068 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) +/* ivb */ #define _PIPE_CRC_RES_3_A_IVB 0x6006c #define _PIPE_CRC_RES_3_B_IVB 0x6106c #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) +/* ivb */ #define _PIPE_CRC_RES_4_A_IVB 0x60070 #define _PIPE_CRC_RES_4_B_IVB 0x61070 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) +/* ivb */ #define _PIPE_CRC_RES_5_A_IVB 0x60074 #define _PIPE_CRC_RES_5_B_IVB 0x61074 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) From patchwork Fri May 31 11:53:41 2024 Content-Type: text/plain; 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31 May 2024 04:54:02 -0700 X-CSE-ConnectionGUID: 8SGtFjnfRpu9RB0hhkGIDg== X-CSE-MsgGUID: lsfdGkbyR1i6BF2n9UAt+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,204,1712646000"; d="scan'208";a="36135007" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 31 May 2024 04:53:59 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 31 May 2024 14:53:58 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 6/7] drm/i915: Define the PIPE_CRC_EXP registers Date: Fri, 31 May 2024 14:53:41 +0300 Message-ID: <20240531115342.2763-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240531115342.2763-1-ville.syrjala@linux.intel.com> References: <20240531115342.2763-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä I need a scratch register which fill the following requirements: - can be accessed via DSB - all the bits can be read/written - no serious side effects So far the only thing I could think of is the "expected CRC" register. Add the definition so I can use it. While I only need the hsw+ variant currently, let's define the older variants as well for completeness. Signed-off-by: Ville Syrjälä Acked-by: Jani Nikula --- .../drm/i915/display/intel_pipe_crc_regs.h | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h index 4f4bf51e1940..383910a785f6 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -56,6 +56,24 @@ #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) /* gen2 doesn't have source selection bits */ #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) +#define PIPE_CRC_EXP_RED_MASK REG_BIT(22, 0) /* pre-ivb */ +#define PIPE_CRC_EXP_1_MASK_IVB REG_BIT(22, 0) /* ivb */ + +#define _PIPE_CRC_EXP_GREEN_A 0x60054 +#define PIPE_CRC_EXP_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_GREEN_A) +#define PIPE_CRC_EXP_GREEN_MASK REG_BIT(22, 0) /* pre-ivb */ + +#define _PIPE_CRC_EXP_BLUE_A 0x60058 +#define PIPE_CRC_EXP_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_BLUE_A) +#define PIPE_CRC_EXP_BLUE_MASK REG_BIT(22, 0) /* pre-ivb */ + +#define _PIPE_CRC_EXP_RES1_A_I915 0x6005c /* i915+ */ +#define PIPE_CRC_EXP_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES1_A_I915) +#define PIPE_CRC_EXP_RES1_MASK REG_BIT(22, 0) /* pre-ivb */ + +#define _PIPE_CRC_EXP_RES2_A_G4X 0x60080 /* g4x+ */ +#define PIPE_CRC_EXP_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES2_A_G4X) +#define PIPE_CRC_EXP_RES2_MASK REG_BIT(22, 0) /* pre-ivb */ #define _PIPE_CRC_RES_RED_A 0x60060 #define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) @@ -72,6 +90,30 @@ #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 /* g4x+ */ #define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) +/* ivb */ +#define _PIPE_CRC_EXP_2_A_IVB 0x60054 +#define _PIPE_CRC_EXP_2_B_IVB 0x61054 +#define PIPE_CRC_EXP_2_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB) +#define PIPE_CRC_EXP_2_MASK_IVB REG_BIT(22, 0) /* ivb */ + +/* ivb */ +#define _PIPE_CRC_EXP_3_A_IVB 0x60058 +#define _PIPE_CRC_EXP_3_B_IVB 0x61058 +#define PIPE_CRC_EXP_3_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_3_A_IVB, _PIPE_CRC_EXP_3_B_IVB) +#define PIPE_CRC_EXP_3_MASK_IVB REG_BIT(22, 0) /* ivb */ + +/* ivb */ +#define _PIPE_CRC_EXP_4_A_IVB 0x6005c +#define _PIPE_CRC_EXP_4_B_IVB 0x6105c +#define PIPE_CRC_EXP_4_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB) +#define PIPE_CRC_EXP_4_MASK_IVB REG_BIT(22, 0) /* ivb */ + +/* ivb */ +#define _PIPE_CRC_EXP_5_A_IVB 0x60060 +#define _PIPE_CRC_EXP_5_B_IVB 0x61060 +#define PIPE_CRC_EXP_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB) +#define PIPE_CRC_EXP_5_MASK_IVB REG_BIT(22, 0) /* ivb */ + /* ivb */ #define _PIPE_CRC_RES_1_A_IVB 0x60064 #define _PIPE_CRC_RES_1_B_IVB 0x61064 @@ -97,6 +139,11 @@ #define _PIPE_CRC_RES_5_B_IVB 0x61074 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) +/* hsw+ */ +#define _PIPE_CRC_EXP_A_HSW 0x60054 +#define _PIPE_CRC_EXP_B_HSW 0x61054 +#define PIPE_CRC_EXP_HSW(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW) + /* hsw+ */ #define _PIPE_CRC_RES_A_HSW 0x60064 #define _PIPE_CRC_RES_B_HSW 0x61064 From patchwork Fri May 31 11:53:42 2024 Content-Type: text/plain; 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31 May 2024 04:54:04 -0700 X-CSE-ConnectionGUID: LnYjr6iMT8iGvI9Brk0njA== X-CSE-MsgGUID: 9GSHGHsORA2biCUtv+ptfg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,204,1712646000"; d="scan'208";a="36135008" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 31 May 2024 04:54:02 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 31 May 2024 14:54:01 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 7/7] drm/i915: Protect CRC reg macro arguments for consistency Date: Fri, 31 May 2024 14:53:42 +0300 Message-ID: <20240531115342.2763-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240531115342.2763-1-ville.syrjala@linux.intel.com> References: <20240531115342.2763-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä It's probably a good idea to start protecting all macro arguments to avoid any cargo-cult mistakes when people go looking for examples of how to define these things. Signed-off-by: Ville Syrjälä --- .../drm/i915/display/intel_pipe_crc_regs.h | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h index 383910a785f6..4e65f51d34e6 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -9,7 +9,7 @@ #include "intel_display_reg_defs.h" #define _PIPE_CRC_CTL_A 0x60050 -#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) +#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_CTL_A) #define PIPE_CRC_ENABLE REG_BIT(31) /* skl+ source selection */ #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) @@ -76,19 +76,19 @@ #define PIPE_CRC_EXP_RES2_MASK REG_BIT(22, 0) /* pre-ivb */ #define _PIPE_CRC_RES_RED_A 0x60060 -#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) +#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RED_A) #define _PIPE_CRC_RES_GREEN_A 0x60064 -#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) +#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_GREEN_A) #define _PIPE_CRC_RES_BLUE_A 0x60068 -#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) +#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_BLUE_A) #define _PIPE_CRC_RES_RES1_A_I915 0x6006c /* i915+ */ -#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) +#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_A_I915) #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 /* g4x+ */ -#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) +#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A_G4X) /* ivb */ #define _PIPE_CRC_EXP_2_A_IVB 0x60054 @@ -117,36 +117,36 @@ /* ivb */ #define _PIPE_CRC_RES_1_A_IVB 0x60064 #define _PIPE_CRC_RES_1_B_IVB 0x61064 -#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) +#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) /* ivb */ #define _PIPE_CRC_RES_2_A_IVB 0x60068 #define _PIPE_CRC_RES_2_B_IVB 0x61068 -#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) +#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) /* ivb */ #define _PIPE_CRC_RES_3_A_IVB 0x6006c #define _PIPE_CRC_RES_3_B_IVB 0x6106c -#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) +#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) /* ivb */ #define _PIPE_CRC_RES_4_A_IVB 0x60070 #define _PIPE_CRC_RES_4_B_IVB 0x61070 -#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) +#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) /* ivb */ #define _PIPE_CRC_RES_5_A_IVB 0x60074 #define _PIPE_CRC_RES_5_B_IVB 0x61074 -#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) +#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) /* hsw+ */ #define _PIPE_CRC_EXP_A_HSW 0x60054 #define _PIPE_CRC_EXP_B_HSW 0x61054 -#define PIPE_CRC_EXP_HSW(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW) +#define PIPE_CRC_EXP_HSW(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW) /* hsw+ */ #define _PIPE_CRC_RES_A_HSW 0x60064 #define _PIPE_CRC_RES_B_HSW 0x61064 -#define PIPE_CRC_RES_HSW(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW) +#define PIPE_CRC_RES_HSW(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW) #endif /* __INTEL_PIPE_CRC_REGS_H__ */