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Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Krzysztof Kozlowski , Julien Panis , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717411855; l=2060; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=IZPrvRPbGNSCghjb/r1UV5NLYTSYSWHR7o/UY4dQ/l8=; b=H0YGfuOx97A32AYKnSb54my+ipnwNHN3gyXGwn1w1+Gowhq81ksSoJwKx5VAgIuDuFdYqw47N vgPxSRvm45PD22rChAtElT+XIOrWc0ylFv5Ds4cGkpg6i0UnRDm/xCa X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= Fix a thermal zone name for consistency with the other SoCs: MFG contains GPU, the latter is more specific and must be used here. The naming must be fixed "atomically" so compilation does not break. As a result, the change is made in the dt-bindings and in the LVTS driver within a single commit, despite the checkpatch warning. The definition can be safely modified here because it is used only in the LVTS driver, which is modified accordingly, and has not yet been included in a released kernel. Fixes: a2ca202350f9 ("dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for MT8186") Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley Signed-off-by: Julien Panis --- drivers/thermal/mediatek/lvts_thermal.c | 2 +- include/dt-bindings/thermal/mediatek,lvts-thermal.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index 0bb3a495b56e..506eed52db1e 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -1436,7 +1436,7 @@ static const struct lvts_ctrl_data mt8186_lvts_data_ctrl[] = { .cal_offsets = { 29, 30, 31 } }, { .dt_id = MT8186_ADSP, .cal_offsets = { 34, 35, 28 } }, - { .dt_id = MT8186_MFG, + { .dt_id = MT8186_GPU, .cal_offsets = { 39, 32, 33 } } }, VALID_SENSOR_MAP(1, 1, 1, 0), diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/dt-bindings/thermal/mediatek,lvts-thermal.h index bf95309d2525..85d25b4d726d 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -24,7 +24,7 @@ #define MT8186_BIG_CPU1 5 #define MT8186_NNA 6 #define MT8186_ADSP 7 -#define MT8186_MFG 8 +#define MT8186_GPU 8 #define MT8188_MCU_LITTLE_CPU0 0 #define MT8188_MCU_LITTLE_CPU1 1 From patchwork Mon Jun 3 10:50:49 2024 Content-Type: text/plain; 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Mon, 03 Jun 2024 03:51:01 -0700 (PDT) From: Julien Panis Date: Mon, 03 Jun 2024 12:50:49 +0200 Subject: [PATCH v7 2/6] dt-bindings: thermal: mediatek: Fix thermal zone definitions for MT8188 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240603-mtk-thermal-mt818x-dtsi-v7-2-8c8e3c7a3643@baylibre.com> References: <20240603-mtk-thermal-mt818x-dtsi-v7-0-8c8e3c7a3643@baylibre.com> In-Reply-To: <20240603-mtk-thermal-mt818x-dtsi-v7-0-8c8e3c7a3643@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Daniel Lezcano , Nicolas Pitre , "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Krzysztof Kozlowski , Julien Panis , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717411855; l=2836; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=ZqI2EmSTiCeQkIQ029juObOniGHTqqS9zskZ5qN+P1Y=; b=Tw82fn/ZAXPeDohLJa8RKt2pEsOcZr9bdvgVK6hzP3QqxnhsrLDnsX2AgTmAaCXFSECZy0zTP oMSA7L28yq2DyzTWri20+vWMBaXVEEvLL9M55ZVVNtlWFMvGysf0qwK X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= Fix thermal zone names for consistency with the other SoCs: - GPU0 must be used as the first GPU item. - SOCx deal with audio DSP, video, and infra subsystems. The naming must be fixed "atomically" so compilation does not break. As a result, the change is made in the dt-bindings and in the LVTS driver within a single commit, despite the checkpatch warning. The definitions can be safely modified here because they are used only in the LVTS driver, which is modified accordingly, and have not yet been included in a released kernel. Fixes: 78c88534e5e1 ("dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for MT8188") Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley Signed-off-by: Julien Panis --- drivers/thermal/mediatek/lvts_thermal.c | 10 +++++----- include/dt-bindings/thermal/mediatek,lvts-thermal.h | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index 506eed52db1e..89fb92666b81 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -1487,11 +1487,11 @@ static const struct lvts_ctrl_data mt8188_lvts_ap_data_ctrl[] = { }, { .lvts_sensor = { - { .dt_id = MT8188_AP_GPU1, + { .dt_id = MT8188_AP_GPU0, .cal_offsets = { 43, 44, 45 } }, - { .dt_id = MT8188_AP_GPU2, + { .dt_id = MT8188_AP_GPU1, .cal_offsets = { 46, 47, 48 } }, - { .dt_id = MT8188_AP_SOC1, + { .dt_id = MT8188_AP_ADSP, .cal_offsets = { 49, 50, 51 } }, }, VALID_SENSOR_MAP(1, 1, 1, 0), @@ -1500,9 +1500,9 @@ static const struct lvts_ctrl_data mt8188_lvts_ap_data_ctrl[] = { }, { .lvts_sensor = { - { .dt_id = MT8188_AP_SOC2, + { .dt_id = MT8188_AP_VDO, .cal_offsets = { 52, 53, 54 } }, - { .dt_id = MT8188_AP_SOC3, + { .dt_id = MT8188_AP_INFRA, .cal_offsets = { 55, 56, 57 } }, }, VALID_SENSOR_MAP(1, 1, 0, 0), diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/dt-bindings/thermal/mediatek,lvts-thermal.h index 85d25b4d726d..ddc7302a510a 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -34,11 +34,11 @@ #define MT8188_MCU_BIG_CPU1 5 #define MT8188_AP_APU 0 -#define MT8188_AP_GPU1 1 -#define MT8188_AP_GPU2 2 -#define MT8188_AP_SOC1 3 -#define MT8188_AP_SOC2 4 -#define MT8188_AP_SOC3 5 +#define MT8188_AP_GPU0 1 +#define MT8188_AP_GPU1 2 +#define MT8188_AP_ADSP 3 +#define MT8188_AP_VDO 4 +#define MT8188_AP_INFRA 5 #define MT8188_AP_CAM1 6 #define MT8188_AP_CAM2 7 From patchwork Mon Jun 3 10:50:50 2024 Content-Type: text/plain; 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Mon, 03 Jun 2024 03:51:03 -0700 (PDT) From: Julien Panis Date: Mon, 03 Jun 2024 12:50:50 +0200 Subject: [PATCH v7 3/6] arm64: dts: mediatek: mt8186: add lvts definitions Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240603-mtk-thermal-mt818x-dtsi-v7-3-8c8e3c7a3643@baylibre.com> References: <20240603-mtk-thermal-mt818x-dtsi-v7-0-8c8e3c7a3643@baylibre.com> In-Reply-To: <20240603-mtk-thermal-mt818x-dtsi-v7-0-8c8e3c7a3643@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Daniel Lezcano , Nicolas Pitre , "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Krzysztof Kozlowski , Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717411855; l=1717; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=ZXPmUPXXFa1JCVfBMk9FrptEjzZlcdWN0z1cSMSnOwA=; b=Kt+1V0UhcrpohxTAKZFUE6vVY7Di9DK+ytngdabEc9EgSfLdYOSvG84ZuIRjZE5ntcFnGkiTk 2NXaGqDdubOAar0nMdkuK90dJZZMBlW7wdgSxz2A3s1DmE7244C82G2 X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= From: Nicolas Pitre Values extracted from vendor source tree. Signed-off-by: Nicolas Pitre Link: https://lore.kernel.org/r/20240402032729.2736685-8-nico@fluxnic.net [Angelo: Fixed validation and quality issues] Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Julien Panis --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 4763ed5dc86c..caec83f5eece 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1361,6 +1361,17 @@ spi0: spi@1100a000 { status = "disabled"; }; + lvts: thermal-sensor@1100b000 { + compatible = "mediatek,mt8186-lvts"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + resets = <&infracfg_ao MT8186_INFRA_THERMAL_CTRL_RST>; + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; + #thermal-sensor-cells = <1>; + }; + pwm0: pwm@1100e000 { compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; reg = <0 0x1100e000 0 0x1000>; @@ -1676,6 +1687,14 @@ efuse: efuse@11cb0000 { #address-cells = <1>; #size-cells = <1>; + lvts_efuse_data1: lvts1-calib@1cc { + reg = <0x1cc 0x14>; + }; + + lvts_efuse_data2: lvts2-calib@2f8 { + reg = <0x2f8 0x14>; + }; + gpu_speedbin: gpu-speedbin@59c { reg = <0x59c 0x4>; bits = <0 3>; From patchwork Mon Jun 3 10:50:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Panis X-Patchwork-Id: 13683615 X-Patchwork-Delegate: daniel.lezcano@linaro.org Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32F7084D37 for ; Mon, 3 Jun 2024 10:51:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; 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Mon, 03 Jun 2024 03:51:05 -0700 (PDT) Received: from [127.0.1.1] ([84.102.31.231]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42133227f8asm95372535e9.19.2024.06.03.03.51.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 03:51:05 -0700 (PDT) From: Julien Panis Date: Mon, 03 Jun 2024 12:50:51 +0200 Subject: [PATCH v7 4/6] arm64: dts: mediatek: mt8186: add default thermal zones Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240603-mtk-thermal-mt818x-dtsi-v7-4-8c8e3c7a3643@baylibre.com> References: <20240603-mtk-thermal-mt818x-dtsi-v7-0-8c8e3c7a3643@baylibre.com> In-Reply-To: <20240603-mtk-thermal-mt818x-dtsi-v7-0-8c8e3c7a3643@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Daniel Lezcano , Nicolas Pitre , "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Krzysztof Kozlowski , Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717411855; l=7860; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=lPgsulGv9GpCiinxcEjh9k1yG/tfMpaueb3shauQV5g=; b=p+SoN5gmJzAKZ6pn3yzDgBwHeGquM4KfP3Y+wTQCNv9PggaHPFLkV0/uxu/EfpITVJw2EB6l9 8crXgGllKsrCPdaxkmqgGmxYdoLcEYENs0/TOs2DxoloQUdTpDp0czR X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= From: Nicolas Pitre Inspired by the vendor kernel but adapted to the upstream thermal driver version. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Pitre Signed-off-by: Julien Panis --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 297 +++++++++++++++++++++++++++++++ 1 file changed, 297 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index caec83f5eece..95fe5a05f0d7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -13,6 +13,8 @@ #include #include #include +#include +#include / { compatible = "mediatek,mt8186"; @@ -2197,4 +2199,299 @@ larb19: smi@1c10f000 { power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; }; }; + + thermal_zones: thermal-zones { + cpu-little0-thermal { + polling-delay = <1000>; + polling-delay-passive = <150>; + thermal-sensors = <&lvts MT8186_LITTLE_CPU0>; + + trips { + cpu_little0_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_little0_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_little0_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_little0_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little1-thermal { + polling-delay = <1000>; + polling-delay-passive = <150>; + thermal-sensors = <&lvts MT8186_LITTLE_CPU1>; + + trips { + cpu_little1_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_little1_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_little1_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_little1_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little2-thermal { + polling-delay = <1000>; + polling-delay-passive = <150>; + thermal-sensors = <&lvts MT8186_LITTLE_CPU2>; + + trips { + cpu_little2_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_little2_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_little2_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_little2_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cam-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts MT8186_CAM>; + + trips { + cam_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cam_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cam_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nna-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts MT8186_NNA>; + + trips { + nna_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + nna_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + nna_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + adsp-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts MT8186_ADSP>; + + trips { + adsp_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + adsp_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + adsp_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts MT8186_GPU>; + + trips { + gpu_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpu_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-big0-thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&lvts MT8186_BIG_CPU0>; + + trips { + cpu_big0_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_big0_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_big0_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_big0_alert0>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-big1-thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&lvts MT8186_BIG_CPU1>; + + trips { + cpu_big1_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_big1_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_big1_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_big1_alert0>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; }; From patchwork Mon Jun 3 10:50:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Panis X-Patchwork-Id: 13683616 X-Patchwork-Delegate: daniel.lezcano@linaro.org Received: from mail-lj1-f176.google.com (mail-lj1-f176.google.com [209.85.208.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DB5484FAA for ; Mon, 3 Jun 2024 10:51:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717411871; cv=none; b=ss53jIt3heDeA7NvPd9AJnUdlKLn701eKYJxr5Y0+n3W9AzttT3AEJNNbqKydpPvgWo3xkcocwsrcI1c7mWZEVqWPJ+b4jTZkd8JM7vmy/4hHoGGfKmGrPSE4TtOoLPVqtUWx7KJuDqlHVo7XH/GUf05skKdsKM5eEFMD3ZKPtQ= ARC-Message-Signature: i=1; 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Mon, 03 Jun 2024 03:51:07 -0700 (PDT) From: Julien Panis Date: Mon, 03 Jun 2024 12:50:52 +0200 Subject: [PATCH v7 5/6] arm64: dts: mediatek: mt8188: add lvts definitions Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240603-mtk-thermal-mt818x-dtsi-v7-5-8c8e3c7a3643@baylibre.com> References: <20240603-mtk-thermal-mt818x-dtsi-v7-0-8c8e3c7a3643@baylibre.com> In-Reply-To: <20240603-mtk-thermal-mt818x-dtsi-v7-0-8c8e3c7a3643@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Daniel Lezcano , Nicolas Pitre , "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Krzysztof Kozlowski , Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717411855; l=2943; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=a+N8mpao7+QeANDnMFXYaOS/6MVQmW9fHDWrXbASce8=; b=nPcjEmvEDQuDtpxAh7mvZz2ffsRr5fj3qPdL3X5DhgO6KVn3q8ZDpj1hjVdfG5wxvVClk3weC QqeeaNkkDhlBBnKbra1B7aOJADUxtXQsEYidq8Xne/9nTcyJKSxyLXL X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= From: Nicolas Pitre Various values extracted from the vendor's kernel driver. Signed-off-by: Nicolas Pitre Link: https://lore.kernel.org/r/20240402032729.2736685-14-nico@fluxnic.net [Angelo: Fixed wrong nvmem-cell-names] Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Julien Panis --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 29d012d28edb..02786fe9891b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8188"; @@ -464,6 +465,7 @@ infracfg_ao: syscon@10001000 { compatible = "mediatek,mt8188-infracfg-ao", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; pericfg: syscon@10003000 { @@ -937,6 +939,17 @@ spi0: spi@1100a000 { status = "disabled"; }; + lvts_ap: thermal-sensor@1100b000 { + compatible = "mediatek,mt8188-lvts-ap"; + reg = <0 0x1100b000 0 0xc00>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST>; + nvmem-cells = <&lvts_efuse_data1>; + nvmem-cell-names = "lvts-calib-data-1"; + #thermal-sensor-cells = <1>; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; #address-cells = <1>; @@ -1050,6 +1063,17 @@ mmc1: mmc@11240000 { status = "disabled"; }; + lvts_mcu: thermal-sensor@11278000 { + compatible = "mediatek,mt8188-lvts-mcu"; + reg = <0 0x11278000 0 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST>; + nvmem-cells = <&lvts_efuse_data1>; + nvmem-cell-names = "lvts-calib-data-1"; + #thermal-sensor-cells = <1>; + }; + i2c0: i2c@11280000 { compatible = "mediatek,mt8188-i2c"; reg = <0 0x11280000 0 0x1000>, @@ -1273,6 +1297,17 @@ imp_iic_wrap_en: clock-controller@11ec2000 { #clock-cells = <1>; }; + efuse: efuse@11f20000 { + compatible = "mediatek,mt8188-efuse", "mediatek,efuse"; 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Mon, 03 Jun 2024 03:51:09 -0700 (PDT) From: Julien Panis Date: Mon, 03 Jun 2024 12:50:53 +0200 Subject: [PATCH v7 6/6] arm64: dts: mediatek: mt8188: add default thermal zones Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240603-mtk-thermal-mt818x-dtsi-v7-6-8c8e3c7a3643@baylibre.com> References: <20240603-mtk-thermal-mt818x-dtsi-v7-0-8c8e3c7a3643@baylibre.com> In-Reply-To: <20240603-mtk-thermal-mt818x-dtsi-v7-0-8c8e3c7a3643@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Daniel Lezcano , Nicolas Pitre , "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Krzysztof Kozlowski , Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717411855; l=11532; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=df8BOD5nCQUlwBBSC2fQS7/v/hAp+pkQj+1lq7cROSc=; b=Rs5iynNgYBz5szWQoUkV/DSghHbMv5Xf8NmrhhMUlz6RqthNrgFngI+rqptUEu/GOUAfV/aKm HRff6+EBGxGApx8uUmYr+RjnbTj+fcPKc5xkBab6iHno+Uk/ruGIFga X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= From: Nicolas Pitre Inspired by the vendor kernel but adapted to the upstream thermal driver version. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Pitre Signed-off-by: Julien Panis --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 447 +++++++++++++++++++++++++++++++ 1 file changed, 447 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 02786fe9891b..cd27966d2e3c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -13,6 +13,8 @@ #include #include #include +#include +#include / { compatible = "mediatek,mt8188"; @@ -418,6 +420,450 @@ psci { method = "smc"; }; + thermal_zones: thermal-zones { + cpu-little0-thermal { + polling-delay = <1000>; + polling-delay-passive = <150>; + thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU0>; + + trips { + cpu_little0_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_little0_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_little0_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_little0_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little1-thermal { + polling-delay = <1000>; + polling-delay-passive = <150>; + thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU1>; + + trips { + cpu_little1_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_little1_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_little1_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_little1_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little2-thermal { + polling-delay = <1000>; + polling-delay-passive = <150>; + thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU2>; + + trips { + cpu_little2_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_little2_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_little2_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_little2_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little3-thermal { + polling-delay = <1000>; + polling-delay-passive = <150>; + thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU3>; + + trips { + cpu_little3_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_little3_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_little3_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_little3_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-big0-thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU0>; + + trips { + cpu_big0_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_big0_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_big0_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_big0_alert0>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-big1-thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU1>; + + trips { + cpu_big1_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_big1_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_big1_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_big1_alert0>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + apu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8188_AP_APU>; + + trips { + apu_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + apu_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + apu_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8188_AP_GPU0>; + + trips { + gpu_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpu_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8188_AP_GPU1>; + + trips { + gpu1_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu1_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpu1_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + adsp-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8188_AP_ADSP>; + + trips { + soc_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + soc_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + vdo-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8188_AP_VDO>; + + trips { + soc1_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc1_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + soc1_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + infra-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8188_AP_INFRA>; + + trips { + soc2_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc2_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + soc2_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cam1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8188_AP_CAM1>; + + trips { + cam1_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cam1_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cam1_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cam2-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8188_AP_CAM2>; + + trips { + cam2_alert0: trip-alert0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cam2_alert1: trip-alert1 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cam2_crit: trip-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; @@ -1322,6 +1768,7 @@ gpu: gpu@13000000 { <&spm MT8188_POWER_DOMAIN_MFG3>, <&spm MT8188_POWER_DOMAIN_MFG4>; power-domain-names = "core0", "core1", "core2"; + #cooling-cells = <2>; status = "disabled"; };