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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c1dcb56014sm7115617a91.25.2024.06.03.23.22.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 23:22:35 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Jim Shu , "Fea . Wang" , Frank Chang Subject: [PATCH v3 1/6] target/riscv: Reuse the conversion function of priv_spec Date: Tue, 4 Jun 2024 14:27:42 +0800 Message-Id: <20240604062747.9212-2-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604062747.9212-1-fea.wang@sifive.com> References: <20240604062747.9212-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=fea.wang@sifive.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Jim Shu Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 13 ++++--------- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cee6fc4a9a..e9e69b9863 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1786,7 +1786,7 @@ static int priv_spec_from_str(const char *priv_spec_str) return priv_version; } -static const char *priv_spec_to_str(int priv_version) +const char *priv_spec_to_str(int priv_version) { switch (priv_version) { case PRIV_VERSION_1_10_0: diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 12d8b5344a..94600b91fa 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -829,4 +829,5 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); /* Implemented in th_csr.c */ void th_register_custom_csrs(RISCVCPU *cpu); +const char *priv_spec_to_str(int priv_version); #endif /* RISCV_CPU_H */ diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 683f604d9f..60fe0fd060 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -76,16 +76,11 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, static const char *cpu_priv_ver_to_str(int priv_ver) { - switch (priv_ver) { - case PRIV_VERSION_1_10_0: - return "v1.10.0"; - case PRIV_VERSION_1_11_0: - return "v1.11.0"; - case PRIV_VERSION_1_12_0: - return "v1.12.0"; - } + const char *priv_spec_str = priv_spec_to_str(priv_ver); - g_assert_not_reached(); + g_assert(priv_spec_str); + + return priv_spec_str; } static void riscv_cpu_synchronize_from_tb(CPUState *cs, From patchwork Tue Jun 4 06:27:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Fea.Wang" X-Patchwork-Id: 13684713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04FD5C25B74 for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c1dcb56014sm7115617a91.25.2024.06.03.23.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 23:22:38 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang Subject: [PATCH v3 2/6] target/riscv: Define macros and variables for ss1p13 Date: Tue, 4 Jun 2024 14:27:43 +0800 Message-Id: <20240604062747.9212-3-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604062747.9212-1-fea.wang@sifive.com> References: <20240604062747.9212-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=fea.wang@sifive.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add macros and variables for RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 4 +++- target/riscv/cpu_cfg.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 94600b91fa..4d73486ea2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -96,12 +96,14 @@ extern RISCVCPUProfile *riscv_profiles[]; #define PRIV_VER_1_10_0_STR "v1.10.0" #define PRIV_VER_1_11_0_STR "v1.11.0" #define PRIV_VER_1_12_0_STR "v1.12.0" +#define PRIV_VER_1_13_0_STR "v1.13.0" enum { PRIV_VERSION_1_10_0 = 0, PRIV_VERSION_1_11_0, PRIV_VERSION_1_12_0, + PRIV_VERSION_1_13_0, - PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, + PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0, }; #define VEXT_VERSION_1_00_0 0x00010000 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index e1e4f32698..fb7eebde52 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -136,6 +136,7 @@ struct RISCVCPUConfig { * TCG always implement/can't be user disabled, * based on spec version. */ + bool has_priv_1_13; bool has_priv_1_12; bool has_priv_1_11; From patchwork Tue Jun 4 06:27:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Fea.Wang" X-Patchwork-Id: 13684717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BE3AC25B74 for ; Tue, 4 Jun 2024 06:23:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sENZH-00078A-7v; Tue, 04 Jun 2024 02:22:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sENZF-00077R-FS for qemu-devel@nongnu.org; Tue, 04 Jun 2024 02:22:45 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sENZE-0006f8-0e for qemu-devel@nongnu.org; Tue, 04 Jun 2024 02:22:45 -0400 Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-681bc7f50d0so3717802a12.0 for ; Mon, 03 Jun 2024 23:22:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717482162; x=1718086962; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nmHsMUz/pX/ZNVmgFEjShgDAW9pA0BGkng6p8nimz/0=; b=MJ8XF/eGIPxYDh1V8+dwOdTcUeGIpv9jWZjs2mTM7ctMsSD0BTB++W6TNjI8RwuFOj W8qoFktr1vGx6jezCZmVYp2PZYofLv820n6FNVSqTtHbuLKQv24D6GwV9aHTcwUpg3UU 1QJRP5NEjO4oOwZSPn0UmFCLsufH/ZtO+aChK+IY4/v7eWYmVtpk3G2WUHBfcBE46Uu+ seK4zGvkA8/5/G10l2jHOB5hmMKmqd06/rjca4hvm+MELR215+ZhvmtgkEFlm6CEadUo xHQioChB3kvJsgbUyPRAHnzHoNg1bxw5AFB1GsfDK8WeutRcYkhlDbRzUcinhJq/c+uQ yhTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717482162; x=1718086962; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nmHsMUz/pX/ZNVmgFEjShgDAW9pA0BGkng6p8nimz/0=; b=J6DEt3BzZgwHn31Aw9G5tSWAXIHaAmgedUzad6dyPZAMCkFDe//aWviBeDFWvaQsIx psyMJhG38o45Uj1KK77cqTtsBiXBbAsCsCt7fcN7RFlrGe3vkFiHK6+Kh+SCwgnP7koo wvEJ7e/5nSZDmuxyJlpGSj5Lwj05dCSLjYuautBpvcb2a+it6kqm2KTT77YZMJBkHou0 2uzbUZExvpfOuxX9i5SSwtsXXurAHzm+Wiq/3b3VJvBRsePAjVqaNeqtxSLze8Ht3vPu WBgEFxvkH4R/W5squ6sW12vM7OQgaSIeiPx+/lyzeu1h1uvucLzbmdmLtI9Nm25NW8dJ I3Mg== X-Gm-Message-State: AOJu0YxcvajESobokmI4sNDQLlev8uWWIzC8tssTB7eN9NTD1VUwnAWa sKNPWi73e4+3cG3fjMEUb2i3Xb0shLvLegTLuIKQyF+dB9zUDown8dRUQQzPAkueBK+XGzzBXch RvqcOryNN8TpfTZNy4zQbq6qu0WrfMErbfdxQj5TllQcOf8Irr3Gl37NAZexTZGRYemMH13UiZs VydXtRFIYFgqmG8Bx47ouv66Jj0mu2ibJ8+04= X-Google-Smtp-Source: AGHT+IHwrIBPeu8ZA4jxr+7tSS0LNAvYWM8ligKABX8KT4oNDKXAocPojh0HibtDWbkvHKCqGGk+zQ== X-Received: by 2002:a17:90a:d150:b0:2c0:93e:df44 with SMTP id 98e67ed59e1d1-2c2530b584emr2600172a91.17.1717482162127; Mon, 03 Jun 2024 23:22:42 -0700 (PDT) Received: from hsinchu36-syssw02.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c1dcb56014sm7115617a91.25.2024.06.03.23.22.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 23:22:41 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang Subject: [PATCH v3 3/6] target/riscv: Support the version for ss1p13 Date: Tue, 4 Jun 2024 14:27:44 +0800 Message-Id: <20240604062747.9212-4-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604062747.9212-1-fea.wang@sifive.com> References: <20240604062747.9212-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=fea.wang@sifive.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 6 +++++- target/riscv/tcg/tcg-cpu.c | 4 ++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e9e69b9863..02c1e12a03 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1775,7 +1775,9 @@ static int priv_spec_from_str(const char *priv_spec_str) { int priv_version = -1; - if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) { + if (!g_strcmp0(priv_spec_str, PRIV_VER_1_13_0_STR)) { + priv_version = PRIV_VERSION_1_13_0; + } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) { priv_version = PRIV_VERSION_1_12_0; } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) { priv_version = PRIV_VERSION_1_11_0; @@ -1795,6 +1797,8 @@ const char *priv_spec_to_str(int priv_version) return PRIV_VER_1_11_0_STR; case PRIV_VERSION_1_12_0: return PRIV_VER_1_12_0_STR; + case PRIV_VERSION_1_13_0: + return PRIV_VER_1_13_0_STR; default: return NULL; } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 60fe0fd060..595d3b5b8f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -318,6 +318,10 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu) cpu->cfg.has_priv_1_12 = true; } + if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { + cpu->cfg.has_priv_1_13 = true; + } + /* zic64b is 1.12 or later */ cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && cpu->cfg.cbop_blocksize == 64 && From patchwork Tue Jun 4 06:27:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Fea.Wang" X-Patchwork-Id: 13684720 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A91E6C25B7E for ; Tue, 4 Jun 2024 06:24:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sENZK-00078p-5Y; Tue, 04 Jun 2024 02:22:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sENZI-00078K-Jq for qemu-devel@nongnu.org; Tue, 04 Jun 2024 02:22:48 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sENZH-0006ff-22 for qemu-devel@nongnu.org; Tue, 04 Jun 2024 02:22:48 -0400 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-6c57fa82fdbso2692068a12.0 for ; Mon, 03 Jun 2024 23:22:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717482165; x=1718086965; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RjKQ0LWyXOz4Tysm+g4djnQkCrSs2pDGW5FYItNP6eQ=; b=fXhJ586OUTWEBCE0m/W9XbspIENJsJh0widzZIumdMw21SkeZTwGZ5rEFbx/t9J4hL cMeYbnP0xFA50YuXiMlZN2x4SmtEJ2n8XKr+fKJmptx5eVf0/zltv+nly9gGIeIdGC9L +xMjZ6Jx0J9fuTH0cCW7vmQYtSH2hXIm5PxuVhvMgXatKhSmVxhaBBNRzLykFKYGjO+e 1O88I8XrHuf45DxEUYXKqHd+RCq4V65yISJ+efogJEq/6ksELHzZY7PL732ezv3LFx/W NaCgWJjbqA6+Bwgw6Z8C36wbHIz8jeAuFm0ydtJ0NkVyF2VytA9VWWbSDmwz+P5SwbkV ot2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717482165; x=1718086965; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RjKQ0LWyXOz4Tysm+g4djnQkCrSs2pDGW5FYItNP6eQ=; b=Gdae2OVN+bjqi4Hy6LqCD6R3UyeDjCxTWCyF/EINxbyx4ab5RvK2IujmJKJvgPhAW1 N5aoynthSf/sWTJBn2M4B9M6OMNntTqKuUJWkZo88KZEAihyzcUpOwNL+w5hKaQxumnD LSwJC1UsSqw3IFoe5hF3hY/GyoWQHWB3PMkr0mPcb0B8grXl9JCzUblLsQUCPlObJ5Pk 6V7htMkRJ6Nx0o2D8+MRbzsALfWwFeg7pfeY9MdE+vjOoDCx2DZ88LFOD3aTeM66rx7Z qGPBhW0eXEPvVzE+hjUSqMlTHv7CnJ7rNbsxyaBaI+p6D7tkOI1FSUuUgq4kxhv6K8PD +GeA== X-Gm-Message-State: AOJu0YyQ2XBVahSWM9WLytJtr6dSXfzv/eYfQ1+HIRCuQMxRHa56PV/c TxkmZhseMGTdKlO6FXEOG14tpHz51+sAtpE8CyuMeVZOt6OY7fVXfWoTn6OcJEBZQMYP7dLAwQF z3vgWMO7IfME//wk0eO15AYiBidZrR4w7JpwAXQ7ZNSlJG+ltKi3LcDmSe1qyctTghEogP0cu1M QNnWL46h5DZTBBlyb8xOWjhRep28kc3GkEMeM= X-Google-Smtp-Source: AGHT+IHHAJKRxccxZtv6lpzGVAq926PYUz5xfEIERiwKNo8BQ64488GLahE8q1+Uf/TAYrZtRXBukA== X-Received: by 2002:a05:6a20:3d86:b0:1af:fff9:30e6 with SMTP id adf61e73a8af0-1b26f1b9abcmr12117069637.15.1717482165081; Mon, 03 Jun 2024 23:22:45 -0700 (PDT) Received: from hsinchu36-syssw02.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c1dcb56014sm7115617a91.25.2024.06.03.23.22.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 23:22:44 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang Subject: [PATCH v3 4/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0 Date: Tue, 4 Jun 2024 14:27:45 +0800 Message-Id: <20240604062747.9212-5-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604062747.9212-1-fea.wang@sifive.com> References: <20240604062747.9212-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=fea.wang@sifive.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in mstateen0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 74318a925c..28bd3fb0b4 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -315,6 +315,7 @@ #define SMSTATEEN0_CS (1ULL << 0) #define SMSTATEEN0_FCSR (1ULL << 1) #define SMSTATEEN0_JVT (1ULL << 2) +#define SMSTATEEN0_P1P13 (1ULL << 56) #define SMSTATEEN0_HSCONTXT (1ULL << 57) #define SMSTATEEN0_IMSIC (1ULL << 58) #define SMSTATEEN0_AIA (1ULL << 59) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 58ef7079dc..3dcfb343fe 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2245,6 +2245,10 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, wr_mask |= SMSTATEEN0_FCSR; } + if (env->priv_ver >= PRIV_VERSION_1_13_0) { + wr_mask |= SMSTATEEN0_P1P13; + } + return write_mstateen(env, csrno, wr_mask, new_val); } @@ -2280,6 +2284,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (env->priv_ver >= PRIV_VERSION_1_13_0) { + wr_mask |= SMSTATEEN0_P1P13; + } + return write_mstateenh(env, csrno, wr_mask, new_val); } From patchwork Tue Jun 4 06:27:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Fea.Wang" X-Patchwork-Id: 13684715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DEAFC25B7E for ; Tue, 4 Jun 2024 06:23:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sENZN-00079T-1a; Tue, 04 Jun 2024 02:22:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sENZL-00079F-PQ for qemu-devel@nongnu.org; Tue, 04 Jun 2024 02:22:51 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sENZK-0006g7-68 for qemu-devel@nongnu.org; Tue, 04 Jun 2024 02:22:51 -0400 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2c210d3dc6cso547170a91.3 for ; Mon, 03 Jun 2024 23:22:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717482169; x=1718086969; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qq2F16iGLWJ1JpPy/R68fie0tbSa93MUzDYcvl7x2d0=; b=cI3RbW39jOU3qpRFBYVX7e9D5Sgww/0/dk/vmqL6RRgusCNcM316GValT7OUA4P2tS zZrQma+HOGCO8WUrtI5OeigplDTmMsSOQ/KnCCEAGFVWlhlb5WR7edSprk5teG3/gwOT S42sxWZ8AvgLFcNsuNF1CczzoD42ifDUMGmgslaIOsB/jLziDI51kkMtH7kOvTd8kiz9 fXFi7cAYjCuGKvOP/18mXSQ5OKXmCdZ+kZAOeEuUlZ4T9rrvvQ7q4f1QIzLRaK24yhU0 NocYwGIzu4IrBny8P+bogIJ7jr3TqJaz+A9yssUiyJyROso1ZPjQ9GBmhSQHwy4Y8u/B O2NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717482169; x=1718086969; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qq2F16iGLWJ1JpPy/R68fie0tbSa93MUzDYcvl7x2d0=; b=rnfzN5jZDLMDY2DX7Ky5m35pwizB+ICUYlR12j5+i5AJBMhip6lD+0DPoOvYCMPpFR BmlbECRbFSbyWvXE0ovKgGBfbjHWOBCcyYhYxYml2GplSkNgv36R/II7bE/EKW9A2DUW WYsfuoVOgWguTb9sHrhstFibKKPrLba6RSX8uG+uCdufvbAxKIFoPPk3CAwpgyVIHiy1 NvOLIPpI8SIVbOv/IuEiTZTHjRtLtOrpH/IMED2oqNjg/hhXz2x4f9maY2L9eoMRrcnJ QppK5PUOxtd8wT87M3x8PL4Oh+ImAzLB8U0Y+l+8SthMKXAheg0pJu1AZ52n/9iAf7op v3SQ== X-Gm-Message-State: AOJu0Yx/hkADx31b9OryFd/ZGyRgPT9CwSqd4uLbvpLAkxm9bRsV3d0Z tIyHACsX6lyURWThapRDOtunoKFKY0BHs16bX7c1cY93gMQpLAq1vzpNBVSuOy2UMBffTWBKRwe VQwF/Fk+KbbDP1lcNlEBwNd1OJZQfAXpJ+R3DwKW+1GJ5SGxGPLEujBwnBpE6e4eEkb1OR6v/xk Io+RwiZ4zM8qXmS+juAVTrq/m5/LgguwPhRtI= X-Google-Smtp-Source: AGHT+IEeQ5JTMwH32iAMPQTYmqnN+2FxxrkJsVFayPwlsAyj8/cVnUuvYzBDkCIHRIML4v8xVA4ddw== X-Received: by 2002:a17:90a:1fc2:b0:2c1:972b:4910 with SMTP id 98e67ed59e1d1-2c1dc56cd13mr9127499a91.2.1717482168372; Mon, 03 Jun 2024 23:22:48 -0700 (PDT) Received: from hsinchu36-syssw02.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c1dcb56014sm7115617a91.25.2024.06.03.23.22.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 23:22:48 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang Subject: [PATCH v3 5/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 Date: Tue, 4 Jun 2024 14:27:46 +0800 Message-Id: <20240604062747.9212-6-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604062747.9212-1-fea.wang@sifive.com> References: <20240604062747.9212-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=fea.wang@sifive.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH and HEDELEGH for exception codes 32-47 for reserving and exception codes 48-63 for custom use. Add the CSR number though the implementation is just reading zero and writing ignore. Besides, for accessing HEDELEGH, it should be controlled by mstateen0 'P1P13' bit. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 28bd3fb0b4..f888025c59 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -156,6 +156,8 @@ /* 32-bit only */ #define CSR_MSTATUSH 0x310 +#define CSR_MEDELEGH 0x312 +#define CSR_HEDELEGH 0x612 /* Machine Trap Handling */ #define CSR_MSCRATCH 0x340 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3dcfb343fe..d480feb94d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3222,6 +3222,33 @@ static RISCVException write_hedeleg(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException read_hedelegh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + RISCVException ret; + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + + /* Reserved, now read zero */ + *val = 0; + return RISCV_EXCP_NONE; +} + +static RISCVException write_hedelegh(CPURISCVState *env, int csrno, + target_ulong val) +{ + RISCVException ret; + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + + /* Reserved, now write ignore */ + return RISCV_EXCP_NONE; +} + static RISCVException rmw_hvien64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -4626,6 +4653,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, + [CSR_MEDELEGH] = { "medelegh", any32, read_zero, write_ignore, + .min_priv_ver = PRIV_VERSION_1_13_0 }, + [CSR_HEDELEGH] = { "hedelegh", hmode32, read_hedelegh, write_hedelegh, + .min_priv_ver = PRIV_VERSION_1_13_0 }, /* Machine Trap Handling */ [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, From patchwork Tue Jun 4 06:27:47 2024 Content-Type: text/plain; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c1dcb56014sm7115617a91.25.2024.06.03.23.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 23:22:52 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang Subject: [PATCH v3 6/6] target/riscv: Reserve exception codes for sw-check and hw-err Date: Tue, 4 Jun 2024 14:27:47 +0800 Message-Id: <20240604062747.9212-7-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604062747.9212-1-fea.wang@sifive.com> References: <20240604062747.9212-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=fea.wang@sifive.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f888025c59..f037f727d9 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -673,6 +673,8 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */ + RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */ RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,