From patchwork Tue Jun 4 16:04:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christian_K=C3=B6nig?= X-Patchwork-Id: 13685631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BD43C27C52 for ; Tue, 4 Jun 2024 16:05:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 47D6E10E1D9; Tue, 4 Jun 2024 16:05:37 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="lNesMdz8"; dkim-atps=neutral Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by gabe.freedesktop.org (Postfix) with ESMTPS id 35B8910E0CF; Tue, 4 Jun 2024 16:05:10 +0000 (UTC) Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-42147970772so7796355e9.0; Tue, 04 Jun 2024 09:05:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1717517108; x=1718121908; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GHxeKnQ2f1oDQioghZ3Qjfp5SfNlRx4NYZEzuEzE94o=; b=lNesMdz85IKJQmleCcWVXJ3lrdXFE1i/zBQ6NXvWSV/m0Za0P3oUD5nN0EX+MFzGgT gaAfK3x+BJZd6G5SRng651P/1NSNwBbC1FvYUTcFCXC/7OPM+k1eSSLM/JiL7+/oWQ5C 8gmexaN5K3nYimznaV38rvX6ozV2fvOguvIlhiFL0fBZjf3o6BfILq2tg3P56lyKix5/ 8rKUbqHsXAK8bEFsbIYnMZapWKD9Zya8sMKt1ggs5HIpAzf1oy1VpvCeiSv3G3rnJRaa Oujn+8Jr6sbL5cXruG57sg35SB51BR+F3pSHk1N6+OTemDLPAj98wHnPABQyF/FnOpCq Yjqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717517108; x=1718121908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GHxeKnQ2f1oDQioghZ3Qjfp5SfNlRx4NYZEzuEzE94o=; b=j78WzYCOlMcsj+koz1TDxjJX4dtN1xGarF8xg/z4Mh0frw99hLR6fT4IVZRIYqM845 lZaNnBdsCDfX2E9d06FNbY/sKbZiUFqacfCR1os9KSrmA9aSzcivsh3KFla/irS3ESch X++0GokeZWrbmMSMu1KJ7GYKUkOQaDNQz5mPW2B9FJyX+lqJKoEeavAkvy8+M7gRPT99 ZCKYM8/4QmwYjgBvm+jZ8Sz0yRovtUx02G1QSHyKSFInKjykhLpmoCU9gpkOaV5laYc/ fodj0zOiZ6/ny78mKMaDCD5BUQvMgVeLJnE6jhQnknnn7+tfGSbAh6F8QAqNfNZ/WzSc jaxg== X-Forwarded-Encrypted: i=1; AJvYcCXxaaM0BoRTFUb27IINxVxpLHnjMuz3lLr7SKJhG7OCKJMv4YkiwlAHzR+7fAJ4Hx2upndE8rIMqjPHLXO13GiYK+IYJf6zdAyU/etryA== X-Gm-Message-State: AOJu0Yy+ktCj38ANON7ka3teC1hOs64O+rYjY079mVAcZovRC2E4KKjK LTtq3VMNf9FxQrlbwt7cs7lKKrDKGIbBIhYuZAFWgDoYiO1KWiCw X-Google-Smtp-Source: AGHT+IF8nC1GVrzK4cgpF1Cj6d61cI4iYX0+Rl/QVO6SAWz/gX04PXs3AIgjSBUCCoxM7c7av4rP9w== X-Received: by 2002:a05:600c:5487:b0:420:2cbe:7efd with SMTP id 5b1f17b1804b1-42156338a6bmr383055e9.31.1717517108167; Tue, 04 Jun 2024 09:05:08 -0700 (PDT) Received: from able.fritz.box ([2a00:e180:157b:4500:3a1f:103c:c5a9:7f90]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35e7e07d7besm2388082f8f.18.2024.06.04.09.05.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jun 2024 09:05:07 -0700 (PDT) From: " =?utf-8?q?Christian_K=C3=B6nig?= " X-Google-Original-From: =?utf-8?q?Christian_K=C3=B6nig?= To: tursulin@ursulin.net, friedrich.vock@gmx.de Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org Subject: [PATCH 1/6] drm/amdgpu: cleanup MES command submission Date: Tue, 4 Jun 2024 18:04:58 +0200 Message-Id: <20240604160503.43359-2-christian.koenig@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604160503.43359-1-christian.koenig@amd.com> References: <20240604160503.43359-1-christian.koenig@amd.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The approach of having a separate WB slot for each submission doesn't really work well and for example breaks GPU reset. Use a status query packet for the fence update instead since those should always succeed we can use the fence of the original packet to signal the state of the operation. Only compile tested. While at it cleanup the coding style. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 76 ++++++++++++++++---------- 1 file changed, 48 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 0d1407f25005..32d4519541c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -154,18 +154,18 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, void *pkt, int size, int api_status_off) { - int ndw = size / 4; - signed long r; - union MESAPI__MISC *x_pkt = pkt; - struct MES_API_STATUS *api_status; + union MESAPI__QUERY_MES_STATUS mes_status_pkt; + signed long timeout = 3000000; /* 3000 ms */ struct amdgpu_device *adev = mes->adev; struct amdgpu_ring *ring = &mes->ring; - unsigned long flags; - signed long timeout = 3000000; /* 3000 ms */ + struct MES_API_STATUS *api_status; + union MESAPI__MISC *x_pkt = pkt; const char *op_str, *misc_op_str; - u32 fence_offset; - u64 fence_gpu_addr; - u64 *fence_ptr; + unsigned long flags; + u64 status_gpu_addr; + u32 status_offset; + u64 *status_ptr; + signed long r; int ret; if (x_pkt->header.opcode >= MES_SCH_API_MAX) @@ -177,28 +177,38 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ timeout = 15 * 600 * 1000; } - BUG_ON(size % 4 != 0); - ret = amdgpu_device_wb_get(adev, &fence_offset); + ret = amdgpu_device_wb_get(adev, &status_offset); if (ret) return ret; - fence_gpu_addr = - adev->wb.gpu_addr + (fence_offset * 4); - fence_ptr = (u64 *)&adev->wb.wb[fence_offset]; - *fence_ptr = 0; + + status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); + status_ptr = (u64 *)&adev->wb.wb[status_offset]; + *status_ptr = 0; spin_lock_irqsave(&mes->ring_lock, flags); - if (amdgpu_ring_alloc(ring, ndw)) { - spin_unlock_irqrestore(&mes->ring_lock, flags); - amdgpu_device_wb_free(adev, fence_offset); - return -ENOMEM; - } + r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); + if (r) + goto error_unlock_free; api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); - api_status->api_completion_fence_addr = fence_gpu_addr; + api_status->api_completion_fence_addr = status_gpu_addr; api_status->api_completion_fence_value = 1; - amdgpu_ring_write_multiple(ring, pkt, ndw); + amdgpu_ring_write_multiple(ring, pkt, size / 4); + + memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); + mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; + mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + mes_status_pkt.api_status.api_completion_fence_addr = + ring->fence_drv.gpu_addr; + mes_status_pkt.api_status.api_completion_fence_value = + ++ring->fence_drv.sync_seq; + + amdgpu_ring_write_multiple(ring, &mes_status_pkt, + sizeof(mes_status_pkt) / 4); + amdgpu_ring_commit(ring); spin_unlock_irqrestore(&mes->ring_lock, flags); @@ -206,15 +216,16 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); if (misc_op_str) - dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, misc_op_str); + dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, + misc_op_str); else if (op_str) dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); else - dev_dbg(adev->dev, "MES msg=%d was emitted\n", x_pkt->header.opcode); + dev_dbg(adev->dev, "MES msg=%d was emitted\n", + x_pkt->header.opcode); - r = amdgpu_mes_fence_wait_polling(fence_ptr, (u64)1, timeout); - amdgpu_device_wb_free(adev, fence_offset); - if (r < 1) { + r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, timeout); + if (r < 1 || !*status_ptr) { if (misc_op_str) dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", @@ -229,10 +240,19 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, while (halt_if_hws_hang) schedule(); - return -ETIMEDOUT; + r = -ETIMEDOUT; + goto error_wb_free; } + amdgpu_device_wb_free(adev, status_offset); return 0; + +error_unlock_free: + spin_unlock_irqrestore(&mes->ring_lock, flags); + +error_wb_free: + amdgpu_device_wb_free(adev, status_offset); + return r; } static int convert_to_mes_queue_type(int queue_type) From patchwork Tue Jun 4 16:04:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christian_K=C3=B6nig?= X-Patchwork-Id: 13685628 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ACAADC25B78 for ; Tue, 4 Jun 2024 16:05:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6885510E025; 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Tue, 04 Jun 2024 09:05:08 -0700 (PDT) Received: from able.fritz.box ([2a00:e180:157b:4500:3a1f:103c:c5a9:7f90]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35e7e07d7besm2388082f8f.18.2024.06.04.09.05.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jun 2024 09:05:08 -0700 (PDT) From: " =?utf-8?q?Christian_K=C3=B6nig?= " X-Google-Original-From: =?utf-8?q?Christian_K=C3=B6nig?= To: tursulin@ursulin.net, friedrich.vock@gmx.de Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org Subject: [PATCH 2/6] drm/ttm: add TTM_PL_FLAG_TRESHOLD Date: Tue, 4 Jun 2024 18:04:59 +0200 Message-Id: <20240604160503.43359-3-christian.koenig@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604160503.43359-1-christian.koenig@amd.com> References: <20240604160503.43359-1-christian.koenig@amd.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This adds support to enable a placement only when a certain treshold of moved bytes is reached. It's a context flag which will be handled together with TTM_PL_FLAG_DESIRED and TTM_PL_FLAG_FALLBACK. Signed-off-by: Christian König --- drivers/gpu/drm/ttm/ttm_bo.c | 5 ++--- drivers/gpu/drm/ttm/ttm_resource.c | 35 ++++++++++++++++++++++++++++-- include/drm/ttm/ttm_bo.h | 3 +++ include/drm/ttm/ttm_placement.h | 15 +++++++++++++ include/drm/ttm/ttm_resource.h | 2 ++ 5 files changed, 55 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 6396dece0db1..6cd2e32bb5db 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -764,8 +764,7 @@ static int ttm_bo_alloc_resource(struct ttm_buffer_object *bo, if (!man || !ttm_resource_manager_used(man)) continue; - if (place->flags & (force_space ? TTM_PL_FLAG_DESIRED : - TTM_PL_FLAG_FALLBACK)) + if (!ttm_place_applicable(place, ctx, force_space)) continue; do { @@ -864,7 +863,7 @@ int ttm_bo_validate(struct ttm_buffer_object *bo, do { /* Check whether we need to move buffer. */ if (bo->resource && - ttm_resource_compatible(bo->resource, placement, + ttm_resource_compatible(bo->resource, placement, ctx, force_space)) return 0; diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index 4a66b851b67d..74a6bfc74dbe 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -292,6 +292,37 @@ bool ttm_resource_intersects(struct ttm_device *bdev, return man->func->intersects(man, res, place, size); } +/** + * ttm_place_applicable - check if place is applicable + * + * @place: place to check + * @ctx: the operation context + * @evicting: true if TTM is evicting resources + * + * Return true if the place is currently applicable. + */ +bool ttm_place_applicable(const struct ttm_place *place, + struct ttm_operation_ctx *ctx, + bool evicting) +{ + + /* When no flag is given we always consider the place applicable */ + if (!(place->flags & TTM_PL_FLAG_CTX_MASK)) + return true; + + if (place->flags & TTM_PL_FLAG_FALLBACK && evicting) + return true; + + if (place->flags & TTM_PL_FLAG_DESIRED && !evicting) + return true; + + if (place->flags & TTM_PL_FLAG_MOVE_THRESHOLD && + ctx->bytes_moved < ctx->move_threshold) + return true; + + return false; +} + /** * ttm_resource_compatible - check if resource is compatible with placement * @@ -303,6 +334,7 @@ bool ttm_resource_intersects(struct ttm_device *bdev, */ bool ttm_resource_compatible(struct ttm_resource *res, struct ttm_placement *placement, + struct ttm_operation_ctx *ctx, bool evicting) { struct ttm_buffer_object *bo = res->bo; @@ -319,8 +351,7 @@ bool ttm_resource_compatible(struct ttm_resource *res, if (res->mem_type != place->mem_type) continue; - if (place->flags & (evicting ? TTM_PL_FLAG_DESIRED : - TTM_PL_FLAG_FALLBACK)) + if (!ttm_place_applicable(place, ctx, evicting)) continue; if (place->flags & TTM_PL_FLAG_CONTIGUOUS && diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index 6ccf96c91f3a..a85be2140970 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -176,6 +176,8 @@ struct ttm_bo_kmap_obj { * faults. Should only be used by TTM internally. * @resv: Reservation object to allow reserved evictions with. * @bytes_moved: Statistics on how many bytes have been moved. + * @move_threshold: When @bytes_moved >= @move_threshold placements with + * @TTM_PL_FLAG_MOVE_TRESHOLD are used as well. * * Context for TTM operations like changing buffer placement or general memory * allocation. @@ -188,6 +190,7 @@ struct ttm_operation_ctx { bool force_alloc; struct dma_resv *resv; uint64_t bytes_moved; + uint64_t move_threshold; }; /** diff --git a/include/drm/ttm/ttm_placement.h b/include/drm/ttm/ttm_placement.h index b510a4812609..cf809749585d 100644 --- a/include/drm/ttm/ttm_placement.h +++ b/include/drm/ttm/ttm_placement.h @@ -48,6 +48,8 @@ * placement that can handle such scenarios is a good idea. */ +struct ttm_operation_ctx; + #define TTM_PL_SYSTEM 0 #define TTM_PL_TT 1 #define TTM_PL_VRAM 2 @@ -70,6 +72,15 @@ /* Placement is only used during eviction */ #define TTM_PL_FLAG_FALLBACK (1 << 4) +/* Placement can only be used if threshold of moved bytes is reached */ +#define TTM_PL_FLAG_MOVE_THRESHOLD (1 << 5) + +/* Placement flags which depend on TTMs operation ctx. Fulfilling any flag is + * enough to consider the placement applicable. + */ +#define TTM_PL_FLAG_CTX_MASK (TTM_PL_FLAG_DESIRED | TTM_PL_FLAG_FALLBACK | \ + TTM_PL_FLAG_MOVE_THRESHOLD) + /** * struct ttm_place * @@ -100,4 +111,8 @@ struct ttm_placement { const struct ttm_place *placement; }; +bool ttm_place_applicable(const struct ttm_place *place, + struct ttm_operation_ctx *ctx, + bool evicting); + #endif diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h index 69769355139f..6ca6b7b82fb8 100644 --- a/include/drm/ttm/ttm_resource.h +++ b/include/drm/ttm/ttm_resource.h @@ -44,6 +44,7 @@ struct ttm_resource; struct ttm_place; struct ttm_buffer_object; struct ttm_placement; +struct ttm_operation_ctx; struct iosys_map; struct io_mapping; struct sg_table; @@ -370,6 +371,7 @@ bool ttm_resource_intersects(struct ttm_device *bdev, size_t size); bool ttm_resource_compatible(struct ttm_resource *res, struct ttm_placement *placement, + struct ttm_operation_ctx *ctx, bool evicting); void ttm_resource_set_bo(struct ttm_resource *res, struct ttm_buffer_object *bo); From patchwork Tue Jun 4 16:05:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christian_K=C3=B6nig?= X-Patchwork-Id: 13685629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65F0AC27C52 for ; Tue, 4 Jun 2024 16:05:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4BD6810E2EE; Tue, 4 Jun 2024 16:05:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="FkqeHeQi"; dkim-atps=neutral Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5D72410E195; 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Tue, 04 Jun 2024 09:05:09 -0700 (PDT) From: " =?utf-8?q?Christian_K=C3=B6nig?= " X-Google-Original-From: =?utf-8?q?Christian_K=C3=B6nig?= To: tursulin@ursulin.net, friedrich.vock@gmx.de Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org Subject: [PATCH 3/6] drm/amdgpu: enable GTT fallback handling for dGPUs only Date: Tue, 4 Jun 2024 18:05:00 +0200 Message-Id: <20240604160503.43359-4-christian.koenig@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604160503.43359-1-christian.koenig@amd.com> References: <20240604160503.43359-1-christian.koenig@amd.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" That is just a waste of time on APUs. Signed-off-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 8d8c39be6129..f7b534c55c43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -180,7 +180,8 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) * When GTT is just an alternative to VRAM make sure that we * only use it as fallback and still try to fill up VRAM first. */ - if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) + if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM && + !(adev->flags & AMD_IS_APU)) places[c].flags |= TTM_PL_FLAG_FALLBACK; c++; } From patchwork Tue Jun 4 16:05:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christian_K=C3=B6nig?= X-Patchwork-Id: 13685633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F4A1C27C52 for ; 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Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index f7b534c55c43..8c92065c2d52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -161,14 +161,6 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) c++; } - if (domain & AMDGPU_GEM_DOMAIN_DOORBELL) { - places[c].fpfn = 0; - places[c].lpfn = 0; - places[c].mem_type = AMDGPU_PL_DOORBELL; - places[c].flags = 0; - c++; - } - if (domain & AMDGPU_GEM_DOMAIN_GTT) { places[c].fpfn = 0; places[c].lpfn = 0; @@ -218,6 +210,14 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) c++; } + if (domain & AMDGPU_GEM_DOMAIN_DOORBELL) { + places[c].fpfn = 0; + places[c].lpfn = 0; + places[c].mem_type = AMDGPU_PL_DOORBELL; + places[c].flags = 0; + c++; + } + if (!c) { places[c].fpfn = 0; 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Tue, 04 Jun 2024 09:05:10 -0700 (PDT) From: " =?utf-8?q?Christian_K=C3=B6nig?= " X-Google-Original-From: =?utf-8?q?Christian_K=C3=B6nig?= To: tursulin@ursulin.net, friedrich.vock@gmx.de Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org Subject: [PATCH 5/6] drm/amdgpu: always enable move threshold for BOs Date: Tue, 4 Jun 2024 18:05:02 +0200 Message-Id: <20240604160503.43359-6-christian.koenig@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604160503.43359-1-christian.koenig@amd.com> References: <20240604160503.43359-1-christian.koenig@amd.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This should prevent buffer moves when the threshold is reached during CS. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 36 ++++++++-------------- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 22 +++++++++---- 2 files changed, 29 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index ec888fc6ead8..9a217932a4fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -784,7 +784,6 @@ static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo) .no_wait_gpu = false, .resv = bo->tbo.base.resv }; - uint32_t domain; int r; if (bo->tbo.pin_count) @@ -796,37 +795,28 @@ static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo) if (p->bytes_moved < p->bytes_moved_threshold && (!bo->tbo.base.dma_buf || list_empty(&bo->tbo.base.dma_buf->attachments))) { + + /* And don't move a CPU_ACCESS_REQUIRED BO to limited + * visible VRAM if we've depleted our allowance to do + * that. + */ if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && - (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) { - /* And don't move a CPU_ACCESS_REQUIRED BO to limited - * visible VRAM if we've depleted our allowance to do - * that. - */ - if (p->bytes_moved_vis < p->bytes_moved_vis_threshold) - domain = bo->preferred_domains; - else - domain = bo->allowed_domains; - } else { - domain = bo->preferred_domains; - } - } else { - domain = bo->allowed_domains; + (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && + p->bytes_moved_vis < p->bytes_moved_vis_threshold) + ctx.move_threshold = p->bytes_moved_vis_threshold - + p->bytes_moved_vis; + else + ctx.move_threshold = p->bytes_moved_vis_threshold - + p->bytes_moved; } -retry: - amdgpu_bo_placement_from_domain(bo, domain); + amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); p->bytes_moved += ctx.bytes_moved; if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && amdgpu_res_cpu_visible(adev, bo->tbo.resource)) p->bytes_moved_vis += ctx.bytes_moved; - - if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { - domain = bo->allowed_domains; - goto retry; - } - return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 8c92065c2d52..cae1a5420c58 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -168,13 +168,23 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ? AMDGPU_PL_PREEMPT : TTM_PL_TT; places[c].flags = 0; - /* - * When GTT is just an alternative to VRAM make sure that we - * only use it as fallback and still try to fill up VRAM first. - */ + if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM && - !(adev->flags & AMD_IS_APU)) - places[c].flags |= TTM_PL_FLAG_FALLBACK; + !(adev->flags & AMD_IS_APU)) { + /* + * When GTT is just an alternative to VRAM make sure that we + * only use it as fallback and still try to fill up VRAM first. + */ + if (abo->preferred_domains & AMDGPU_GEM_DOMAIN_GTT) + places[c].flags |= TTM_PL_FLAG_FALLBACK; + + /* + * Enable GTT when the threshold of moved bytes is + * reached. This prevents any non essential buffer move + * when the links are already saturated. + */ + places[c].flags |= TTM_PL_FLAG_MOVE_THRESHOLD; + } c++; } From patchwork Tue Jun 4 16:05:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christian_K=C3=B6nig?= X-Patchwork-Id: 13685630 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 34FDFC27C54 for ; Tue, 4 Jun 2024 16:05:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DD60010E238; Tue, 4 Jun 2024 16:05:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QT6Y9H4D"; dkim-atps=neutral Received: from mail-lj1-f174.google.com (mail-lj1-f174.google.com [209.85.208.174]) by gabe.freedesktop.org (Postfix) with ESMTPS id DE82610E025; Tue, 4 Jun 2024 16:05:13 +0000 (UTC) Received: by mail-lj1-f174.google.com with SMTP id 38308e7fff4ca-2eaa80cb550so16993111fa.0; Tue, 04 Jun 2024 09:05:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1717517112; x=1718121912; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZPsP0RmXQWgRLeKsh9rUQ07m9IfAwnD8hQVO6AEBOV0=; b=QT6Y9H4DmgRNQA+ue2OWZM6qbVcemIvo4Vlw3hBZ9elo3XfobV8AO7MF2+ZCFUWrMA zvjEyj6vSQsbKk67/UIyK9kgERO5hMP8Ot4HxTjoZ5nPx6Mfvs+w95+0Dgs5ZJSfuIZ+ d+BoXVIRa14a7k/GmgzzJhqGItr/AYupQjLOvV4L6Oyn/7eb6ACJKRNt5E5L4EA17b02 7W9ctX97pF9RiwW2lvcM0dAAi0IxkotXorHkEaPeF7PeAzYzVV6O8uXUOuC8Op/nlsuM fQbADCD3IUjjxaTlB0qG0PIciyRQF/dxfx/sflwmf570RaG+PsBnvyBrCHFkZlV/ywCa SeJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717517112; x=1718121912; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZPsP0RmXQWgRLeKsh9rUQ07m9IfAwnD8hQVO6AEBOV0=; b=tUpR59eU1s2ZG4XGCMRtn7r7W6lFYvJhjbILfYR1KDpuFQcbMhqfCp9JbIskIGBooc DDwfaIwapulLbr3N4kxja8y5stTOjFerh7fQSGmEfpUiHnDazwGFefCr5DvT3PfQM5Ps HTlyrgqUEZZSL/JJCcyhQ43J0Ba96kpH6XmakQhMWGOVzjtk0gbXWLooPH7s7N1A97ip /9hVjG9iM4boSMpvcEye1FjePJaBIpGH+DaZ5NCJPFo+XHcXkoB7lUy7UElwTujFlcKW nlKlB4RbfTPhkF6j+wXcHyOWAXC12unh3p3y39o7gAuG7vtN3y8sY63gNXMVCXceSXPI +LWw== X-Forwarded-Encrypted: i=1; AJvYcCU16LuDspBpAKqfM5qEdy3xwIaEo2lORKZ3fI0yC3XHRRkGnFkHvM6wrsONyF6eIaKAU8Vr52yLRYzXNbrVb+zZAaJdlX+Nx2ohoPG4LQ== X-Gm-Message-State: AOJu0Yxl63rY7M7rxPz9nFg2iYxYfuJ4bx3wwlopgJQDiGJasPjcryov Pb4FdzEdsynbCZAYoeNlEq3OgUjPZ0fuVcWI6u+khlsIJg6/cRSn X-Google-Smtp-Source: AGHT+IHZaHnMhcp/DQUzaQXIxYFqWKasSEBxmn5u+Hx/QRti7rFuamenhGjtXyoRB4pmhrZ/hKsL7g== X-Received: by 2002:a2e:a554:0:b0:2ea:c3db:d0ce with SMTP id 38308e7fff4ca-2eac3dbd2fbmr7950801fa.46.1717517111731; Tue, 04 Jun 2024 09:05:11 -0700 (PDT) Received: from able.fritz.box ([2a00:e180:157b:4500:3a1f:103c:c5a9:7f90]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35e7e07d7besm2388082f8f.18.2024.06.04.09.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jun 2024 09:05:11 -0700 (PDT) From: " =?utf-8?q?Christian_K=C3=B6nig?= " X-Google-Original-From: =?utf-8?q?Christian_K=C3=B6nig?= To: tursulin@ursulin.net, friedrich.vock@gmx.de Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org Subject: [PATCH 6/6] drm/amdgpu: Re-validate evicted buffers v2 Date: Tue, 4 Jun 2024 18:05:03 +0200 Message-Id: <20240604160503.43359-7-christian.koenig@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604160503.43359-1-christian.koenig@amd.com> References: <20240604160503.43359-1-christian.koenig@amd.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tvrtko Ursulin Currently the driver appears to be thinking that it will be attempting to re-validate the evicted buffers on the next submission if they are not in their preferred placement. That however appears not to be true for the very common case of buffers with allowed placements of VRAM+GTT. Simply because the check can only detect if the current placement is *none* of the preferred ones, happily leaving VRAM+GTT buffers in the GTT placement "forever". Fix it by extending the VRAM+GTT special case to the re-validation logic. v2: re-work the criteria to consider if something is in it's preferred placement or not and also disable the handling on APUs. Signed-off-by: Tvrtko Ursulin Signed-off-by: Christian König Reported-by:. In which case I could theoretically even provide an r-b. :) --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 4e2391c83d7c..1a470dafa93d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1242,15 +1242,15 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, return r; } - /* If the BO is not in its preferred location add it back to - * the evicted list so that it gets validated again on the - * next command submission. - */ if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) { - uint32_t mem_type = bo->tbo.resource->mem_type; - - if (!(bo->preferred_domains & - amdgpu_mem_type_to_domain(mem_type))) + /* + * If the preferred location is VRAM but we placed it into GTT + * add it back to the evicted list so that it gets validated + * again on the next command submission. + */ + if (!(adev->flags & AMD_IS_APU) && + bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM && + bo->tbo.resource->mem_type != TTM_PL_VRAM) amdgpu_vm_bo_evicted(&bo_va->base); else amdgpu_vm_bo_idle(&bo_va->base);