From patchwork Wed Jun 5 01:22:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13686076 Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-vi1eur04on2080.outbound.protection.outlook.com [40.107.8.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5F519460 for ; Wed, 5 Jun 2024 01:13:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.8.80 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717550031; cv=fail; b=m/ySjeaTByTv91NxfhehZrtN88SiGB6x1qXiZpavk7NLq+FhDSlcnmEMKpTqrjoF/o9GRnilVZzv7po9cYMHTgiX2hakrMAu2Fo+2t4k71iS67UBPj+e9HeLAMYNQakPWiFX1juDZDiFGFvmYo1GfXX11yYLfkeEChdR4xAPeQw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717550031; c=relaxed/simple; bh=xDHthho3clLMwVkgJtffn/O2I4fbcl26gyOATRJQtI4=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=a+Ej6NO/+o79Q3D3OAh+g/sXOnLAuYfgrv8fh4qxLVq8rc/rsbVaDnAs7jIB4C21S3c4PIWkpM2mFSvpuxswNKp1uUpNlk1+1QLTKKIYhe9mT8nHGZl/yyKXZi5uQc+KmtAxM2KMuW3U2emfB8bHY8EpGQDrLfrpOcd8Q1PxvMw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (1024-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=Kve2s2i3; arc=fail smtp.client-ip=40.107.8.80 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="Kve2s2i3" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GZtUxY+ZeXx135ZJfu37Qq6G6b0YZopjUhkQypFOkkP/WDn8SexaFw4nGEKLd6LKJo8FGDy5xLOx1Owty8gVB7wiikYShDE2ihnL8HapqC6gROi8JgolamGVm382ixCMijsOb6+1PMjkcYeSnxBY5qm60SCD+C2m5tYJdZVEAFetHYXmnXymGnXnIzn2o+txBbHaMT3z8iwonyU/1MTHkvqC187e1lPnZUUYBK2GYwYIU+UNeZ/MiAj415penDFWliWORrLHdmMxsx7/KKHleWyY214wTQYSVzyD5JDkqC/0lDWkvzFEWEYjq/tm04Ryii6cF8JhTcyv2QWhSeYStQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=N3LuyELaiSC0sVNX2XPvkzFPVBktsV4F8YpUGnJ4zDs=; b=TYpsr1repY72zPZdO3mHI7gJxKhM5XuJ9023EZKVEdCeaL6pzTC/Du3vnI8UxbyUbs6td+SxNggKW97cTTAO2WkE57czCSCm3OFk4oKMBQ3MonZIVIX4c5Oq5woRG56w17zOQBO1RW6R7ocwQTxGMKZUpTs9h/kzdoL0ytH1nQbKe0OZPlvAXYNva5EJAvqxeQ0EyDpGt1NDgEuntzdaEwaVbmC7+oBzp4TZ8n4iH08M2FZmE3cZ5N7LgtpqLEMY2WQ9CrBinzB9i/fGtlMXQEv6HogZ4qwnuXrRNrgEHn/J4b7bh8qUVgdeLqjigiqHH72jUgq5HY6JXUhXM8bSCA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=N3LuyELaiSC0sVNX2XPvkzFPVBktsV4F8YpUGnJ4zDs=; b=Kve2s2i3flIVAmMnsavnMSX0rwa1ygxEkl8Jt/uetXmw/CjEkdMeQFtYnsfd5ruzKc07u/LvDSCSauLj4Eqh/Qy5Ka1XhMYKUzgmOgq5GW1ooTNblHh841n9ZTcZYxF/C3ttiK0hEOLE20m4L04S/ikvxbGwhaDKCm3AYwVdQSU= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by PAXPR04MB9668.eurprd04.prod.outlook.com (2603:10a6:102:243::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.24; Wed, 5 Jun 2024 01:13:46 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::557f:6fcf:a5a7:981c]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::557f:6fcf:a5a7:981c%7]) with mapi id 15.20.7633.021; Wed, 5 Jun 2024 01:13:46 +0000 From: "Peng Fan (OSS)" Date: Wed, 05 Jun 2024 09:22:48 +0800 Subject: [PATCH v6 1/3] dt-bindings: arm: fsl: add i.MX95 19x19 EVK board Message-Id: <20240605-imx95-dts-v3-v6-1-2ce275ed0e80@nxp.com> References: <20240605-imx95-dts-v3-v6-0-2ce275ed0e80@nxp.com> In-Reply-To: <20240605-imx95-dts-v3-v6-0-2ce275ed0e80@nxp.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Alexander Stein , Peng Fan , Conor Dooley X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717550578; l=938; i=peng.fan@nxp.com; s=20230812; h=from:subject:message-id; bh=hxkVlQeaJgJhLHSlZ83jW3veqMTWVj/bEjw+HMyTvrY=; b=czB6H2SSMtLXyWhIro1Gsp2bqjM7hdprdD++2n4jXXx2SbfgDtIn4gm/T5L3qIZPaSjEQA8sU 1whwQM/lnstCzMJwprVs5vj9OzAew9S+vTx/3YofvTCfFJ4TzToJjfl X-Developer-Key: i=peng.fan@nxp.com; a=ed25519; pk=I4sJg7atIT1g63H7bb5lDRGR2gJW14RKDD0wFL8TT1g= X-ClientProxiedBy: SI2PR01CA0028.apcprd01.prod.exchangelabs.com (2603:1096:4:192::21) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|PAXPR04MB9668:EE_ X-MS-Office365-Filtering-Correlation-Id: 0792e31c-44f6-40ea-f2f5-08dc84fcbfcc X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|7416005|52116005|1800799015|376005|366007|38350700005; X-Microsoft-Antispam-Message-Info: =?utf-8?q?RpFNU/55QXPhbScUdV6gHkBU4K+BFzU?= =?utf-8?q?8A63lXpER4jI//wRGKyuw5/vbw9STaXtvg5ucWpzo03zdBOmh2iKEpSnVl62aWA+W?= =?utf-8?q?5Anll/rXH2nYIlk96CIMvMqJfwUjmp1E7R4FVt85+307/GO/t3+EouEZDiGng8+J0?= =?utf-8?q?ke9aGlDCNJRw12sqV17zMiZHw6RNxkT8SdB0gBpln5zmynBgJt2HU5L5r8ausZ37D?= =?utf-8?q?pVHixzl7UlqyDd62pFWt0w+HrZTw/GeUYG5stNVBQsLtwzAXi0a3x7YoEpMkE00dC?= =?utf-8?q?jj3ytaG47IBZcbpmI9eVDFNpCdC8QEo/R0VGcKPGHDtlGAbrTyYbn94Bw7icScvvm?= =?utf-8?q?t/Im8P9uH3aTa4qS5zTlBGZ/dBwxAE6HiGYGNnGlgefer/ljyrowjBZ4/05SkqIAd?= =?utf-8?q?sqVjS4XEibaD/KCfAxhehm/xEff9NhvUD+H2th6adTYZ3wz+B+puZbsRKabak/flk?= =?utf-8?q?9D3m5QqklDV9r1nBmqh0wm+jcXQi/m4Un5ld8YyLmcFyA/fgGLyVH0hivh383OLYc?= =?utf-8?q?YBcLxjaONWl2GZ8WWcAsGM0+fi/sd87kHyVoiQYgbNNvYwtFM6gLJqd2pFphcz1kU?= =?utf-8?q?8q6Kk5kjw/UDp2Xfc28uyR5VMxrIBzocRjCGutRWKyLiXjdIVkvchpfXHsVFC6+AB?= =?utf-8?q?ll991kWGkSiX6BdPHoGXKWzDRoR5DVAH9/xlY94ViVtmamoNffCzhsU2kYlSS3bZY?= =?utf-8?q?FFuVqzWxy4t9T+Q342BwLGAH4DZ2LDCKmCgvzZZzrVJIDm5/oJ+jRArOIaoPvF4cH?= =?utf-8?q?8qO6mPbSGlSQdteTcIyxPAKokz9zWeRP4V6CZpgvmKIRgx/1uPMvrR2hkVPWSb8aJ?= =?utf-8?q?4DI9+0kknGhYRf/xJrLD6ZDlRB2WMGk+BMP51dxNSei8sQB4RWwuAmBALKP18EzDi?= =?utf-8?q?+MIkdNOGDU6OJnavb1fDW4cX4CwYF4dqJRR+Ax2HATmrKXDhP5BWpVTIxpOCGk+la?= =?utf-8?q?rR1U7FPR4EI3eBsT2/QLod6QlG92ZQOr5qg5e5z6h3ZsVK+ZqjO9MQdmYfZVrSgVz?= =?utf-8?q?HXYP1C3LtOlh7QlR5rUhk/kU527ThXLu7F/p+yHhItqhZ8skk6IASlRi3q3geAvKq?= =?utf-8?q?VmSf28ZeEQP58eGRHxJG2pfot4JQVQiaxaUrLilFxYJw40HIofktAfd8tTWsDbwh1?= =?utf-8?q?dgE8Cefibqy1ftftJrns1jd3udtGJntemIHemj4X6XY7WcmRU2hL4kvMeiYa1TJ8D?= =?utf-8?q?FImSiUX6yMiVWYgJp57Rwqz3uJORD1e6LFw0pSv9OpyltDZ34EubZPvy2abyjBzfP?= =?utf-8?q?db6s9NwjJBtH1W5u2F3GuO8t/qdluc1XnMQ=3D=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DU0PR04MB9417.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(7416005)(52116005)(1800799015)(376005)(366007)(38350700005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?0DiRZsMWra9xpKxvvJ/pySsob62o?= =?utf-8?q?nDLX45hXID4/DOr2u64nn0h8uD6+I8y6bIGWCt0fc40YcwL/YSfsa8O6LGcYQc2mG?= =?utf-8?q?k+P3md+XPFi4ay/KhlqEPHy6GeD8F/LnYNe5s7aCFsg6gnWA/1fL3T+8/XRxJid1I?= =?utf-8?q?xqtQ9lKabVR/8G39dLi7et2rm43+0R8P6xT1A1HrKprK6DQETH5ZCS4ESxAq8YA39?= =?utf-8?q?V71KodebK1wTvx8VCo4a9SYPbECO2xD9kqThLMdvM7FViq5I5o3kTttjPGIcETxcd?= =?utf-8?q?btne+slpw9OM4Ezu5iwIG5mJhueZVLZ/98ETlkHgDBGsWo0yg7Z/CdLoCdmsRyhEk?= =?utf-8?q?ljy3Y+bPZhqKGSxcqnmR2H+3qQg/bz0mB/+GW+yxcMJR8GjgW2hM/IakXAIMVuNFP?= =?utf-8?q?7UrSbqyGJ+hZJMFZU9oHWxRiS5BGKPf/dicZMLM48y9DZRLmPPOeaOor6Qk6TsVgX?= =?utf-8?q?ENtJRYZBKyzqTMSnoaaoIdp6LfP9gocJlV9CJWOHnpepmLrRlTYdDhxAJjIKB6l3X?= =?utf-8?q?A20hIF0AYzc1lr6ngu+XwPhgcEOQtbRyDExsMeHVDXBX0aC9QfadCJfZpyro68H8S?= =?utf-8?q?GyrsxB1cDbfZpr4MvNhJMXeB9Yn2sMd0Ur09hbNFJNx3TgNiNDikBsuSkr6liqI8K?= =?utf-8?q?9psdSIPVfWdjlk8YSMqBs29oQCpSzzvdA0sUu6nTOrHbsQILDscpYOGe0TbOFkZFC?= =?utf-8?q?e7XgrwUYNCA//+g/Fo4/0UIgLyGAbjwy20kgqeXaTrrN4eHUbT2/UGqT8JtzRTzZY?= =?utf-8?q?zKkIJWI14zGPlLDsXM5yD0kLUEozJBUgM1xhA6YcWdK0UD44lYIbJis9hO9qomXna?= =?utf-8?q?hohZY2jr/kHoVWWFIfY0M/pGrs+bPTBS64PxiKUlI83Tq9wo2Ss0Yi1+YrJo8BTZT?= =?utf-8?q?3C/0AocQv+kkTyNsIoT1loYo9gbEv6Ms09vNiIpd+avJE65zYMKzS7q67lZo7fw4R?= =?utf-8?q?NhJGEN9eu90G1mULRd3KL6RzFWhYUZkzdR82fpZSvmEck6aptGqkED/r0DJJyin2K?= =?utf-8?q?8KqDUhKLJn1PFdkTTw1OokQTVQvfc2Rv6LrhCMHf2Ic5L0F3GQhj9pr8YEPQxbV5l?= =?utf-8?q?PoV0A85nTek5Ax64RrrXP+FHMpAr6ThAd6dIReIzJ8k1nkHyUZqWlGpuA96tEgZTt?= =?utf-8?q?NQzvBnUUE5X54XMK9OwGbcxhVvlkin2UZjjzfrAcmtd6h2/Vz0u4v/edEoRnuxxDM?= =?utf-8?q?eek3olsnZ05uZ8hal998KMGCayb2zdAJeneN7jfo64UEDue4ElzlbTxOwpDosDU0C?= =?utf-8?q?93YXYdAeqPoqkbQyv/VISmOb/6O8nXNhRROqmVNXwf423NxhdSnz8kuDz5eJT0+I5?= =?utf-8?q?UbO47AacaSuG8B0zeWgG+eIRIMwKvYIGoUn0bEPeliUIBv5mCgJAktYBfpnAHBV8z?= =?utf-8?q?2kHDpYe8SJGiMHp45FLXSkP+0DFacycP6l/WjAXJ5Pe3D11Br/mU7iVuDNPslztLY?= =?utf-8?q?p9aFVO9xMolkZvZzsySAf4VwIcYLP2Wdv95arxe3I5kRwcu3aWOqrqgTsR56mvL1w?= =?utf-8?q?UWPJqVcTcQ+3?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0792e31c-44f6-40ea-f2f5-08dc84fcbfcc X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2024 01:13:46.4973 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: hZL21ukvXOof5r+OK8xT52mZAMFSNSbzIhoEUet6gq5yGKQoSTn2ywfAdOCr7FGSxytz85KjhVCapr2HpDJaLw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB9668 From: Peng Fan Add DT compatible string for NXP i.MX95 19x19 EVK board. Acked-by: Conor Dooley Signed-off-by: Peng Fan --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 6d185d09cb6a..5c9014087c17 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1275,6 +1275,12 @@ properties: - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 + - description: i.MX95 based Boards + items: + - enum: + - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board + - const: fsl,imx95 + - description: i.MXRT1050 based Boards items: - enum: From patchwork Wed Jun 5 01:22:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13686077 Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2050.outbound.protection.outlook.com [40.107.105.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF76D1BDDF for ; Wed, 5 Jun 2024 01:13:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.105.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717550041; cv=fail; b=a8eDv74dIDFUAsjbxPk+SZmluDxFEpQCJCV6HU4XRUpZlbxaI4eEdfpDJScMld2MECJow2QZ0/lrvN4MzWGjHjXD2HIMT6x/A/np/CAJQ15nANfzMrn1k/Jj86UHkOFbp8KUEyRSWHfpfv58bV5Mz4LPOMEIqj2w23lLFZUlLjE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717550041; c=relaxed/simple; bh=ky3F8Abc3hI/WKfIygcQIP4cJ01gUzGvFhNkVkdyxIc=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=EDv+PYith+6qjfGldwInNZ20mzQJ0bCKtGFlpeMkBbpaijsFQHZF5/UdNwmRzA//DAyvRM6+yd5puieB6oGlAG9+LWbOiheUmNs9ZL3NMOfEPzQ0XQkGqcOaqP9OSUSNiyAsSV1Ezp9TDBC85yGBpsyKSiZ/usSnmVDLGzYSMeM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (1024-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=h8rNOib2; arc=fail smtp.client-ip=40.107.105.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="h8rNOib2" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=FrUaffXNenUVHXiM8JQ/oBpRQPcJWs82BHl2203/X0lE3s7VVaQWplNzTSuvq4YfRuWkinSVM/2jlHdb0UKrsU9c3I1sGLrP2NEMuvGemYodcww4SWPGW8yBrCNYPzoNor27OxDhlk4PYjvRwmlccSMIc9rAGdHAw8qyVtQdubmHoxnD7cykF2UBM5ZylIicFk0/NIWUY4LHr3/j+I9W8XPxFbwmV+qTgtd2jHMlJoY49uMBlZJdk3gPNuFzmkO6FwE2xLWaaltkN4CuVlxC0ENXqLzx1JH0gjKDvvnsQM8R+bOoVFmvKSmtIop8x9a65CCRnY3W4c0irnG+JCzplw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MdqSP9j0ztuqLIvzIwILzbcJ0ccrWMi9RTlozOFOiX8=; b=ZpPPiYTpboidCe0Qxid3DGqJK0XHas0jqcK5VizTYb9YfwkQX0Dk2TiH336m3Sfk8xIqqD6OZ7usz0JQTeiluHA8x97tuJtelgD/QRtFohyALGvD4807ml5Mlmj0GBpOEVicGjpFQPz5enZtQxxTNFsu4uIgSduHx4dVusCQZ5dUv0pHpsktjDEB26umtPuvfHQlh+WfhH7+GRof25Fg0jkcg16NkmCV+lZefGGKv6YCW+JuDZTbzWzTc+AX4kSfOvBrZSZrhJR8BwQr6PXFQkdKeUu4cFSqYhoQqI+abAsruv9cWBn+JA4zQ3gxMGJgXeczk9pDsNKjfLvhySADxg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MdqSP9j0ztuqLIvzIwILzbcJ0ccrWMi9RTlozOFOiX8=; b=h8rNOib2itC5sbC5+GpT+iJCJiwVVukTYdi9mJovo6NXTvZKfltvwPS+b+Y9GUm91MVdWA3MmlCDgHeU4xcM+xplOJvCn2CIhTzgio2aMrtck6tjZgkLEcJe1W9L3owwEjYvb92QTmBSYtzIKS3pHUf9rIiLFCCavLmgK61Qwp8= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by PAXPR04MB9668.eurprd04.prod.outlook.com (2603:10a6:102:243::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.24; Wed, 5 Jun 2024 01:13:51 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::557f:6fcf:a5a7:981c]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::557f:6fcf:a5a7:981c%7]) with mapi id 15.20.7633.021; Wed, 5 Jun 2024 01:13:51 +0000 From: "Peng Fan (OSS)" Date: Wed, 05 Jun 2024 09:22:49 +0800 Subject: [PATCH v6 2/3] arm64: dts: freescale: add i.MX95 basic dtsi Message-Id: <20240605-imx95-dts-v3-v6-2-2ce275ed0e80@nxp.com> References: <20240605-imx95-dts-v3-v6-0-2ce275ed0e80@nxp.com> In-Reply-To: <20240605-imx95-dts-v3-v6-0-2ce275ed0e80@nxp.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Alexander Stein , Peng Fan X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717550578; l=120205; i=peng.fan@nxp.com; s=20230812; h=from:subject:message-id; bh=X8YzpTOkWMS7Dk+NKORg3toHoYYifP1UhT5v/4HQd74=; b=SBpP+yAwc2jtvA0B7ySyjaGtEfn4rD010dIL4PCpPzJHhZKJyek8xPSW01WF0ZLXEDqcGrvEi Cfzg7fLkyBzCmnWvGNuXb+a0ZZ95O4Sq2cVONUGqzCLfMwX3KhzWohh X-Developer-Key: i=peng.fan@nxp.com; a=ed25519; pk=I4sJg7atIT1g63H7bb5lDRGR2gJW14RKDD0wFL8TT1g= X-ClientProxiedBy: SI2PR01CA0028.apcprd01.prod.exchangelabs.com (2603:1096:4:192::21) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|PAXPR04MB9668:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d25c872-5bd4-4a59-aaf4-08dc84fcc277 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|7416005|52116005|1800799015|376005|366007|38350700005; X-Microsoft-Antispam-Message-Info: =?utf-8?q?WjLZa5FU1BI/AN1yNfWOVMTkGu9CyG9?= =?utf-8?q?ABPS6OTAj6Bv9czhEtFSnPuwaKQl5CCy4OGXIlLv1uFotbIwZapM3zKlWb70ck99F?= =?utf-8?q?BU7GmwUEUsvG/LxF6PdsBV4MOsrO+axsEJxUfQwNoVIPz7zxKuxzo3x7VuKXrZ0KC?= =?utf-8?q?SfEEzFL5YzC5CMlgHim2ybUaq08pfaTIYFx0H2OD8js56tzW8zkP0TLm0ptg/QLEW?= =?utf-8?q?z7JMXUbR3DzMfYOTF7UZvGFyS5dIZVYChcMzQdCTJuoFzVM+2sLjB6Z27I3ATORQu?= =?utf-8?q?p0ic0pTiFGqCrrR7A2SeCFsdp+NyBLTm0Y2WH6iZ2ynLYaNouaS5A+ge/403lDuu6?= =?utf-8?q?7uUKWa6fAI6SH6DE/TZIBJAz73z80YCpbWjsLS0+J4DmqV5ldxHPF0zj62BC7H1q/?= =?utf-8?q?rCKY+ouzIszFASJr8VxSv3q/dSNderljn3myxb6DrnOtXXsw1AHoulDBb+nDv6E1l?= =?utf-8?q?26l8liORjuDonuzHse4vrtt3krMGJAnclHI7loN6jx9ZkZpGZxF6yrHellu8vTF7R?= =?utf-8?q?+Z33Ft3qK0F2jDv8yp0ixYgT8ZcMSvATGElNV+YlFhpsYzGqR+2zY1QlapAkv1iqz?= =?utf-8?q?jLvf+4Weviu7pi58x+cBGCi9Pb+L6mlSOSn0cVN1OBDKgVA7kdUDI2y1hWyR+drpE?= =?utf-8?q?1IzjkOhcPPpxF+82uu7+2wS4oIMLQ5sQRmkwixPMUQ5VHqM/RuygJeGvr5Uux2eiE?= =?utf-8?q?+VEaPoDp8J/mefs5R51g8JlVn1THYPM9xK0Zw8uBRUjjyNqTTi3JD60k2GcOVoiwe?= =?utf-8?q?8lwzMlHbIiRXWVt2vmdgVvUD11e8du2NmAF+qodBf3+ZFp7ZY3hw0uP59F2e+QGTB?= =?utf-8?q?HzudYr9GmWQy2yLGWejXRrwRyfNL7WtUUkMP/Odj+YaN/2XThjW6fMsjagzpo0AVg?= =?utf-8?q?rr5tmBWZEsoP44XLvQLtl5MjGUSZ7JFaKDqDeO7D7iBRTdFJIDnSEsS/xI7M6J5ka?= =?utf-8?q?P6vl5ylty9MOvgtm3PwadYJuvGn9Y65WBWbKCozR8dkzCirpToJRozIPoN1nNX5wL?= =?utf-8?q?AuaWAR82Oz4Zcgxc0TmlCmnIAp5iOjJSJRoD+aLGtx5mjXxAxOkSr7GRg574Uz5Nj?= =?utf-8?q?/MXNBWy0uh0cBDdEeef4pRblJ5Cv7+tvTRYeJc06p54xR7LxOppNCTEHLNMtcROPV?= =?utf-8?q?nnXZBMxt/cDqYzn6bb4Z/wb1RbZjvmeOxkQnYGDJHVP4cdjEZxxzTAS4YwH14nDq/?= =?utf-8?q?qOnChHmbnItU6CJVRgxoB0lHemUcGQJgJNT03VXAL1ox9g7ibJHEFEYKqYrY6xtbr?= =?utf-8?q?V/5Q1zcs99nR5?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DU0PR04MB9417.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(7416005)(52116005)(1800799015)(376005)(366007)(38350700005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?FmU65uB3hXJZRdiTLbKLJHZvhkNu?= =?utf-8?q?Dxjq6Sx1SKMZjGJHvaHJ1DAJ4JFGhMbmPwRyl0r4YxbW3/5lfyrP5rWL9fZJZrR9m?= =?utf-8?q?Ug8mFe/W53YdIolDL+NR4QTCK0QmPgjMdyzZoVNA3ZZyCfF3FLzHqHO/VhcRFrUQJ?= =?utf-8?q?lhEaJek1QgkohxGdcZfmVORljvtrxEP8m6fXwQ/miLPsBzgpaT0f/Be71NxuoGqOg?= =?utf-8?q?5AewGQ4iQaRz4lT99D9rM5EV3WfEBngjs7A+tWl7S2zYATAtmwFxxJeIgP10/Nw0A?= =?utf-8?q?9KU3SDLHwva//0/qOKCHNENdNGHXe2AKWQDFQCBiYbRQXAz+tJhplDyXTZim0PXY7?= =?utf-8?q?SkieocA/wgDnNEE1BvCVPrWAcfbhnbgfhgbnKqJwls+9/LkNHeaJ6di2MZ9T72hb4?= =?utf-8?q?DQtFE82wJUYJm7xVYR4zx+e0GJRorQU3YuU0SFV6y+teaMwPiPcFDKVEz+lyud2Ow?= =?utf-8?q?DyV/uIkaZduYD95yb64o4KBXwl+5HBYITJnXo4O0ddOCMlAnwci+/3NxdQ9ljOEtL?= =?utf-8?q?sBQ9YTsRWo/E3S5O2O/74DtOrKBB9dSdkaSJPGYIrNzXnEec7ePZyfwRIivFeInxw?= =?utf-8?q?/07LR3k3lyg9oXbxo7vQagY8xD/gSo2gJDqId7OkBy856WfwXiolvxeR/yVP4790y?= =?utf-8?q?BpDWCXwl0OazqSrsDIn9TBPbBRjGtU3TTEziIT+mcQz29bch59uyWs5u4usXDm5dr?= =?utf-8?q?AgyBbrgndgyJPTEglKJjK0TcZbKoEGi/OB5BcPlmVjCQIrb+r5oO6jRWKRxrcmupP?= =?utf-8?q?g7m0ETIKyRECQBNRBWevwKnvVgZe3sZh+rDOCxPFBQEuw4Z2KjHLJPi76Aed7cFrU?= =?utf-8?q?1harMExhp7Rft+IBSdfEeA5s7q5ga3G1iYFRCScsQgBr0XVvYab+YnYQBhRwlnJcB?= =?utf-8?q?8I2aL33CnXKvc3SBNt5wc16H7hbrwcNpVg6qC7p+37d1BmBqg0HUj2jzE5s8gO1g7?= =?utf-8?q?PaFVu3Ms66P/gbdPooM9yTo8y9ZHtN8IOCbgWd40qQokyTjooEyWFfAWxdY08OHi8?= =?utf-8?q?ctUhzJdQTz1A1M+nBxerlE/SVFsowgBvERs5Lj9WQZhhp7RBIfYSTIIGupvs+LDWX?= =?utf-8?q?07+Ws1/MlNG63sdrku93hbWz6yR7hrHOnX3Z0ED0gtYOa3Mas5Wtw0sktKXUpiK64?= =?utf-8?q?ckqSulscED3wq9tYY+qnRsShTuItRV5Ge6T+I2N2BusfrTo8r7Kz8ejEfaB+Bb89Q?= =?utf-8?q?VhlDZ+s2hBZH6OVvHD5uMM/9tOD784ePyOpUtE/x55dPsgxvOu5z5irZwDaNjrMen?= =?utf-8?q?u2NYbXZgZl3ipnI+DFTPQzfkxmtP71uuaZhMuJ3ly8tRs3k+GhfgF/3dUoCJfDdF4?= =?utf-8?q?zw6lcovid+ztM404Y1UJ6YWT1vch3heNHjqpE3+h4CL1tVcvpHnRU3A58kXGed43I?= =?utf-8?q?ZpNV0jF/Tvew9gd7w//DcD2r7kQlcPfOPkAU0FbW+B4TNFVvPU6fxejMVeZVjG8cC?= =?utf-8?q?hhhbuXTuaqFClZl5rH4jUI3X9vTM2NXMdW2akUDYJuRYvXnJJ0rchigSBAY2Z6umo?= =?utf-8?q?rLR5cUTuPtoD?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3d25c872-5bd4-4a59-aaf4-08dc84fcc277 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2024 01:13:51.3937 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: AmKgfqKEmEYQqgcWb0VORoqieDF3wDI6C8DrAc2BePY5361vp42QMDNgANPeCW5MMCNFBTJMgiaXXUMMr6jV7A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB9668 From: Peng Fan i.MX95 features 6 A55 Cores, ARM Mali GPU, ISP, ML acceleration NPU, and Edgelock secure enclave security. This patch is to add a minimal dtsi, with cpu cores, scmi, gic, uart, mu, sdhc, lpi2c added. Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx95-clock.h | 187 +++++ arch/arm64/boot/dts/freescale/imx95-pinfunc.h | 865 ++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx95-power.h | 47 ++ arch/arm64/boot/dts/freescale/imx95.dtsi | 1063 +++++++++++++++++++++++++ 4 files changed, 2162 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-clock.h b/arch/arm64/boot/dts/freescale/imx95-clock.h new file mode 100644 index 000000000000..5badaace3148 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-clock.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Copyright 2024 NXP + */ + +#ifndef __CLOCK_IMX95_H +#define __CLOCK_IMX95_H + +/* The index should match i.MX95 SCMI Firmware */ +#define IMX95_CLK_32K 1 +#define IMX95_CLK_24M 2 +#define IMX95_CLK_FRO 3 +#define IMX95_CLK_SYSPLL1_VCO 4 +#define IMX95_CLK_SYSPLL1_PFD0_UNGATED 5 +#define IMX95_CLK_SYSPLL1_PFD0 6 +#define IMX95_CLK_SYSPLL1_PFD0_DIV2 7 +#define IMX95_CLK_SYSPLL1_PFD1_UNGATED 8 +#define IMX95_CLK_SYSPLL1_PFD1 9 +#define IMX95_CLK_SYSPLL1_PFD1_DIV2 10 +#define IMX95_CLK_SYSPLL1_PFD2_UNGATED 11 +#define IMX95_CLK_SYSPLL1_PFD2 12 +#define IMX95_CLK_SYSPLL1_PFD2_DIV2 13 +#define IMX95_CLK_AUDIOPLL1_VCO 14 +#define IMX95_CLK_AUDIOPLL1 15 +#define IMX95_CLK_AUDIOPLL2_VCO 16 +#define IMX95_CLK_AUDIOPLL2 17 +#define IMX95_CLK_VIDEOPLL1_VCO 18 +#define IMX95_CLK_VIDEOPLL1 19 +#define IMX95_CLK_RESERVED20 20 +#define IMX95_CLK_RESERVED21 21 +#define IMX95_CLK_RESERVED22 22 +#define IMX95_CLK_RESERVED23 23 +#define IMX95_CLK_ARMPLL_VCO 24 +#define IMX95_CLK_ARMPLL_PFD0_UNGATED 25 +#define IMX95_CLK_ARMPLL_PFD0 26 +#define IMX95_CLK_ARMPLL_PFD1_UNGATED 27 +#define IMX95_CLK_ARMPLL_PFD1 28 +#define IMX95_CLK_ARMPLL_PFD2_UNGATED 29 +#define IMX95_CLK_ARMPLL_PFD2 30 +#define IMX95_CLK_ARMPLL_PFD3_UNGATED 31 +#define IMX95_CLK_ARMPLL_PFD3 32 +#define IMX95_CLK_DRAMPLL_VCO 33 +#define IMX95_CLK_DRAMPLL 34 +#define IMX95_CLK_HSIOPLL_VCO 35 +#define IMX95_CLK_HSIOPLL 36 +#define IMX95_CLK_LDBPLL_VCO 37 +#define IMX95_CLK_LDBPLL 38 +#define IMX95_CLK_EXT1 39 +#define IMX95_CLK_EXT2 40 + +#define IMX95_CCM_NUM_CLK_SRC 41 + +#define IMX95_CLK_ADC (IMX95_CCM_NUM_CLK_SRC + 0) +#define IMX95_CLK_TMU (IMX95_CCM_NUM_CLK_SRC + 1) +#define IMX95_CLK_BUSAON (IMX95_CCM_NUM_CLK_SRC + 2) +#define IMX95_CLK_CAN1 (IMX95_CCM_NUM_CLK_SRC + 3) +#define IMX95_CLK_I3C1 (IMX95_CCM_NUM_CLK_SRC + 4) +#define IMX95_CLK_I3C1SLOW (IMX95_CCM_NUM_CLK_SRC + 5) +#define IMX95_CLK_LPI2C1 (IMX95_CCM_NUM_CLK_SRC + 6) +#define IMX95_CLK_LPI2C2 (IMX95_CCM_NUM_CLK_SRC + 7) +#define IMX95_CLK_LPSPI1 (IMX95_CCM_NUM_CLK_SRC + 8) +#define IMX95_CLK_LPSPI2 (IMX95_CCM_NUM_CLK_SRC + 9) +#define IMX95_CLK_LPTMR1 (IMX95_CCM_NUM_CLK_SRC + 10) +#define IMX95_CLK_LPUART1 (IMX95_CCM_NUM_CLK_SRC + 11) +#define IMX95_CLK_LPUART2 (IMX95_CCM_NUM_CLK_SRC + 12) +#define IMX95_CLK_M33 (IMX95_CCM_NUM_CLK_SRC + 13) +#define IMX95_CLK_M33SYSTICK (IMX95_CCM_NUM_CLK_SRC + 14) +#define IMX95_CLK_MQS1 (IMX95_CCM_NUM_CLK_SRC + 15) +#define IMX95_CLK_PDM (IMX95_CCM_NUM_CLK_SRC + 16) +#define IMX95_CLK_SAI1 (IMX95_CCM_NUM_CLK_SRC + 17) +#define IMX95_CLK_SENTINEL (IMX95_CCM_NUM_CLK_SRC + 18) +#define IMX95_CLK_TPM2 (IMX95_CCM_NUM_CLK_SRC + 19) +#define IMX95_CLK_TSTMR1 (IMX95_CCM_NUM_CLK_SRC + 20) +#define IMX95_CLK_CAMAPB (IMX95_CCM_NUM_CLK_SRC + 21) +#define IMX95_CLK_CAMAXI (IMX95_CCM_NUM_CLK_SRC + 22) +#define IMX95_CLK_CAMCM0 (IMX95_CCM_NUM_CLK_SRC + 23) +#define IMX95_CLK_CAMISI (IMX95_CCM_NUM_CLK_SRC + 24) +#define IMX95_CLK_MIPIPHYCFG (IMX95_CCM_NUM_CLK_SRC + 25) +#define IMX95_CLK_MIPIPHYPLLBYPASS (IMX95_CCM_NUM_CLK_SRC + 26) +#define IMX95_CLK_MIPIPHYPLLREF (IMX95_CCM_NUM_CLK_SRC + 27) +#define IMX95_CLK_MIPITESTBYTE (IMX95_CCM_NUM_CLK_SRC + 28) +#define IMX95_CLK_A55 (IMX95_CCM_NUM_CLK_SRC + 29) +#define IMX95_CLK_A55MTRBUS (IMX95_CCM_NUM_CLK_SRC + 30) +#define IMX95_CLK_A55PERIPH (IMX95_CCM_NUM_CLK_SRC + 31) +#define IMX95_CLK_DRAMALT (IMX95_CCM_NUM_CLK_SRC + 32) +#define IMX95_CLK_DRAMAPB (IMX95_CCM_NUM_CLK_SRC + 33) +#define IMX95_CLK_DISPAPB (IMX95_CCM_NUM_CLK_SRC + 34) +#define IMX95_CLK_DISPAXI (IMX95_CCM_NUM_CLK_SRC + 35) +#define IMX95_CLK_DISPDP (IMX95_CCM_NUM_CLK_SRC + 36) +#define IMX95_CLK_DISPOCRAM (IMX95_CCM_NUM_CLK_SRC + 37) +#define IMX95_CLK_DISPUSB31 (IMX95_CCM_NUM_CLK_SRC + 38) +#define IMX95_CLK_DISP1PIX (IMX95_CCM_NUM_CLK_SRC + 39) +#define IMX95_CLK_DISP2PIX (IMX95_CCM_NUM_CLK_SRC + 40) +#define IMX95_CLK_DISP3PIX (IMX95_CCM_NUM_CLK_SRC + 41) +#define IMX95_CLK_GPUAPB (IMX95_CCM_NUM_CLK_SRC + 42) +#define IMX95_CLK_GPU (IMX95_CCM_NUM_CLK_SRC + 43) +#define IMX95_CLK_HSIOACSCAN480M (IMX95_CCM_NUM_CLK_SRC + 44) +#define IMX95_CLK_HSIOACSCAN80M (IMX95_CCM_NUM_CLK_SRC + 45) +#define IMX95_CLK_HSIO (IMX95_CCM_NUM_CLK_SRC + 46) +#define IMX95_CLK_HSIOPCIEAUX (IMX95_CCM_NUM_CLK_SRC + 47) +#define IMX95_CLK_HSIOPCIETEST160M (IMX95_CCM_NUM_CLK_SRC + 48) +#define IMX95_CLK_HSIOPCIETEST400M (IMX95_CCM_NUM_CLK_SRC + 49) +#define IMX95_CLK_HSIOPCIETEST500M (IMX95_CCM_NUM_CLK_SRC + 50) +#define IMX95_CLK_HSIOUSBTEST50M (IMX95_CCM_NUM_CLK_SRC + 51) +#define IMX95_CLK_HSIOUSBTEST60M (IMX95_CCM_NUM_CLK_SRC + 52) +#define IMX95_CLK_BUSM7 (IMX95_CCM_NUM_CLK_SRC + 53) +#define IMX95_CLK_M7 (IMX95_CCM_NUM_CLK_SRC + 54) +#define IMX95_CLK_M7SYSTICK (IMX95_CCM_NUM_CLK_SRC + 55) +#define IMX95_CLK_BUSNETCMIX (IMX95_CCM_NUM_CLK_SRC + 56) +#define IMX95_CLK_ENET (IMX95_CCM_NUM_CLK_SRC + 57) +#define IMX95_CLK_ENETPHYTEST200M (IMX95_CCM_NUM_CLK_SRC + 58) +#define IMX95_CLK_ENETPHYTEST500M (IMX95_CCM_NUM_CLK_SRC + 59) +#define IMX95_CLK_ENETPHYTEST667M (IMX95_CCM_NUM_CLK_SRC + 60) +#define IMX95_CLK_ENETREF (IMX95_CCM_NUM_CLK_SRC + 61) +#define IMX95_CLK_ENETTIMER1 (IMX95_CCM_NUM_CLK_SRC + 62) +#define IMX95_CLK_MQS2 (IMX95_CCM_NUM_CLK_SRC + 63) +#define IMX95_CLK_SAI2 (IMX95_CCM_NUM_CLK_SRC + 64) +#define IMX95_CLK_NOCAPB (IMX95_CCM_NUM_CLK_SRC + 65) +#define IMX95_CLK_NOC (IMX95_CCM_NUM_CLK_SRC + 66) +#define IMX95_CLK_NPUAPB (IMX95_CCM_NUM_CLK_SRC + 67) +#define IMX95_CLK_NPU (IMX95_CCM_NUM_CLK_SRC + 68) +#define IMX95_CLK_CCMCKO1 (IMX95_CCM_NUM_CLK_SRC + 69) +#define IMX95_CLK_CCMCKO2 (IMX95_CCM_NUM_CLK_SRC + 70) +#define IMX95_CLK_CCMCKO3 (IMX95_CCM_NUM_CLK_SRC + 71) +#define IMX95_CLK_CCMCKO4 (IMX95_CCM_NUM_CLK_SRC + 72) +#define IMX95_CLK_VPUAPB (IMX95_CCM_NUM_CLK_SRC + 73) +#define IMX95_CLK_VPU (IMX95_CCM_NUM_CLK_SRC + 74) +#define IMX95_CLK_VPUDSP (IMX95_CCM_NUM_CLK_SRC + 75) +#define IMX95_CLK_VPUJPEG (IMX95_CCM_NUM_CLK_SRC + 76) +#define IMX95_CLK_AUDIOXCVR (IMX95_CCM_NUM_CLK_SRC + 77) +#define IMX95_CLK_BUSWAKEUP (IMX95_CCM_NUM_CLK_SRC + 78) +#define IMX95_CLK_CAN2 (IMX95_CCM_NUM_CLK_SRC + 79) +#define IMX95_CLK_CAN3 (IMX95_CCM_NUM_CLK_SRC + 80) +#define IMX95_CLK_CAN4 (IMX95_CCM_NUM_CLK_SRC + 81) +#define IMX95_CLK_CAN5 (IMX95_CCM_NUM_CLK_SRC + 82) +#define IMX95_CLK_FLEXIO1 (IMX95_CCM_NUM_CLK_SRC + 83) +#define IMX95_CLK_FLEXIO2 (IMX95_CCM_NUM_CLK_SRC + 84) +#define IMX95_CLK_FLEXSPI1 (IMX95_CCM_NUM_CLK_SRC + 85) +#define IMX95_CLK_I3C2 (IMX95_CCM_NUM_CLK_SRC + 86) +#define IMX95_CLK_I3C2SLOW (IMX95_CCM_NUM_CLK_SRC + 87) +#define IMX95_CLK_LPI2C3 (IMX95_CCM_NUM_CLK_SRC + 88) +#define IMX95_CLK_LPI2C4 (IMX95_CCM_NUM_CLK_SRC + 89) +#define IMX95_CLK_LPI2C5 (IMX95_CCM_NUM_CLK_SRC + 90) +#define IMX95_CLK_LPI2C6 (IMX95_CCM_NUM_CLK_SRC + 91) +#define IMX95_CLK_LPI2C7 (IMX95_CCM_NUM_CLK_SRC + 92) +#define IMX95_CLK_LPI2C8 (IMX95_CCM_NUM_CLK_SRC + 93) +#define IMX95_CLK_LPSPI3 (IMX95_CCM_NUM_CLK_SRC + 94) +#define IMX95_CLK_LPSPI4 (IMX95_CCM_NUM_CLK_SRC + 95) +#define IMX95_CLK_LPSPI5 (IMX95_CCM_NUM_CLK_SRC + 96) +#define IMX95_CLK_LPSPI6 (IMX95_CCM_NUM_CLK_SRC + 97) +#define IMX95_CLK_LPSPI7 (IMX95_CCM_NUM_CLK_SRC + 98) +#define IMX95_CLK_LPSPI8 (IMX95_CCM_NUM_CLK_SRC + 99) +#define IMX95_CLK_LPTMR2 (IMX95_CCM_NUM_CLK_SRC + 100) +#define IMX95_CLK_LPUART3 (IMX95_CCM_NUM_CLK_SRC + 101) +#define IMX95_CLK_LPUART4 (IMX95_CCM_NUM_CLK_SRC + 102) +#define IMX95_CLK_LPUART5 (IMX95_CCM_NUM_CLK_SRC + 103) +#define IMX95_CLK_LPUART6 (IMX95_CCM_NUM_CLK_SRC + 104) +#define IMX95_CLK_LPUART7 (IMX95_CCM_NUM_CLK_SRC + 105) +#define IMX95_CLK_LPUART8 (IMX95_CCM_NUM_CLK_SRC + 106) +#define IMX95_CLK_SAI3 (IMX95_CCM_NUM_CLK_SRC + 107) +#define IMX95_CLK_SAI4 (IMX95_CCM_NUM_CLK_SRC + 108) +#define IMX95_CLK_SAI5 (IMX95_CCM_NUM_CLK_SRC + 109) +#define IMX95_CLK_SPDIF (IMX95_CCM_NUM_CLK_SRC + 110) +#define IMX95_CLK_SWOTRACE (IMX95_CCM_NUM_CLK_SRC + 111) +#define IMX95_CLK_TPM4 (IMX95_CCM_NUM_CLK_SRC + 112) +#define IMX95_CLK_TPM5 (IMX95_CCM_NUM_CLK_SRC + 113) +#define IMX95_CLK_TPM6 (IMX95_CCM_NUM_CLK_SRC + 114) +#define IMX95_CLK_TSTMR2 (IMX95_CCM_NUM_CLK_SRC + 115) +#define IMX95_CLK_USBPHYBURUNIN (IMX95_CCM_NUM_CLK_SRC + 116) +#define IMX95_CLK_USDHC1 (IMX95_CCM_NUM_CLK_SRC + 117) +#define IMX95_CLK_USDHC2 (IMX95_CCM_NUM_CLK_SRC + 118) +#define IMX95_CLK_USDHC3 (IMX95_CCM_NUM_CLK_SRC + 119) +#define IMX95_CLK_V2XPK (IMX95_CCM_NUM_CLK_SRC + 120) +#define IMX95_CLK_WAKEUPAXI (IMX95_CCM_NUM_CLK_SRC + 121) +#define IMX95_CLK_XSPISLVROOT (IMX95_CCM_NUM_CLK_SRC + 122) +#define IMX95_CLK_SEL_EXT (IMX95_CCM_NUM_CLK_SRC + 123 + 0) +#define IMX95_CLK_SEL_A55C0 (IMX95_CCM_NUM_CLK_SRC + 123 + 1) +#define IMX95_CLK_SEL_A55C1 (IMX95_CCM_NUM_CLK_SRC + 123 + 2) +#define IMX95_CLK_SEL_A55C2 (IMX95_CCM_NUM_CLK_SRC + 123 + 3) +#define IMX95_CLK_SEL_A55C3 (IMX95_CCM_NUM_CLK_SRC + 123 + 4) +#define IMX95_CLK_SEL_A55C4 (IMX95_CCM_NUM_CLK_SRC + 123 + 5) +#define IMX95_CLK_SEL_A55C5 (IMX95_CCM_NUM_CLK_SRC + 123 + 6) +#define IMX95_CLK_SEL_A55P (IMX95_CCM_NUM_CLK_SRC + 123 + 7) +#define IMX95_CLK_SEL_DRAM (IMX95_CCM_NUM_CLK_SRC + 123 + 8) +#define IMX95_CLK_SEL_TEMPSENSE (IMX95_CCM_NUM_CLK_SRC + 123 + 9) + +#endif /* __DT_BINDINGS_CLOCK_IMX95_H */ diff --git a/arch/arm64/boot/dts/freescale/imx95-pinfunc.h b/arch/arm64/boot/dts/freescale/imx95-pinfunc.h new file mode 100644 index 000000000000..9f614eea7c86 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-pinfunc.h @@ -0,0 +1,865 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2024 NXP + */ + +#ifndef __DTS_IMX95_PINFUNC_H +#define __DTS_IMX95_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00 +#define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00 +#define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00 +#define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00 +#define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00 +#define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00 +#define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00 + +#define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00 +#define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00 +#define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00 +#define IMX95_PAD_DAP_TMS_SWDIO__GPIO3_IO_BIT29 0x0004 0x0208 0x0000 0x05 0x00 +#define IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x0208 0x0000 0x06 0x00 + +#define IMX95_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x020C 0x060C 0x00 0x00 +#define IMX95_PAD_DAP_TCLK_SWCLK__CAN4_RX 0x0008 0x020C 0x044C 0x02 0x00 +#define IMX95_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO_BIT30 0x0008 0x020C 0x0460 0x04 0x00 +#define IMX95_PAD_DAP_TCLK_SWCLK__GPIO3_IO_BIT30 0x0008 0x020C 0x0000 0x05 0x00 +#define IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x020C 0x056C 0x06 0x00 + +#define IMX95_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x0210 0x0000 0x00 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_MQS2_RIGHT 0x000C 0x0210 0x0000 0x01 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_NETC_TMR_1588_ALARM 0x000C 0x0210 0x0000 0x02 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x0210 0x0444 0x03 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO_BIT31 0x000C 0x0210 0x0464 0x04 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__GPIO3_IO_BIT31 0x000C 0x0210 0x0000 0x05 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x0210 0x0574 0x06 0x00 + +#define IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x0010 0x0214 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x0214 0x0504 0x11 0x00 +#define IMX95_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x0214 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x0214 0x0574 0x05 0x01 +#define IMX95_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x0214 0x0514 0x16 0x00 +#define IMX95_PAD_GPIO_IO00__FLEXIO1_FLEXIO_BIT0 0x0010 0x0214 0x0468 0x07 0x00 + +#define IMX95_PAD_GPIO_IO01__GPIO2_IO_BIT1 0x0014 0x0218 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x0218 0x0500 0x11 0x00 +#define IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x0218 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x0218 0x0570 0x05 0x01 +#define IMX95_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x0218 0x0510 0x16 0x00 +#define IMX95_PAD_GPIO_IO01__FLEXIO1_FLEXIO_BIT1 0x0014 0x0218 0x046C 0x07 0x00 + +#define IMX95_PAD_GPIO_IO02__GPIO2_IO_BIT2 0x0018 0x021C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x021C 0x050C 0x11 0x00 +#define IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x021C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x021C 0x056C 0x05 0x01 +#define IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x021C 0x051C 0x16 0x00 +#define IMX95_PAD_GPIO_IO02__FLEXIO1_FLEXIO_BIT2 0x0018 0x021C 0x0470 0x07 0x00 + +#define IMX95_PAD_GPIO_IO03__GPIO2_IO_BIT3 0x001C 0x0220 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x0220 0x0508 0x11 0x00 +#define IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x0220 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x0220 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x0220 0x0518 0x16 0x00 +#define IMX95_PAD_GPIO_IO03__FLEXIO1_FLEXIO_BIT3 0x001C 0x0220 0x0474 0x07 0x00 + +#define IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x0020 0x0224 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x0224 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO04__AONMIX_TOP_PDM_CLK 0x0020 0x0224 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO04__CAN4_TX 0x0020 0x0224 0x0000 0x03 0x00 +#define IMX95_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x0224 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x0224 0x0580 0x05 0x01 +#define IMX95_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x0224 0x051C 0x16 0x01 +#define IMX95_PAD_GPIO_IO04__FLEXIO1_FLEXIO_BIT4 0x0020 0x0224 0x0478 0x07 0x00 + +#define IMX95_PAD_GPIO_IO05__GPIO2_IO_BIT5 0x0024 0x0228 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x0228 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO05__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x0024 0x0228 0x040C 0x02 0x01 +#define IMX95_PAD_GPIO_IO05__CAN4_RX 0x0024 0x0228 0x044C 0x03 0x01 +#define IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x0228 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x0228 0x057C 0x05 0x01 +#define IMX95_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x0228 0x0518 0x16 0x01 +#define IMX95_PAD_GPIO_IO05__FLEXIO1_FLEXIO_BIT5 0x0024 0x0228 0x047C 0x07 0x00 + +#define IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x0028 0x022C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x022C 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x0028 0x022C 0x0410 0x02 0x01 +#define IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x022C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x022C 0x0578 0x05 0x01 +#define IMX95_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x022C 0x0524 0x16 0x00 +#define IMX95_PAD_GPIO_IO06__FLEXIO1_FLEXIO_BIT6 0x0028 0x022C 0x0480 0x07 0x00 + +#define IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x002C 0x0230 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x0230 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x0230 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x0230 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x0230 0x0520 0x16 0x00 +#define IMX95_PAD_GPIO_IO07__FLEXIO1_FLEXIO_BIT7 0x002C 0x0230 0x0484 0x07 0x00 + +#define IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8 0x0030 0x0234 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x0234 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x0234 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x0234 0x0588 0x05 0x01 +#define IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x0234 0x0524 0x16 0x01 +#define IMX95_PAD_GPIO_IO08__FLEXIO1_FLEXIO_BIT8 0x0030 0x0234 0x0488 0x07 0x00 + +#define IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x0034 0x0238 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x0238 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x0238 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x0238 0x0584 0x05 0x01 +#define IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x0238 0x0520 0x16 0x01 +#define IMX95_PAD_GPIO_IO09__FLEXIO1_FLEXIO_BIT9 0x0034 0x0238 0x048C 0x07 0x00 + +#define IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x0038 0x023C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x023C 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x023C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x023C 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x023C 0x052C 0x16 0x00 +#define IMX95_PAD_GPIO_IO10__FLEXIO1_FLEXIO_BIT10 0x0038 0x023C 0x0490 0x07 0x00 + +#define IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x003C 0x0240 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x0240 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x0240 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x0240 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x0240 0x0528 0x16 0x00 +#define IMX95_PAD_GPIO_IO11__FLEXIO1_FLEXIO_BIT11 0x003C 0x0240 0x0494 0x07 0x00 + +#define IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12 0x0040 0x0244 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x0244 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x0040 0x0244 0x0414 0x02 0x00 +#define IMX95_PAD_GPIO_IO12__FLEXIO1_FLEXIO_BIT12 0x0040 0x0244 0x0498 0x03 0x00 +#define IMX95_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x0244 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x0244 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x0244 0x052C 0x16 0x01 +#define IMX95_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x0244 0x0590 0x07 0x00 + +#define IMX95_PAD_GPIO_IO13__GPIO2_IO_BIT13 0x0044 0x0248 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x0248 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x0044 0x0248 0x0418 0x02 0x00 +#define IMX95_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x0248 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x0248 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x0248 0x0528 0x16 0x01 +#define IMX95_PAD_GPIO_IO13__FLEXIO1_FLEXIO_BIT13 0x0044 0x0248 0x049C 0x07 0x00 + +#define IMX95_PAD_GPIO_IO14__GPIO2_IO_BIT14 0x0048 0x024C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x024C 0x055C 0x01 0x01 +#define IMX95_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x024C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x024C 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x024C 0x0568 0x06 0x01 +#define IMX95_PAD_GPIO_IO14__FLEXIO1_FLEXIO_BIT14 0x0048 0x024C 0x04A0 0x07 0x00 + +#define IMX95_PAD_GPIO_IO15__GPIO2_IO_BIT15 0x004C 0x0250 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x0250 0x0558 0x01 0x01 +#define IMX95_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x0250 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x0250 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x0250 0x0564 0x06 0x01 +#define IMX95_PAD_GPIO_IO15__FLEXIO1_FLEXIO_BIT15 0x004C 0x0250 0x04A4 0x07 0x00 + +#define IMX95_PAD_GPIO_IO16__GPIO2_IO_BIT16 0x0050 0x0254 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0254 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO16__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x0050 0x0254 0x0414 0x02 0x01 +#define IMX95_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0254 0x0554 0x04 0x01 +#define IMX95_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0254 0x0538 0x05 0x01 +#define IMX95_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0254 0x0560 0x06 0x01 +#define IMX95_PAD_GPIO_IO16__FLEXIO1_FLEXIO_BIT16 0x0050 0x0254 0x04A8 0x07 0x00 + +#define IMX95_PAD_GPIO_IO17__GPIO2_IO_BIT17 0x0054 0x0258 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0258 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0258 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0258 0x0534 0x05 0x01 +#define IMX95_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0258 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO17__FLEXIO1_FLEXIO_BIT17 0x0054 0x0258 0x04AC 0x07 0x00 + +#define IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x0058 0x025C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x025C 0x058C 0x01 0x00 +#define IMX95_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x025C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x025C 0x0530 0x05 0x01 +#define IMX95_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x025C 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO18__FLEXIO1_FLEXIO_BIT18 0x0058 0x025C 0x04B0 0x07 0x00 + +#define IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19 0x005C 0x0260 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x0260 0x0590 0x01 0x01 +#define IMX95_PAD_GPIO_IO19__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x005C 0x0260 0x0418 0x02 0x01 +#define IMX95_PAD_GPIO_IO19__FLEXIO1_FLEXIO_BIT19 0x005C 0x0260 0x04B4 0x03 0x00 +#define IMX95_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x0260 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x0260 0x0540 0x05 0x01 +#define IMX95_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x0260 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0 0x005C 0x0260 0x0000 0x07 0x00 + +#define IMX95_PAD_GPIO_IO20__GPIO2_IO_BIT20 0x0060 0x0264 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x0060 0x0264 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO20__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x0060 0x0264 0x040C 0x02 0x02 +#define IMX95_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0264 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0264 0x0544 0x05 0x01 +#define IMX95_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0264 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO20__FLEXIO1_FLEXIO_BIT20 0x0060 0x0264 0x04B8 0x07 0x00 + +#define IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21 0x0064 0x0268 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x0064 0x0268 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO21__AONMIX_TOP_PDM_CLK 0x0064 0x0268 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO21__FLEXIO1_FLEXIO_BIT21 0x0064 0x0268 0x04BC 0x03 0x00 +#define IMX95_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0268 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0268 0x053C 0x05 0x01 +#define IMX95_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0268 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0268 0x058C 0x07 0x01 + +#define IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x0068 0x026C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x026C 0x05C8 0x01 0x00 +#define IMX95_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x026C 0x0454 0x02 0x02 +#define IMX95_PAD_GPIO_IO22__CAN5_TX 0x0068 0x026C 0x0000 0x03 0x00 +#define IMX95_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x026C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x026C 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x026C 0x0514 0x16 0x01 +#define IMX95_PAD_GPIO_IO22__FLEXIO1_FLEXIO_BIT22 0x0068 0x026C 0x04C0 0x07 0x00 + +#define IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x006C 0x0270 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x0270 0x05CC 0x01 0x00 +#define IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x0270 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO23__CAN5_RX 0x006C 0x0270 0x0450 0x03 0x00 +#define IMX95_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x0270 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x0270 0x0510 0x16 0x01 +#define IMX95_PAD_GPIO_IO23__FLEXIO1_FLEXIO_BIT23 0x006C 0x0270 0x04C4 0x07 0x00 + +#define IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x0070 0x0274 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0274 0x05D0 0x01 0x00 +#define IMX95_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0274 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0274 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0274 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO24__FLEXIO1_FLEXIO_BIT24 0x0070 0x0274 0x04C8 0x07 0x00 + +#define IMX95_PAD_GPIO_IO25__GPIO2_IO_BIT25 0x0074 0x0278 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0278 0x05D4 0x01 0x00 +#define IMX95_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0278 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0278 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0278 0x060C 0x05 0x01 +#define IMX95_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0278 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO25__FLEXIO1_FLEXIO_BIT25 0x0074 0x0278 0x04CC 0x07 0x00 + +#define IMX95_PAD_GPIO_IO26__GPIO2_IO_BIT26 0x0078 0x027C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x027C 0x05D8 0x01 0x00 +#define IMX95_PAD_GPIO_IO26__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x0078 0x027C 0x0410 0x02 0x02 +#define IMX95_PAD_GPIO_IO26__FLEXIO1_FLEXIO_BIT26 0x0078 0x027C 0x0458 0x03 0x01 +#define IMX95_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x027C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x027C 0x0610 0x05 0x01 +#define IMX95_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x027C 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x027C 0x0000 0x07 0x00 + +#define IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x007C 0x0280 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x0280 0x05DC 0x01 0x00 +#define IMX95_PAD_GPIO_IO27__CAN2_RX 0x007C 0x0280 0x0444 0x02 0x02 +#define IMX95_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x0280 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x0280 0x0614 0x05 0x01 +#define IMX95_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x0280 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO27__FLEXIO1_FLEXIO_BIT27 0x007C 0x0280 0x045C 0x07 0x01 + +#define IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x0080 0x0284 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0284 0x0504 0x11 0x01 +#define IMX95_PAD_GPIO_IO28__CAN3_TX 0x0080 0x0284 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO28__FLEXIO1_FLEXIO_BIT28 0x0080 0x0284 0x0000 0x07 0x00 + +#define IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x0084 0x0288 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0288 0x0500 0x11 0x01 +#define IMX95_PAD_GPIO_IO29__CAN3_RX 0x0084 0x0288 0x0448 0x02 0x01 +#define IMX95_PAD_GPIO_IO29__FLEXIO1_FLEXIO_BIT29 0x0084 0x0288 0x0000 0x07 0x00 + +#define IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x0088 0x028C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x0088 0x028C 0x050C 0x11 0x01 +#define IMX95_PAD_GPIO_IO30__CAN5_TX 0x0088 0x028C 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO30__FLEXIO1_FLEXIO_BIT30 0x0088 0x028C 0x0460 0x07 0x01 + +#define IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x008C 0x0290 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x008C 0x0290 0x0508 0x11 0x01 +#define IMX95_PAD_GPIO_IO31__CAN5_RX 0x008C 0x0290 0x0450 0x02 0x01 +#define IMX95_PAD_GPIO_IO31__FLEXIO1_FLEXIO_BIT31 0x008C 0x0290 0x0464 0x07 0x01 + +#define IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x0090 0x0294 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x0090 0x0294 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO32__LPUART6_TX 0x0090 0x0294 0x0580 0x02 0x00 +#define IMX95_PAD_GPIO_IO32__LPSPI4_PCS2 0x0090 0x0294 0x0538 0x04 0x00 + +#define IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x0094 0x0298 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO33__LPUART6_RX 0x0094 0x0298 0x057C 0x02 0x00 +#define IMX95_PAD_GPIO_IO33__LPSPI4_PCS1 0x0094 0x0298 0x0534 0x04 0x00 + +#define IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x0098 0x029C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO34__LPUART6_CTS_B 0x0098 0x029C 0x0578 0x02 0x00 +#define IMX95_PAD_GPIO_IO34__LPSPI4_PCS0 0x0098 0x029C 0x0530 0x04 0x00 + +#define IMX95_PAD_GPIO_IO35__GPIO5_IO_BIT15 0x009C 0x02A0 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x009C 0x02A0 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO35__LPUART6_RTS_B 0x009C 0x02A0 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO35__LPSPI4_SIN 0x009C 0x02A0 0x0540 0x04 0x00 + +#define IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x00A0 0x02A4 0x0544 0x04 0x00 +#define IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x00A0 0x02A4 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO36__LPUART7_TX 0x00A0 0x02A4 0x0588 0x02 0x00 + +#define IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17 0x00A4 0x02A8 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO37__LPUART7_RX 0x00A4 0x02A8 0x0584 0x02 0x00 +#define IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x00A4 0x02A8 0x053C 0x04 0x00 + +#define IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x00A8 0x02AC 0x0000 0x00 0x00 +#define IMX95_PAD_CCM_CLKO1__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x00A8 0x02AC 0x0434 0x01 0x00 +#define IMX95_PAD_CCM_CLKO1__FLEXIO1_FLEXIO_BIT26 0x00A8 0x02AC 0x0458 0x04 0x00 +#define IMX95_PAD_CCM_CLKO1__GPIO3_IO_BIT26 0x00A8 0x02AC 0x0000 0x05 0x00 + +#define IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x00AC 0x02B0 0x0000 0x05 0x00 +#define IMX95_PAD_CCM_CLKO2__CCMSRCGPCMIX_TOP_CLKO_2 0x00AC 0x02B0 0x0000 0x00 0x00 +#define IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x00AC 0x02B0 0x0000 0x01 0x00 +#define IMX95_PAD_CCM_CLKO2__FLEXIO1_FLEXIO_BIT27 0x00AC 0x02B0 0x045C 0x04 0x00 + +#define IMX95_PAD_CCM_CLKO3__CCMSRCGPCMIX_TOP_CLKO_3 0x00B0 0x02B4 0x0000 0x00 0x00 +#define IMX95_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x00B0 0x02B4 0x0438 0x01 0x00 +#define IMX95_PAD_CCM_CLKO3__CAN3_TX 0x00B0 0x02B4 0x0000 0x02 0x00 +#define IMX95_PAD_CCM_CLKO3__FLEXIO2_FLEXIO_BIT28 0x00B0 0x02B4 0x0000 0x04 0x00 +#define IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x00B0 0x02B4 0x0000 0x05 0x00 + +#define IMX95_PAD_CCM_CLKO4__CCMSRCGPCMIX_TOP_CLKO_4 0x00B4 0x02B8 0x0000 0x00 0x00 +#define IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x00B4 0x02B8 0x0000 0x01 0x00 +#define IMX95_PAD_CCM_CLKO4__CAN3_RX 0x00B4 0x02B8 0x0448 0x02 0x00 +#define IMX95_PAD_CCM_CLKO4__FLEXIO2_FLEXIO_BIT29 0x00B4 0x02B8 0x0000 0x04 0x00 +#define IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x00B4 0x02B8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x00B8 0x02BC 0x0424 0x00 0x00 +#define IMX95_PAD_ENET1_MDC__LPUART3_DCD_B 0x00B8 0x02BC 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_MDC__I3C2_SCL 0x00B8 0x02BC 0x04F8 0x02 0x00 +#define IMX95_PAD_ENET1_MDC__HSIOMIX_TOP_USB1_OTG_ID 0x00B8 0x02BC 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_MDC__FLEXIO2_FLEXIO_BIT0 0x00B8 0x02BC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0 0x00B8 0x02BC 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x00BC 0x02C0 0x0428 0x00 0x00 +#define IMX95_PAD_ENET1_MDIO__LPUART3_RIN_B 0x00BC 0x02C0 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x00BC 0x02C0 0x04FC 0x02 0x00 +#define IMX95_PAD_ENET1_MDIO__HSIOMIX_TOP_USB1_OTG_PWR 0x00BC 0x02C0 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_MDIO__FLEXIO2_FLEXIO_BIT1 0x00BC 0x02C0 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_MDIO__GPIO4_IO_BIT1 0x00BC 0x02C0 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x00C0 0x02C4 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TD3__CAN2_TX 0x00C0 0x02C4 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_TD3__HSIOMIX_TOP_USB2_OTG_ID 0x00C0 0x02C4 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_TD3__FLEXIO2_FLEXIO_BIT2 0x00C0 0x02C4 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TD3__GPIO4_IO_BIT2 0x00C0 0x02C4 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x00C4 0x02C8 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RMII_REF50_CLK 0x00C4 0x02C8 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_TD2__CAN2_RX 0x00C4 0x02C8 0x0444 0x02 0x01 +#define IMX95_PAD_ENET1_TD2__HSIOMIX_TOP_USB2_OTG_OC 0x00C4 0x02C8 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_TD2__FLEXIO2_FLEXIO_BIT3 0x00C4 0x02C8 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TD2__GPIO4_IO_BIT3 0x00C4 0x02C8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x00C8 0x02CC 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TD1__LPUART3_RTS_B 0x00C8 0x02CC 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_TD1__I3C2_PUR 0x00C8 0x02CC 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_TD1__HSIOMIX_TOP_USB1_OTG_OC 0x00C8 0x02CC 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_TD1__FLEXIO2_FLEXIO_BIT4 0x00C8 0x02CC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TD1__GPIO4_IO_BIT4 0x00C8 0x02CC 0x0000 0x05 0x00 +#define IMX95_PAD_ENET1_TD1__I3C2_PUR_B 0x00C8 0x02CC 0x0000 0x06 0x00 +#define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RMII_TXD1 0x00C8 0x02CC 0x0000 0x07 0x00 + +#define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x00CC 0x02D0 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TD0__LPUART3_TX 0x00CC 0x02D0 0x055C 0x01 0x00 +#define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RMII_TXD0 0x00CC 0x02D0 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_TD0__FLEXIO2_FLEXIO_BIT5 0x00CC 0x02D0 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TD0__GPIO4_IO_BIT5 0x00CC 0x02D0 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x00D0 0x02D4 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00D0 0x02D4 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RMII_TX_EN 0x00D0 0x02D4 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO_BIT6 0x00D0 0x02D4 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TX_CTL__GPIO4_IO_BIT6 0x00D0 0x02D4 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x00D4 0x02D8 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TXC__CCMSRCGPCMIX_TOP_ENET_CLK_ROOT 0x00D4 0x02D8 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_TXC__FLEXIO2_FLEXIO_BIT7 0x00D4 0x02D8 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TXC__GPIO4_IO_BIT7 0x00D4 0x02D8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x00D8 0x02DC 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00D8 0x02DC 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RMII_CRS_DV 0x00D8 0x02DC 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_RX_CTL__HSIOMIX_TOP_USB2_OTG_PWR 0x00D8 0x02DC 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO_BIT8 0x00D8 0x02DC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RX_CTL__GPIO4_IO_BIT8 0x00D8 0x02DC 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x00DC 0x02E0 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RMII_RX_ER 0x00DC 0x02E0 0x042C 0x01 0x00 +#define IMX95_PAD_ENET1_RXC__FLEXIO2_FLEXIO_BIT9 0x00DC 0x02E0 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RXC__GPIO4_IO_BIT9 0x00DC 0x02E0 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x00E0 0x02E4 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RD0__LPUART3_RX 0x00E0 0x02E4 0x0558 0x01 0x00 +#define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RMII_RXD0 0x00E0 0x02E4 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_RD0__FLEXIO2_FLEXIO_BIT10 0x00E0 0x02E4 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RD0__GPIO4_IO_BIT10 0x00E0 0x02E4 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x00E4 0x02E8 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RD1__LPUART3_CTS_B 0x00E4 0x02E8 0x0554 0x01 0x00 +#define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RMII_RXD1 0x00E4 0x02E8 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_RD1__LPTMR2_ALT1 0x00E4 0x02E8 0x0548 0x03 0x00 +#define IMX95_PAD_ENET1_RD1__FLEXIO2_FLEXIO_BIT11 0x00E4 0x02E8 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RD1__GPIO4_IO_BIT11 0x00E4 0x02E8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x00E8 0x02EC 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RMII_RX_ER 0x00E8 0x02EC 0x042C 0x02 0x01 +#define IMX95_PAD_ENET1_RD2__LPTMR2_ALT2 0x00E8 0x02EC 0x054C 0x03 0x00 +#define IMX95_PAD_ENET1_RD2__FLEXIO2_FLEXIO_BIT12 0x00E8 0x02EC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RD2__GPIO4_IO_BIT12 0x00E8 0x02EC 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x00EC 0x02F0 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RD3__LPTMR2_ALT3 0x00EC 0x02F0 0x0550 0x03 0x00 +#define IMX95_PAD_ENET1_RD3__FLEXIO2_FLEXIO_BIT13 0x00EC 0x02F0 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RD3__GPIO4_IO_BIT13 0x00EC 0x02F0 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x00F0 0x02F4 0x0424 0x00 0x01 +#define IMX95_PAD_ENET2_MDC__LPUART4_DCD_B 0x00F0 0x02F4 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x00F0 0x02F4 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_MDC__FLEXIO2_FLEXIO_BIT14 0x00F0 0x02F4 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14 0x00F0 0x02F4 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x00F4 0x02F8 0x0428 0x00 0x01 +#define IMX95_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00F4 0x02F8 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x00F4 0x02F8 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_MDIO__FLEXIO2_FLEXIO_BIT15 0x00F4 0x02F8 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15 0x00F4 0x02F8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x00F8 0x02FC 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TD3__FLEXIO2_FLEXIO_BIT16 0x00F8 0x02FC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TD3__GPIO4_IO_BIT16 0x00F8 0x02FC 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x00F8 0x02FC 0x0000 0x00 0x00 + +#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x00FC 0x0300 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RMII_REF50_CLK 0x00FC 0x0300 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x00FC 0x0300 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TD2__SAI4_TX_SYNC 0x00FC 0x0300 0x05A4 0x03 0x00 +#define IMX95_PAD_ENET2_TD2__FLEXIO2_FLEXIO_BIT17 0x00FC 0x0300 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TD2__GPIO4_IO_BIT17 0x00FC 0x0300 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x0100 0x0304 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TD1__LPUART4_RTS_B 0x0100 0x0304 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_BIT2 0x0100 0x0304 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TD1__SAI4_TX_BCLK 0x0100 0x0304 0x05A0 0x03 0x00 +#define IMX95_PAD_ENET2_TD1__FLEXIO2_FLEXIO_BIT18 0x0100 0x0304 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TD1__GPIO4_IO_BIT18 0x0100 0x0304 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RMII_TXD1 0x0100 0x0304 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x0104 0x0308 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TD0__LPUART4_TX 0x0104 0x0308 0x0568 0x01 0x00 +#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_BIT3 0x0104 0x0308 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TD0__SAI4_TX_DATA_BIT0 0x0104 0x0308 0x0000 0x03 0x00 +#define IMX95_PAD_ENET2_TD0__FLEXIO2_FLEXIO_BIT19 0x0104 0x0308 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TD0__GPIO4_IO_BIT19 0x0104 0x0308 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RMII_TXD0 0x0104 0x0308 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x0108 0x030C 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x0108 0x030C 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x0108 0x030C 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RMII_TX_EN 0x0108 0x030C 0x0000 0x03 0x00 +#define IMX95_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO_BIT20 0x0108 0x030C 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TX_CTL__GPIO4_IO_BIT20 0x0108 0x030C 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x010C 0x0310 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TXC__CCMSRCGPCMIX_TOP_ENET_CLK_ROOT 0x010C 0x0310 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x010C 0x0310 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TXC__FLEXIO2_FLEXIO_BIT21 0x010C 0x0310 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TXC__GPIO4_IO_BIT21 0x010C 0x0310 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x0110 0x0314 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x0110 0x0314 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x0110 0x0314 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO_BIT22 0x0110 0x0314 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RX_CTL__GPIO4_IO_BIT22 0x0110 0x0314 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RMII_CRS_DV 0x0110 0x0314 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x0114 0x0318 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0114 0x0318 0x0430 0x01 0x00 +#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x0114 0x0318 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RXC__SAI4_RX_SYNC 0x0114 0x0318 0x059C 0x03 0x00 +#define IMX95_PAD_ENET2_RXC__FLEXIO2_FLEXIO_BIT23 0x0114 0x0318 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RXC__GPIO4_IO_BIT23 0x0114 0x0318 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x0118 0x031C 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RD0__LPUART4_RX 0x0118 0x031C 0x0564 0x01 0x00 +#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x0118 0x031C 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RD0__SAI4_RX_BCLK 0x0118 0x031C 0x0594 0x03 0x00 +#define IMX95_PAD_ENET2_RD0__FLEXIO2_FLEXIO_BIT24 0x0118 0x031C 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RD0__GPIO4_IO_BIT24 0x0118 0x031C 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RMII_RXD0 0x0118 0x031C 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x011C 0x0320 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RD1__SPDIF_IN 0x011C 0x0320 0x0454 0x01 0x00 +#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x011C 0x0320 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RD1__SAI4_RX_DATA_BIT0 0x011C 0x0320 0x0598 0x03 0x00 +#define IMX95_PAD_ENET2_RD1__FLEXIO2_FLEXIO_BIT25 0x011C 0x0320 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RD1__GPIO4_IO_BIT25 0x011C 0x0320 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RMII_RXD1 0x011C 0x0320 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x0120 0x0324 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RD2__LPUART4_CTS_B 0x0120 0x0324 0x0560 0x01 0x00 +#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x0120 0x0324 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_MQS2_RIGHT 0x0120 0x0324 0x0000 0x03 0x00 +#define IMX95_PAD_ENET2_RD2__FLEXIO2_FLEXIO_BIT26 0x0120 0x0324 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RD2__GPIO4_IO_BIT26 0x0120 0x0324 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0120 0x0324 0x0430 0x06 0x01 + +#define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x0124 0x0328 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RD3__SPDIF_OUT 0x0124 0x0328 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_RD3__SPDIF_IN 0x0124 0x0328 0x0454 0x02 0x01 +#define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_MQS2_LEFT 0x0124 0x0328 0x0000 0x03 0x00 +#define IMX95_PAD_ENET2_RD3__FLEXIO2_FLEXIO_BIT27 0x0124 0x0328 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27 0x0124 0x0328 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_CLK__FLEXIO1_FLEXIO_BIT8 0x0128 0x032C 0x0488 0x04 0x01 +#define IMX95_PAD_SD1_CLK__GPIO3_IO_BIT8 0x0128 0x032C 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_CLK__USDHC1_CLK 0x0128 0x032C 0x0000 0x00 0x00 + +#define IMX95_PAD_SD1_CMD__USDHC1_CMD 0x012C 0x0330 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_CMD__FLEXIO1_FLEXIO_BIT9 0x012C 0x0330 0x048C 0x04 0x01 +#define IMX95_PAD_SD1_CMD__GPIO3_IO_BIT9 0x012C 0x0330 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x0130 0x0334 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA0__FLEXIO1_FLEXIO_BIT10 0x0130 0x0334 0x0490 0x04 0x01 +#define IMX95_PAD_SD1_DATA0__GPIO3_IO_BIT10 0x0130 0x0334 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x0134 0x0338 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA1__FLEXIO1_FLEXIO_BIT11 0x0134 0x0338 0x0494 0x04 0x01 +#define IMX95_PAD_SD1_DATA1__GPIO3_IO_BIT11 0x0134 0x0338 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x0138 0x033C 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA2__FLEXIO1_FLEXIO_BIT12 0x0138 0x033C 0x0498 0x04 0x01 +#define IMX95_PAD_SD1_DATA2__GPIO3_IO_BIT12 0x0138 0x033C 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA2__CCMSRCGPCMIX_TOP_PMIC_READY 0x0138 0x033C 0x0000 0x06 0x00 + +#define IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x013C 0x0340 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x013C 0x0340 0x0000 0x01 0x00 +#define IMX95_PAD_SD1_DATA3__FLEXIO1_FLEXIO_BIT13 0x013C 0x0340 0x049C 0x04 0x01 +#define IMX95_PAD_SD1_DATA3__GPIO3_IO_BIT13 0x013C 0x0340 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x0140 0x0344 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA4__FLEXSPI1_A_DATA_BIT4 0x0140 0x0344 0x04E4 0x01 0x00 +#define IMX95_PAD_SD1_DATA4__FLEXIO1_FLEXIO_BIT14 0x0140 0x0344 0x04A0 0x04 0x01 +#define IMX95_PAD_SD1_DATA4__GPIO3_IO_BIT14 0x0140 0x0344 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA4__XSPI_DATA_BIT4 0x0140 0x0344 0x05FC 0x06 0x00 + +#define IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x0144 0x0348 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA5__FLEXSPI1_A_DATA_BIT5 0x0144 0x0348 0x04E8 0x01 0x00 +#define IMX95_PAD_SD1_DATA5__USDHC1_RESET_B 0x0144 0x0348 0x0000 0x02 0x00 +#define IMX95_PAD_SD1_DATA5__FLEXIO1_FLEXIO_BIT15 0x0144 0x0348 0x04A4 0x04 0x01 +#define IMX95_PAD_SD1_DATA5__GPIO3_IO_BIT15 0x0144 0x0348 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA5__XSPI_DATA_BIT5 0x0144 0x0348 0x0600 0x06 0x00 + +#define IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x0148 0x034C 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA6__FLEXSPI1_A_DATA_BIT6 0x0148 0x034C 0x04EC 0x01 0x00 +#define IMX95_PAD_SD1_DATA6__USDHC1_CD_B 0x0148 0x034C 0x0000 0x02 0x00 +#define IMX95_PAD_SD1_DATA6__FLEXIO1_FLEXIO_BIT16 0x0148 0x034C 0x04A8 0x04 0x01 +#define IMX95_PAD_SD1_DATA6__GPIO3_IO_BIT16 0x0148 0x034C 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA6__XSPI_DATA_BIT6 0x0148 0x034C 0x0604 0x06 0x00 + +#define IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x014C 0x0350 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA7__FLEXSPI1_A_DATA_BIT7 0x014C 0x0350 0x04F0 0x01 0x00 +#define IMX95_PAD_SD1_DATA7__USDHC1_WP 0x014C 0x0350 0x0000 0x02 0x00 +#define IMX95_PAD_SD1_DATA7__FLEXIO1_FLEXIO_BIT17 0x014C 0x0350 0x04AC 0x04 0x01 +#define IMX95_PAD_SD1_DATA7__GPIO3_IO_BIT17 0x014C 0x0350 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA7__XSPI_DATA_BIT7 0x014C 0x0350 0x0608 0x06 0x00 + +#define IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x0150 0x0354 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0150 0x0354 0x04D0 0x01 0x00 +#define IMX95_PAD_SD1_STROBE__FLEXIO1_FLEXIO_BIT18 0x0150 0x0354 0x04B0 0x04 0x01 +#define IMX95_PAD_SD1_STROBE__GPIO3_IO_BIT18 0x0150 0x0354 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_STROBE__XSPI_DQS 0x0150 0x0354 0x05E4 0x06 0x00 + +#define IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0154 0x0358 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_VSELECT__USDHC2_WP 0x0154 0x0358 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0154 0x0358 0x0550 0x02 0x01 +#define IMX95_PAD_SD2_VSELECT__FLEXIO1_FLEXIO_BIT19 0x0154 0x0358 0x04B4 0x04 0x01 +#define IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x0154 0x0358 0x0000 0x05 0x00 +#define IMX95_PAD_SD2_VSELECT__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0154 0x0358 0x0420 0x06 0x01 + +#define IMX95_PAD_SD3_CLK__USDHC3_CLK 0x0158 0x035C 0x05C8 0x00 0x01 +#define IMX95_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0158 0x035C 0x04F4 0x01 0x00 +#define IMX95_PAD_SD3_CLK__SAI5_TX_DATA_BIT1 0x0158 0x035C 0x0000 0x02 0x00 +#define IMX95_PAD_SD3_CLK__SAI5_RX_DATA_BIT0 0x0158 0x035C 0x05AC 0x03 0x00 +#define IMX95_PAD_SD3_CLK__FLEXIO1_FLEXIO_BIT20 0x0158 0x035C 0x04B8 0x04 0x01 +#define IMX95_PAD_SD3_CLK__GPIO3_IO_BIT20 0x0158 0x035C 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_CLK__XSPI_CLK 0x0158 0x035C 0x05E8 0x06 0x00 + +#define IMX95_PAD_SD3_CMD__USDHC3_CMD 0x015C 0x0360 0x05CC 0x00 0x01 +#define IMX95_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x015C 0x0360 0x0000 0x01 0x00 +#define IMX95_PAD_SD3_CMD__SAI5_TX_DATA_BIT2 0x015C 0x0360 0x0000 0x02 0x00 +#define IMX95_PAD_SD3_CMD__SAI5_RX_SYNC 0x015C 0x0360 0x05BC 0x03 0x00 +#define IMX95_PAD_SD3_CMD__FLEXIO1_FLEXIO_BIT21 0x015C 0x0360 0x04BC 0x04 0x01 +#define IMX95_PAD_SD3_CMD__GPIO3_IO_BIT21 0x015C 0x0360 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_CMD__XSPI_CS 0x015C 0x0360 0x05E0 0x06 0x00 + +#define IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x0160 0x0364 0x05D0 0x00 0x01 +#define IMX95_PAD_SD3_DATA0__FLEXSPI1_A_DATA_BIT0 0x0160 0x0364 0x04D4 0x01 0x00 +#define IMX95_PAD_SD3_DATA0__SAI5_TX_DATA_BIT3 0x0160 0x0364 0x0000 0x02 0x00 +#define IMX95_PAD_SD3_DATA0__SAI5_RX_BCLK 0x0160 0x0364 0x05A8 0x03 0x00 +#define IMX95_PAD_SD3_DATA0__FLEXIO1_FLEXIO_BIT22 0x0160 0x0364 0x04C0 0x04 0x01 +#define IMX95_PAD_SD3_DATA0__GPIO3_IO_BIT22 0x0160 0x0364 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_DATA0__XSPI_DATA_BIT0 0x0160 0x0364 0x05EC 0x06 0x00 + +#define IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x0164 0x0368 0x05D4 0x00 0x01 +#define IMX95_PAD_SD3_DATA1__FLEXSPI1_A_DATA_BIT1 0x0164 0x0368 0x04D8 0x01 0x00 +#define IMX95_PAD_SD3_DATA1__SAI5_RX_DATA_BIT1 0x0164 0x0368 0x05B0 0x02 0x00 +#define IMX95_PAD_SD3_DATA1__SAI5_TX_DATA_BIT0 0x0164 0x0368 0x0000 0x03 0x00 +#define IMX95_PAD_SD3_DATA1__FLEXIO1_FLEXIO_BIT23 0x0164 0x0368 0x04C4 0x04 0x01 +#define IMX95_PAD_SD3_DATA1__GPIO3_IO_BIT23 0x0164 0x0368 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_DATA1__XSPI_DATA_BIT1 0x0164 0x0368 0x05F0 0x06 0x00 + +#define IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x0168 0x036C 0x05D8 0x00 0x01 +#define IMX95_PAD_SD3_DATA2__FLEXSPI1_A_DATA_BIT2 0x0168 0x036C 0x04DC 0x01 0x00 +#define IMX95_PAD_SD3_DATA2__SAI5_RX_DATA_BIT2 0x0168 0x036C 0x05B4 0x02 0x00 +#define IMX95_PAD_SD3_DATA2__SAI5_TX_SYNC 0x0168 0x036C 0x05C4 0x03 0x00 +#define IMX95_PAD_SD3_DATA2__FLEXIO1_FLEXIO_BIT24 0x0168 0x036C 0x04C8 0x04 0x01 +#define IMX95_PAD_SD3_DATA2__GPIO3_IO_BIT24 0x0168 0x036C 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_DATA2__XSPI_DATA_BIT2 0x0168 0x036C 0x05F4 0x06 0x00 + +#define IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x016C 0x0370 0x05DC 0x00 0x01 +#define IMX95_PAD_SD3_DATA3__FLEXSPI1_A_DATA_BIT3 0x016C 0x0370 0x04E0 0x01 0x00 +#define IMX95_PAD_SD3_DATA3__SAI5_RX_DATA_BIT3 0x016C 0x0370 0x05B8 0x02 0x00 +#define IMX95_PAD_SD3_DATA3__SAI5_TX_BCLK 0x016C 0x0370 0x05C0 0x03 0x00 +#define IMX95_PAD_SD3_DATA3__FLEXIO1_FLEXIO_BIT25 0x016C 0x0370 0x04CC 0x04 0x01 +#define IMX95_PAD_SD3_DATA3__GPIO3_IO_BIT25 0x016C 0x0370 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_DATA3__XSPI_DATA_BIT3 0x016C 0x0370 0x05F8 0x06 0x00 + +#define IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x0170 0x0374 0x04D4 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_BIT4 0x0170 0x0374 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA0__SAI4_TX_BCLK 0x0170 0x0374 0x05A0 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA0__SAI4_RX_DATA_BIT1 0x0170 0x0374 0x0000 0x03 0x00 +#define IMX95_PAD_XSPI1_DATA0__XSPI_DATA_BIT0 0x0170 0x0374 0x05EC 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x0170 0x0374 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x0174 0x0378 0x04D8 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_BIT5 0x0174 0x0378 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA1__SAI4_TX_SYNC 0x0174 0x0378 0x05A4 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA1__SAI4_TX_DATA_BIT1 0x0174 0x0378 0x0000 0x03 0x00 +#define IMX95_PAD_XSPI1_DATA1__XSPI_DATA_BIT1 0x0174 0x0378 0x05F0 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x0174 0x0378 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x0178 0x037C 0x04DC 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_BIT6 0x0178 0x037C 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA2__SAI4_TX_DATA_BIT0 0x0178 0x037C 0x0000 0x02 0x00 +#define IMX95_PAD_XSPI1_DATA2__XSPI_DATA_BIT2 0x0178 0x037C 0x05F4 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x0178 0x037C 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x017C 0x0380 0x04E0 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_BIT7 0x017C 0x0380 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA3__SAI4_RX_DATA_BIT0 0x017C 0x0380 0x0598 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA3__XSPI_DATA_BIT3 0x017C 0x0380 0x05F8 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x017C 0x0380 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x0180 0x0384 0x04E4 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x0180 0x0384 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA4__SAI5_RX_DATA_BIT1 0x0180 0x0384 0x05B0 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA4__XSPI_DATA_BIT4 0x0180 0x0384 0x05FC 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x0180 0x0384 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x0184 0x0388 0x04E8 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x0184 0x0388 0x05C4 0x01 0x01 +#define IMX95_PAD_XSPI1_DATA5__SAI5_RX_DATA_BIT2 0x0184 0x0388 0x05B4 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA5__NETCMIX_TOP_SAI2_RX_DATA_BIT6 0x0184 0x0388 0x043C 0x03 0x00 +#define IMX95_PAD_XSPI1_DATA5__XSPI_DATA_BIT5 0x0184 0x0388 0x0600 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5 0x0184 0x0388 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x0188 0x038C 0x04EC 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x0188 0x038C 0x05C0 0x01 0x01 +#define IMX95_PAD_XSPI1_DATA6__SAI5_RX_DATA_BIT3 0x0188 0x038C 0x05B8 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA6__NETCMIX_TOP_SAI2_RX_DATA_BIT7 0x0188 0x038C 0x0440 0x03 0x00 +#define IMX95_PAD_XSPI1_DATA6__XSPI_DATA_BIT6 0x0188 0x038C 0x0604 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x0188 0x038C 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x018C 0x0390 0x04F0 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x018C 0x0390 0x05AC 0x01 0x01 +#define IMX95_PAD_XSPI1_DATA7__SAI5_TX_DATA_BIT1 0x018C 0x0390 0x0000 0x02 0x00 +#define IMX95_PAD_XSPI1_DATA7__XSPI_DATA_BIT7 0x018C 0x0390 0x0608 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7 0x018C 0x0390 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x0190 0x0394 0x04D0 0x00 0x01 +#define IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC 0x0190 0x0394 0x05BC 0x01 0x01 +#define IMX95_PAD_XSPI1_DQS__SAI5_TX_DATA_BIT2 0x0190 0x0394 0x0000 0x02 0x00 +#define IMX95_PAD_XSPI1_DQS__NETCMIX_TOP_SAI2_RX_DATA_BIT6 0x0190 0x0394 0x043C 0x03 0x01 +#define IMX95_PAD_XSPI1_DQS__XSPI_DQS 0x0190 0x0394 0x05E4 0x04 0x01 +#define IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x0190 0x0394 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x0194 0x0398 0x04F4 0x00 0x01 +#define IMX95_PAD_XSPI1_SCLK__NETCMIX_TOP_SAI2_RX_DATA_BIT4 0x0194 0x0398 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_SCLK__SAI4_RX_SYNC 0x0194 0x0398 0x059C 0x02 0x01 +#define IMX95_PAD_XSPI1_SCLK__EARC_DC_HPD_IN 0x0194 0x0398 0x0000 0x03 0x00 +#define IMX95_PAD_XSPI1_SCLK__XSPI_CLK 0x0194 0x0398 0x05E8 0x04 0x01 +#define IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x0194 0x0398 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x0198 0x039C 0x0000 0x00 0x00 +#define IMX95_PAD_XSPI1_SS0_B__NETCMIX_TOP_SAI2_RX_DATA_BIT5 0x0198 0x039C 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_SS0_B__SAI4_RX_BCLK 0x0198 0x039C 0x0594 0x02 0x01 +#define IMX95_PAD_XSPI1_SS0_B__EARC_CEC_OUT 0x0198 0x039C 0x0000 0x03 0x00 +#define IMX95_PAD_XSPI1_SS0_B__XSPI_CS 0x0198 0x039C 0x05E0 0x04 0x01 +#define IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x0198 0x039C 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B 0x019C 0x03A0 0x0000 0x00 0x00 +#define IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK 0x019C 0x03A0 0x05A8 0x01 0x01 +#define IMX95_PAD_XSPI1_SS1_B__SAI5_TX_DATA_BIT3 0x019C 0x03A0 0x0000 0x02 0x00 +#define IMX95_PAD_XSPI1_SS1_B__NETCMIX_TOP_SAI2_RX_DATA_BIT7 0x019C 0x03A0 0x0440 0x03 0x01 +#define IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x019C 0x03A0 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_CD_B__USDHC2_CD_B 0x01A0 0x03A4 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_CD_B__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x01A0 0x03A4 0x0434 0x01 0x01 +#define IMX95_PAD_SD2_CD_B__I3C2_SCL 0x01A0 0x03A4 0x04F8 0x02 0x01 +#define IMX95_PAD_SD2_CD_B__FLEXIO1_FLEXIO_BIT0 0x01A0 0x03A4 0x0468 0x04 0x01 +#define IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x01A0 0x03A4 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_CLK__USDHC2_CLK 0x01A4 0x03A8 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_CLK__NETCMIX_TOP_NETC_TMR_1588_PP1 0x01A4 0x03A8 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_CLK__I3C2_SDA 0x01A4 0x03A8 0x04FC 0x02 0x01 +#define IMX95_PAD_SD2_CLK__FLEXIO1_FLEXIO_BIT1 0x01A4 0x03A8 0x046C 0x04 0x01 +#define IMX95_PAD_SD2_CLK__GPIO3_IO_BIT1 0x01A4 0x03A8 0x0000 0x05 0x00 +#define IMX95_PAD_SD2_CLK__CCMSRCGPCMIX_TOP_OBSERVE_0 0x01A4 0x03A8 0x0000 0x06 0x00 + +#define IMX95_PAD_SD2_CMD__USDHC2_CMD 0x01A8 0x03AC 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_CMD__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x01A8 0x03AC 0x0438 0x01 0x01 +#define IMX95_PAD_SD2_CMD__I3C2_PUR 0x01A8 0x03AC 0x0000 0x02 0x00 +#define IMX95_PAD_SD2_CMD__I3C2_PUR_B 0x01A8 0x03AC 0x0000 0x03 0x00 +#define IMX95_PAD_SD2_CMD__FLEXIO1_FLEXIO_BIT2 0x01A8 0x03AC 0x0470 0x04 0x01 +#define IMX95_PAD_SD2_CMD__GPIO3_IO_BIT2 0x01A8 0x03AC 0x0000 0x05 0x00 +#define IMX95_PAD_SD2_CMD__CCMSRCGPCMIX_TOP_OBSERVE_1 0x01A8 0x03AC 0x0000 0x06 0x00 + +#define IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x01AC 0x03B0 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_DATA0__NETCMIX_TOP_NETC_TMR_1588_PP2 0x01AC 0x03B0 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_DATA0__CAN2_TX 0x01AC 0x03B0 0x0000 0x02 0x00 +#define IMX95_PAD_SD2_DATA0__FLEXIO1_FLEXIO_BIT3 0x01AC 0x03B0 0x0474 0x04 0x01 +#define IMX95_PAD_SD2_DATA0__GPIO3_IO_BIT3 0x01AC 0x03B0 0x0000 0x05 0x00 +#define IMX95_PAD_SD2_DATA0__CCMSRCGPCMIX_TOP_OBSERVE_2 0x01AC 0x03B0 0x0000 0x06 0x00 + +#define IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x01B0 0x03B4 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_DATA1__NETCMIX_TOP_NETC_TMR_1588_CLK 0x01B0 0x03B4 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_DATA1__CAN2_RX 0x01B0 0x03B4 0x0444 0x02 0x03 +#define IMX95_PAD_SD2_DATA1__FLEXIO1_FLEXIO_BIT4 0x01B0 0x03B4 0x0478 0x04 0x01 +#define IMX95_PAD_SD2_DATA1__GPIO3_IO_BIT4 0x01B0 0x03B4 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x01B4 0x03B8 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_NETC_TMR_1588_PP3 0x01B4 0x03B8 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_MQS2_RIGHT 0x01B4 0x03B8 0x0000 0x02 0x00 +#define IMX95_PAD_SD2_DATA2__FLEXIO1_FLEXIO_BIT5 0x01B4 0x03B8 0x047C 0x04 0x01 +#define IMX95_PAD_SD2_DATA2__GPIO3_IO_BIT5 0x01B4 0x03B8 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x01B8 0x03BC 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_DATA3__LPTMR2_ALT1 0x01B8 0x03BC 0x0548 0x01 0x01 +#define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_MQS2_LEFT 0x01B8 0x03BC 0x0000 0x02 0x00 +#define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x01B8 0x03BC 0x0000 0x03 0x00 +#define IMX95_PAD_SD2_DATA3__FLEXIO1_FLEXIO_BIT6 0x01B8 0x03BC 0x0480 0x04 0x01 +#define IMX95_PAD_SD2_DATA3__GPIO3_IO_BIT6 0x01B8 0x03BC 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_RESET_B__USDHC2_RESET_B 0x01BC 0x03C0 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_RESET_B__LPTMR2_ALT2 0x01BC 0x03C0 0x054C 0x01 0x01 +#define IMX95_PAD_SD2_RESET_B__NETCMIX_TOP_NETC_TMR_1588_GCLK 0x01BC 0x03C0 0x0000 0x03 0x00 +#define IMX95_PAD_SD2_RESET_B__FLEXIO1_FLEXIO_BIT7 0x01BC 0x03C0 0x0484 0x04 0x01 +#define IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x01BC 0x03C0 0x0000 0x05 0x00 + +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x01C0 0x03C4 0x0000 0x00 0x00 +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_I3C1_SCL 0x01C0 0x03C4 0x0000 0x01 0x00 +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPUART1_DCD_B 0x01C0 0x03C4 0x0000 0x02 0x00 +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_TPM2_CH0 0x01C0 0x03C4 0x0000 0x03 0x00 +#define IMX95_PAD_I2C1_SCL__VPUMIX_TOP_UART_RX 0x01C0 0x03C4 0x0000 0x04 0x00 +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_GPIO1_IO_BIT0 0x01C0 0x03C4 0x0000 0x05 0x00 + +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x01C4 0x03C8 0x0000 0x00 0x00 +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_I3C1_SDA 0x01C4 0x03C8 0x0000 0x01 0x00 +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPUART1_RIN_B 0x01C4 0x03C8 0x0000 0x02 0x00 +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_TPM2_CH1 0x01C4 0x03C8 0x0000 0x03 0x00 +#define IMX95_PAD_I2C1_SDA__VPUMIX_TOP_UART_TX 0x01C4 0x03C8 0x0000 0x04 0x00 +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_GPIO1_IO_BIT1 0x01C4 0x03C8 0x0000 0x05 0x00 + +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x01C8 0x03CC 0x0000 0x00 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR 0x01C8 0x03CC 0x0000 0x01 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPUART2_DCD_B 0x01C8 0x03CC 0x0000 0x02 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_TPM2_CH2 0x01C8 0x03CC 0x0000 0x03 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_SAI1_RX_SYNC 0x01C8 0x03CC 0x0000 0x04 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x01C8 0x03CC 0x0000 0x05 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR_B 0x01C8 0x03CC 0x0000 0x06 0x00 + +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x01CC 0x03D0 0x0000 0x00 0x00 +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPUART2_RIN_B 0x01CC 0x03D0 0x0000 0x02 0x00 +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_TPM2_CH3 0x01CC 0x03D0 0x0000 0x03 0x00 +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_SAI1_RX_BCLK 0x01CC 0x03D0 0x0000 0x04 0x00 +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x01CC 0x03D0 0x0000 0x05 0x00 + +#define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x01D0 0x03D4 0x0000 0x00 0x00 +#define IMX95_PAD_UART1_RXD__S400_UART_RX 0x01D0 0x03D4 0x0000 0x01 0x00 +#define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPSPI2_SIN 0x01D0 0x03D4 0x0000 0x02 0x00 +#define IMX95_PAD_UART1_RXD__AONMIX_TOP_TPM1_CH0 0x01D0 0x03D4 0x0000 0x03 0x00 +#define IMX95_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_BIT4 0x01D0 0x03D4 0x0000 0x05 0x00 + +#define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x01D4 0x03D8 0x0000 0x00 0x00 +#define IMX95_PAD_UART1_TXD__S400_UART_TX 0x01D4 0x03D8 0x0000 0x01 0x00 +#define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPSPI2_PCS0 0x01D4 0x03D8 0x0000 0x02 0x00 +#define IMX95_PAD_UART1_TXD__AONMIX_TOP_TPM1_CH1 0x01D4 0x03D8 0x0000 0x03 0x00 +#define IMX95_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_BIT5 0x01D4 0x03D8 0x0000 0x05 0x00 + +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x01D8 0x03DC 0x0000 0x00 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B 0x01D8 0x03DC 0x0000 0x01 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPSPI2_SOUT 0x01D8 0x03DC 0x0000 0x02 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_TPM1_CH2 0x01D8 0x03DC 0x0000 0x03 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_SAI1_MCLK 0x01D8 0x03DC 0x041C 0x04 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_GPIO1_IO_BIT6 0x01D8 0x03DC 0x0000 0x05 0x00 + +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x01DC 0x03E0 0x0000 0x00 0x00 +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B 0x01DC 0x03E0 0x0000 0x01 0x00 +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPSPI2_SCK 0x01DC 0x03E0 0x0000 0x02 0x00 +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_TPM1_CH3 0x01DC 0x03E0 0x0000 0x03 0x00 +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_BIT7 0x01DC 0x03E0 0x0000 0x05 0x00 + +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x01E0 0x03E4 0x0000 0x00 0x00 +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_MQS1_LEFT 0x01E0 0x03E4 0x0000 0x01 0x00 +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_LPTMR1_ALT1 0x01E0 0x03E4 0x0000 0x04 0x00 +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_BIT8 0x01E0 0x03E4 0x0000 0x05 0x00 +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x01E0 0x03E4 0x0000 0x06 0x00 + +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x01E4 0x03E8 0x040C 0x00 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_MQS1_RIGHT 0x01E4 0x03E8 0x0000 0x01 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPSPI1_PCS1 0x01E4 0x03E8 0x0000 0x02 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_TPM1_EXTCLK 0x01E4 0x03E8 0x0000 0x03 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPTMR1_ALT2 0x01E4 0x03E8 0x0000 0x04 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_BIT9 0x01E4 0x03E8 0x0000 0x05 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x01E4 0x03E8 0x0408 0x06 0x00 + +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x01E8 0x03EC 0x0410 0x00 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x01E8 0x03EC 0x0000 0x01 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPSPI2_PCS1 0x01E8 0x03EC 0x0000 0x02 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_TPM2_EXTCLK 0x01E8 0x03EC 0x0000 0x03 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPTMR1_ALT3 0x01E8 0x03EC 0x0000 0x04 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x01E8 0x03EC 0x0000 0x05 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_TOP_EXT_CLK1 0x01E8 0x03EC 0x0420 0x06 0x00 + +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x01EC 0x03F0 0x0000 0x00 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_DATA_BIT1 0x01EC 0x03F0 0x0000 0x01 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPSPI1_PCS0 0x01EC 0x03F0 0x0000 0x02 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPUART2_DTR_B 0x01EC 0x03F0 0x0000 0x03 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x01EC 0x03F0 0x0000 0x04 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x01EC 0x03F0 0x0000 0x05 0x00 + +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x01F0 0x03F4 0x0000 0x00 0x00 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x01F0 0x03F4 0x0000 0x01 0x00 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPSPI1_SIN 0x01F0 0x03F4 0x0000 0x02 0x00 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART1_DSR_B 0x01F0 0x03F4 0x0000 0x03 0x00 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x01F0 0x03F4 0x0408 0x04 0x01 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x01F0 0x03F4 0x0000 0x05 0x00 + +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x01F4 0x03F8 0x0000 0x00 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x01F4 0x03F8 0x0000 0x01 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1_SCK 0x01F4 0x03F8 0x0000 0x02 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART1_DTR_B 0x01F4 0x03F8 0x0000 0x03 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x01F4 0x03F8 0x0000 0x04 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x01F4 0x03F8 0x0000 0x05 0x00 + +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x01F8 0x03FC 0x0000 0x00 0x00 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_MCLK 0x01F8 0x03FC 0x041C 0x01 0x01 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1_SOUT 0x01F8 0x03FC 0x0000 0x02 0x00 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPUART2_DSR_B 0x01F8 0x03FC 0x0000 0x03 0x00 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x01F8 0x03FC 0x0000 0x04 0x00 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x01F8 0x03FC 0x0000 0x05 0x00 + +#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_WDOG_ANY 0x01FC 0x0400 0x0000 0x00 0x00 +#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_FCCU_EOUT1 0x01FC 0x0400 0x0000 0x01 0x00 +#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_GPIO1_IO_BIT15 0x01FC 0x0400 0x0000 0x05 0x00 +#endif /* __DTS_IMX95_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx95-power.h b/arch/arm64/boot/dts/freescale/imx95-power.h new file mode 100644 index 000000000000..0b7f0bc30e19 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-power.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2024 NXP + */ + +#ifndef __IMX95_POWER_H__ +#define __IMX95_POWER_H__ + +#define IMX95_PD_ANA 0 +#define IMX95_PD_AON 1 +#define IMX95_PD_BBSM 2 +#define IMX95_PD_CAMERA 3 +#define IMX95_PD_CCMSRCGPC 4 +#define IMX95_PD_A55C0 5 +#define IMX95_PD_A55C1 6 +#define IMX95_PD_A55C2 7 +#define IMX95_PD_A55C3 8 +#define IMX95_PD_A55C4 9 +#define IMX95_PD_A55C5 10 +#define IMX95_PD_A55P 11 +#define IMX95_PD_DDR 12 +#define IMX95_PD_DISPLAY 13 +#define IMX95_PD_GPU 14 +#define IMX95_PD_HSIO_TOP 15 +#define IMX95_PD_HSIO_WAON 16 +#define IMX95_PD_M7 17 +#define IMX95_PD_NETC 18 +#define IMX95_PD_NOC 19 +#define IMX95_PD_NPU 20 +#define IMX95_PD_VPU 21 +#define IMX95_PD_WAKEUP 22 + +#define IMX95_PERF_ELE 0 +#define IMX95_PERF_M33 1 +#define IMX95_PERF_WAKEUP 2 +#define IMX95_PERF_M7 3 +#define IMX95_PERF_DRAM 4 +#define IMX95_PERF_HSIO 5 +#define IMX95_PERF_NPU 6 +#define IMX95_PERF_NOC 7 +#define IMX95_PERF_A55 8 +#define IMX95_PERF_GPU 9 +#define IMX95_PERF_VPU 10 +#define IMX95_PERF_CAM 11 +#define IMX95_PERF_DISP 12 + +#endif diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi new file mode 100644 index 000000000000..09b7c94c7ccf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -0,0 +1,1063 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include + +#include "imx95-clock.h" +#include "imx95-pinfunc.h" +#include "imx95-power.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <10000>; + exit-latency-us = <7000>; + min-residency-us = <27000>; + wakeup-latency-us = <15000>; + status = "disabled"; + }; + }; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + power-domains = <&scmi_devpd IMX95_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + power-domains = <&scmi_devpd IMX95_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + }; + + A55_2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + power-domains = <&scmi_devpd IMX95_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l2>; + }; + + A55_3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + power-domains = <&scmi_devpd IMX95_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l3>; + }; + + A55_4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + power-domains = <&scmi_devpd IMX95_PERF_A55>; + power-domain-names = "perf"; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l4>; + }; + + A55_5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + power-domains = <&scmi_devpd IMX95_PERF_A55>; + power-domain-names = "perf"; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l5>; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l4: l2-cache-l4 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l5: l2-cache-l5 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <3>; + cache-unified; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&A55_0>; + }; + + core1 { + cpu = <&A55_1>; + }; + + core2 { + cpu = <&A55_2>; + }; + + core3 { + cpu = <&A55_3>; + }; + + core4 { + cpu = <&A55_4>; + }; + + core5 { + cpu = <&A55_5>; + }; + }; + }; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + sai1_mclk: sai-mclk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai1_mclk"; + }; + + sai2_mclk: sai-mclk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai2_mclk"; + }; + + sai3_mclk: sai-mclk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai3_mclk"; + }; + + sai4_mclk: sai-mclk4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai4_mclk"; + }; + + sai5_mclk: sai-mclk5 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai5_mclk"; + }; + + osc_24m: osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + sram1: sram@20480000 { + compatible = "mmio-sram"; + reg = <0x0 0x204c0000 0x0 0x18000>; + ranges = <0x0 0x0 0x204c0000 0x18000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + firmware { + scmi { + compatible = "arm,scmi"; + mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>; + shmem = <&scmi_buf0>, <&scmi_buf1>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_perf: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + + scmi_iomuxc: protocol@19 { + reg = <0x19>; + }; + + }; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + thermal-zones { + a55-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&scmi_sensor 1>; + + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48060000 0 0xc0000>; + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + dma-noncoherent; + ranges; + + its: msi-controller@48040000 { + compatible = "arm,gic-v3-its"; + reg = <0 0x48040000 0 0x20000>; + msi-controller; + #msi-cells = <1>; + dma-noncoherent; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x42000000 0x0 0x800000>; + ranges = <0x42000000 0x0 0x42000000 0x8000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + + mu7: mailbox@42430000 { + compatible = "fsl,imx95-mu"; + reg = <0x42430000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + + wdog3: watchdog@42490000 { + compatible = "fsl,imx93-wdt"; + reg = <0x42490000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; + timeout-sec = <40>; + status = "disabled"; + }; + + tpm3: pwm@424e0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424e0000 0x1000>; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm4: pwm@424f0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424f0000 0x1000>; + clocks = <&scmi_clk IMX95_CLK_TPM4>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm5: pwm@42500000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42500000 0x1000>; + clocks = <&scmi_clk IMX95_CLK_TPM5>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm6: pwm@42510000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42510000 0x1000>; + clocks = <&scmi_clk IMX95_CLK_TPM6>; + #pwm-cells = <3>; + status = "disabled"; + }; + + lpi2c3: i2c@42530000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42530000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C3>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c4: i2c@42540000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42540000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C4>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi3: spi@42550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42550000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI3>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi4: spi@42560000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42560000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI4>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpuart3: serial@42570000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42570000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART3>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@42580000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42580000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART4>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@42590000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42590000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART5>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart6: serial@425a0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x425a0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART6>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart7: serial@42690000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42690000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART7>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart8: serial@426a0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x426a0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART8>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpi2c5: i2c@426b0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426b0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C5>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c6: i2c@426c0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426c0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C6>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c7: i2c@426d0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426d0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C7>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c8: i2c@426e0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426e0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C8>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi5: spi@426f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x426f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI5>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi6: spi@42700000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42700000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI6>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi7: spi@42710000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42710000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI7>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi8: spi@42720000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42720000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI8>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + mu8: mailbox@42730000 { + compatible = "fsl,imx95-mu"; + reg = <0x42730000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0 0x42800000 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x42800000 0x0 0x42800000 0x800000>; + + usdhc1: mmc@42850000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42850000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_WAKEUPAXI>, + <&scmi_clk IMX95_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>; + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: mmc@42860000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42860000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_WAKEUPAXI>, + <&scmi_clk IMX95_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>; + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: mmc@428b0000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x428b0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_WAKEUPAXI>, + <&scmi_clk IMX95_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>; + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + }; + + gpio2: gpio@43810000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43810000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 4 32>; + }; + + gpio3: gpio@43820000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43820000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>, + <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>; + }; + + gpio4: gpio@43840000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43840000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>; + }; + + gpio5: gpio@43850000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43850000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>; + }; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x44000000 0x0 0x800000>; + ranges = <0x44000000 0x0 0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + mu1: mailbox@44220000 { + compatible = "fsl,imx95-mu"; + reg = <0x44220000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + tpm1: pwm@44310000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x44310000 0x1000>; + clocks = <&scmi_clk IMX95_CLK_BUSAON>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm2: pwm@44320000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x44320000 0x1000>; + clocks = <&scmi_clk IMX95_CLK_TPM2>; + #pwm-cells = <3>; + status = "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44340000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C1>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44350000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C2>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi1: spi@44360000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x44360000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI1>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi2: spi@44370000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x44370000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI2>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART2>; + clock-names = "ipg"; + status = "disabled"; + }; + + adc1: adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = , + , + ; + clocks = <&scmi_clk IMX95_CLK_ADC>; + clock-names = "ipg"; + status = "disabled"; + }; + + mu2: mailbox@445b0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445b0000 0x1000>; + ranges; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + #mbox-cells = <2>; + + sram0: sram@445b1000 { + compatible = "mmio-sram"; + reg = <0x445b1000 0x400>; + ranges = <0x0 0x445b1000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + scmi_buf0: scmi-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + scmi_buf1: scmi-sram-section@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + + }; + + mu3: mailbox@445d0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445d0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu4: mailbox@445f0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu6: mailbox@44630000 { + compatible = "fsl,imx95-mu"; + reg = <0x44630000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + }; + + mailbox@47320000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47320000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + mailbox@47350000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47350000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + /* GPIO1 is under exclusive control of System Manager */ + gpio1: gpio@47400000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x47400000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX95_CLK_M33>, + <&scmi_clk IMX95_CLK_M33>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 112 16>; + status = "disabled"; + }; + + elemu0: mailbox@47520000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47520000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu1: mailbox@47530000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47530000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu2: mailbox@47540000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47540000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu3: mailbox@47550000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47550000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + elemu4: mailbox@47560000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47560000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu5: mailbox@47570000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47570000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + aips4: bus@49000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x49000000 0x0 0x800000>; + ranges = <0x49000000 0x0 0x49000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + smmu: iommu@490d0000 { + compatible = "arm,smmu-v3"; + reg = <0x490d0000 0x100000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + }; + }; +}; From patchwork Wed Jun 5 01:22:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13686078 Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2050.outbound.protection.outlook.com [40.107.105.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ABF5C129 for ; Wed, 5 Jun 2024 01:14:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.105.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717550043; cv=fail; b=N4GAWfR/aB6wF0jorXRT9wwLNAPngewsE2rwDH01kq52xPpMAf464xnqInaU9gNEMZoO8daibnTeyceLFR/CceYp9ekdQxzckfSpL7RRUQyklR6DxO/bsb0869mWsjyPGiF3TaMcJSKAbhV80epCUucJyQvPIyegwty2psY/lDk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717550043; c=relaxed/simple; bh=bx28az3ePOPU0VUh94Z4aS0tfni01t3N6UobyD8VmG8=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=bJx7cN1yhL+EdD2XRrnN5PFEu9bW/3mukOgw1hkxuA8B8jpPnbr4e7kdl2J/Kb+dgcrR0aNd/L0QcI1r2aUHrOuetso6whqcE2VZR49rXyAfMEO5jj8JN1uKgkde05vZA0a2hfY4LqUGgMyVMKYo6Z1RbPSV/uU5zGzNxzQrbbM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (1024-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=fJ0e/DL+; arc=fail smtp.client-ip=40.107.105.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="fJ0e/DL+" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TipIp10cye5sj0hNu4IeFeVYM8JPAZfKfVNbzk0SxEeRbpA/C9MgaddwwFUTcn27+xNhNkqbgOZaKIVQqD8qYQAayke0YGJrt/EBHUHUrYuMhYifjFMUbFTcHEXImytk9+awiEaDjwvb1D8laGjKarVpsIVjOL+AOLeFPQ4am+5MMmatqWuQpI5HmdAAd78QgcGPSR7DkEZb0CqABYkflfS0URR4xM9CphwA/8xIhwGrHYwpBraGHXY6Qw5gXhDOFEtB1EU4ar7lXbGKlpzu7ph7ESb2LgUgjxJDYAkeTaF3J/UIyNLuB7UbE0lHmAXsUDEtCif75qFNn941zZOrow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=P1cuRznwBBCFztAAmtEmfFPa3B9gNpa9zLWfjFslTxw=; b=igYAmZfxg8pXMIG1JYNEv8nHv96NI0hqxVuf2Pw4niNoNWnzt8TzTj3O0l9OGEJvYtvENshDkDj9OJDx2d/nkk1j5wiRc4+9N4e29rcCP7Jb7bn7nBbkByCMo4OZ46gTxE1+F1jC9HirlWuFyp2FwCqApZjOh3ALnhXIXQ21vY0NJRjUbhBppW6+qteU833QqiR30AJEDlXdWnpA4yHh8zvoP2eXjBx7phVsq+DvZ9GSuiGjXLBvVMDhLzdFla4RNtymRfuMJZv37eeXRpgRmEcqF/SzHae5sPLtbQYsGXSWHUqh4BBHMnKyAoVHKBh+E7aZO6rYB0TScyhWRSrpSQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=P1cuRznwBBCFztAAmtEmfFPa3B9gNpa9zLWfjFslTxw=; b=fJ0e/DL+QftJx4Gj0qiAFA3rliYyKV+c6HRQpt40gjb1ZGTUqYgk3Pr6uOIXqsrjlOl5hqJFd5G9dzCK9iKpxOsbLajphw3RzIATBzn92t9W4w+x8Vl4OoMYAOO1+v1UfAXXTsTPW1+jdIl+1vAacIjAPvNNW+AuyPetx7Ik9Nw= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by PAXPR04MB9668.eurprd04.prod.outlook.com (2603:10a6:102:243::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.24; Wed, 5 Jun 2024 01:13:55 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::557f:6fcf:a5a7:981c]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::557f:6fcf:a5a7:981c%7]) with mapi id 15.20.7633.021; Wed, 5 Jun 2024 01:13:55 +0000 From: "Peng Fan (OSS)" Date: Wed, 05 Jun 2024 09:22:50 +0800 Subject: [PATCH v6 3/3] arm64: dts: freescale: add i.MX95 19x19 EVK minimal board dts Message-Id: <20240605-imx95-dts-v3-v6-3-2ce275ed0e80@nxp.com> References: <20240605-imx95-dts-v3-v6-0-2ce275ed0e80@nxp.com> In-Reply-To: <20240605-imx95-dts-v3-v6-0-2ce275ed0e80@nxp.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Alexander Stein , Peng Fan X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717550578; l=6852; i=peng.fan@nxp.com; s=20230812; h=from:subject:message-id; bh=UCjvqFW5Qo13fFnueDa71qcBnQ8Gxyqod4aW0CarYVI=; b=HLVxSDzNyHSZTC2CkH4LbiLkAylNZPK8NJg2JCjhZMdtFVh2pO9PDLKSYalAu+u97EqH0he2k oZmY1TV9H+gCD2zdSQzuWHNIkBrERTnuUYBY1k4NwuAEYU121oY8RNZ X-Developer-Key: i=peng.fan@nxp.com; a=ed25519; pk=I4sJg7atIT1g63H7bb5lDRGR2gJW14RKDD0wFL8TT1g= X-ClientProxiedBy: SI2PR01CA0028.apcprd01.prod.exchangelabs.com (2603:1096:4:192::21) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|PAXPR04MB9668:EE_ X-MS-Office365-Filtering-Correlation-Id: 1d5bd2bc-feb2-4540-97dc-08dc84fcc565 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|7416005|52116005|1800799015|376005|366007|38350700005; X-Microsoft-Antispam-Message-Info: =?utf-8?q?gvQdLKc/RJ+aT+CGEV+AdAGuZx0VnkJ?= =?utf-8?q?zZrHpFGHSS1kPT/EoO50H1jNM46S5jxjx5g1nB7GuV0RN3nm/giY6YZXmDb3R33Oy?= =?utf-8?q?sAc6qS+jM2nQyoVJethQ6F4mhd27e3mNdNIdCEmXzXoFfATOYFLKsiZci13jfQHAp?= =?utf-8?q?wRDqoM9vLXaoofHqhzGQuehHFqRHJJxslAKAsyA3Vs+o0AW326tcCxbSC+tDxbiVq?= =?utf-8?q?elGfzwHwTJyRX8Gb4TGTz298fAl7gQppXpoozosn0qSqOovJGC+2SieL5i4SX5l8R?= =?utf-8?q?n0EPS82pykFV3OUsGqsaIJqySrd10eBZisiOWxbn7XR3tyAySEtF4l5FweqNPGgx+?= =?utf-8?q?0kCOkzB7S8ZneAbPeKHWM4qCnWKRODK/PVMXurmtr4H7IVi4EL1d13k0gEtxjqTjM?= =?utf-8?q?sx785AeNpXL4mppRc4vZXfIInCvipReIdyyVjBdrLKlcsfhqYBDX7shS3IewWHhw6?= =?utf-8?q?3meDcxt49IeSFHQrGoky9hdnMGaSBD5S9tEKVjXP9QYF35mdVdze8uiZZ/EQBnC8/?= =?utf-8?q?vibpDWkiEku9RnsWGGinnuDZfOKrkhBWcV8bw0Yhwi0MoGi6x5XNv4g+mmr4kXziN?= =?utf-8?q?hQsf458A5m8AL0GygMb9ltw/Va+IVv/p1iMBbpX5v2fYJaqLP9HUEG6FEeNVGDYCn?= =?utf-8?q?KHjWTbL74bZwsQLpp+YDqYOFhpFV9m5oOfW4smAIIEPfH093XfZmY0FoJ5gaPV2Rj?= =?utf-8?q?/U68rVh2IsrxPWRFvGQqeN2hHlLAC00Rgu1o7HnIsXf3Zk00NvJSNKeijMLJPBDIj?= =?utf-8?q?d3EX4q2m6U3kqDAF663xG+CzwjgrZV0kLkM0VJrX9+VDrTO7mdI1WI7ocLG+zHYgL?= =?utf-8?q?JrkeuTIZ7jlFc6fUuDzgZ9WwTXSzvKqyicbTJ4qi+H45+HnqF425JKa3TCRy67VkW?= =?utf-8?q?ToOAD86q57FuxT+4iCSsLeCuCpqzXU2FifEBhwnZOkSj4MEx7JNqedt+3BHljIc5y?= =?utf-8?q?bDN7GPbiQG/B9orlsPoddH4mwPnbz2H5m41XL27+f4ETFraBwnWfz/h0uP0mzaaWM?= =?utf-8?q?vD4I/fNIRbBrMotIzN9tvy8dFl+EDZnN45bZy4KXg8xeoNcvRJKvdasmoIig8jsfM?= =?utf-8?q?pwrbodOng/G3MiMAoS21NhJ/a9klGBcMiNSKf3Em4j88QVwI2PdXfc6R7+b4JlYoU?= =?utf-8?q?H4xsEn7hD1wKkf3LztU0QhUGCPnzHXG54MtuC5Smmv/fLanSkTqbUxbpwULi8dLj/?= =?utf-8?q?kjKRBgWZkLHT0XYfh6FiguozIwr1bPGda2MgxmmI9Mv9NmfBdV/ZMQu3k3CklY3Fi?= =?utf-8?q?kYGOcctByVYP38Xg5janZHyAnWmnUyN0uTg=3D=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DU0PR04MB9417.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(7416005)(52116005)(1800799015)(376005)(366007)(38350700005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?n3rL8gjmwfozIYtF+5LWuQicfL3L?= =?utf-8?q?zAwq+05Vvv63AkU2ijPEW1m14LWeiZhT+3V52xGoAsfwOPXGn6bKUJmaYZ5jIUvC4?= =?utf-8?q?lqRAHpta4rl8M5DK/oGegyfjrpnZDOiBOiHPYd8sKl0yVRAlbYh86N57+iui0E3wk?= =?utf-8?q?No0AjFqALfuRsUufWUjrVaDyA846GtNGPTvawH4Wo6FiAZkF8yUpPI25C8x/aXE6w?= =?utf-8?q?/3I6JaJ6bKD6CowE7YykTl9Ujn+DohBSuDzPhfhOC6rcpJnZSM9Ew3C7GiE9TDVrj?= =?utf-8?q?L2XFzAHeIIArEBvc/7CWpglNj7EiStCMRn3tD8fsd2tnK6jvPubD61V07VhxPAfBP?= =?utf-8?q?jmUnkCCT0kLsl9o1pwu04xkOujoIZF+l8SfVZELdSr1QpzEy7NspioVh0Fc4p2VDG?= =?utf-8?q?lg282A4Nd3erBKcGd4s68msp5J0sTgR3X8MiS+s9zEQ10Hc1AqAnbJv43XB/NGqZc?= =?utf-8?q?UQRiAzt9iVilopaHu/bMO4J7bPoncgMCeDspFX17HSP/bfmIb3tevUbsNgOOg9wLR?= =?utf-8?q?DuTWD5ibiTMXsNhGZ5sIr3XNLd4ka3CKq2Ofkm85fuiJAcMvW2JPtdS0Hk80ayWNj?= =?utf-8?q?cHDgZfRyToZDLPq26dwSKbDKFth/ISeu17HiB9jJPlAmdt1r2WXhDN+R8nG/B5A1/?= =?utf-8?q?t4lGuhKZE1jtluPjPfJ7gJ+MTZTjF5x8yAqQs6Jd9POrgQjNJ6RvmTIIxGpsvpU1k?= =?utf-8?q?b9IMPNq7a6FRP0gDizH5Z7heJV4cw1UwBSWoSaf9jgZtTRydKrfT+YEOvvgNUhfXC?= =?utf-8?q?oK1VAhhduMcXuk38NL5Fmzz1q9B7zKM90uEql/ehcfvS8vYscaYcTx9iu77VJhe1G?= =?utf-8?q?52xcNENEHMeGc+TRYpWbpFfnglg+iuGZkmCJIK1CzkP3IKZvPiujapUAA0rbpXUox?= =?utf-8?q?Z56Gq3+SOObfsY7HxOdJrgmyvUVMz2cGCp2UswhHHfwffmRU2dElFeJpmk1Hi1vgV?= =?utf-8?q?rLdlViQ+SlnqpSEVQVy6m4XRBRLFBq6Emi6XXnfTDvgctdxDDBZDrHie/LKTMdW2r?= =?utf-8?q?rTJWStMZ2FCPmhohoJhcS8puJi3QfTv29BSmjd6FSIBiYxZSUUuudiPuXytDgQv1G?= =?utf-8?q?7W89zZySymJuoEHzmS5WJT87gYtKkd0zL19q7ExtekVk0tFCv7wgaZPqRM4VDuZ8d?= =?utf-8?q?DqdEerTKhKRvauExuW9s5z0IiOfpJmnzPnD1aU705mTBEI2f174rfPlqbcRw8RnYH?= =?utf-8?q?VSq9yZb/IFH6zF7CZtJ6SopO4ZA68JJ1ivNCSHko7l0ZMInU5fCnIkaJuRKtH/9Hg?= =?utf-8?q?NpDFySXSuCMNsLGoDbPDVw+Pq0f037AsRuAyg4q0b0CNzzSPjwjNYkdiDO2OZZk+V?= =?utf-8?q?6UZVV+qV4iEaUJwGhT7nyMPwtmiJh5hh0w0nyaoHy4VTnkmrKta9mmQ4pkFPkKdnO?= =?utf-8?q?WsVZBuET8ymrkvXgRbEfd9OWZ2Iipj2tBpoBKf75+9yP7M57oHeZAwyEVzozXLPWl?= =?utf-8?q?x+Pjm0H3W3imqgcxvK5k8BQddpfvzk0Dd1YdsYYViZHKkMmSkragbAteJAKY2/mym?= =?utf-8?q?PcSpNLDav8Vn?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1d5bd2bc-feb2-4540-97dc-08dc84fcc565 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2024 01:13:55.8960 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: MgbVaN2UloJY+N3NB6R60CktjFj1niZ23bcUbqn4+06lx/U7DR9awqbt0eve+EQAd299bwQX85OnnKOFAH0aZQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB9668 From: Peng Fan Add a minimal dts for i.MX95 19x19 EVK board: - lpuart1 as console - sdhc1/2 as storage Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 200 ++++++++++++++++++++++ 2 files changed, 201 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 1b1e4db02071..c3fef4e4d8dd 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -239,6 +239,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts new file mode 100644 index 000000000000..2c2f3cfbe11a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +/dts-v1/; + +#include "imx95.dtsi" + +/ { + model = "NXP i.MX95 19X19 board"; + compatible = "fsl,imx95-19x19-evk", "fsl,imx95"; + + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + size = <0 0x3c000000>; + linux,cma-default; + reusable; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VDD_SD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; +}; + +&lpuart1 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&mu7 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +};