From patchwork Wed Jun 5 10:07:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Debief X-Patchwork-Id: 13686544 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F378A190050 for ; Wed, 5 Jun 2024 10:07:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717582057; cv=none; b=t9DH3osmWpqmur5DFtvRi+B5uGIkeGiE/dNYVkXHEuK3LEn+SnbwuJNFaMiOG1SKf8pRqL/lgq1ZFXnJ8J5aakHgly2fwejE5FHLsYtlApL3WsNyLz78JsXoL3+9RLZyECmItdYmueYmCBlQmSr96ILT7djEFSW6IvOI5SV0QAM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717582057; c=relaxed/simple; bh=Z1cmO6rPxlcqil03+PLEWeKEDxanAwUup6VEPlIsJRg=; h=MIME-Version:From:Date:Message-ID:Subject:To:Cc:Content-Type; b=HXbQac7pKsHjupTU4suloe34AH+7Rl/qp1hCjL4ATyNUHhgxGykoXZF5+dvFguZwyhMKp5MQfK22TyQ3eyldZwKYMPfJ+5RLlWnUgdLceFZz/n/SMHKe2ken8BtVM8KdC9Izy6y2JJz6tkKPUqcMevb2tZwBns1/UsPpVI8ge6Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=digigram.com; spf=pass smtp.mailfrom=digigram.com; dkim=pass (1024-bit key) header.d=digigram.com header.i=@digigram.com header.b=XEz4auoR; arc=none smtp.client-ip=209.85.167.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=digigram.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=digigram.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=digigram.com header.i=@digigram.com header.b="XEz4auoR" Received: by mail-lf1-f44.google.com with SMTP id 2adb3069b0e04-52b919d214cso4061832e87.2 for ; Wed, 05 Jun 2024 03:07:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=digigram.com; s=google; t=1717582054; x=1718186854; darn=vger.kernel.org; h=cc:to:subject:message-id:date:from:mime-version:from:to:cc:subject :date:message-id:reply-to; bh=PZyXYMsbHdj75aClIqd976E9cE6JwMK9h0UyQ5uxPRw=; b=XEz4auoR2wBXzUZ67wJ3A1vg6yxOeVUFti6qGLrBfl7TYFSJ7uo2lqV8lFRZWk4pVk rmewbMff5fgRw/H7vlRoekEAbq9FFzO8pWx950YQiLvjX/vCqsauyfHjjL8WR0tS/6k6 8aY1GFA62E8NRxG4GeHTx9MQlXagt4I2VOXP8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717582054; x=1718186854; h=cc:to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=PZyXYMsbHdj75aClIqd976E9cE6JwMK9h0UyQ5uxPRw=; b=DIszPFBLOXIZAOHjeDNZy6oZQ6VOTuo1iBaGxkAaViPK4iZPxhdLgE/od0Xgeh6js0 qa0/KGjNV9nVmbzev6bNxZWlYDCbvQPgawROQ0nXJR24oM2ytYSHU/2y/t2ewcM98bXm eHvv2qcXebZTCyyO6icRD6yeXK67msukxIzn+tL/Xu0sG7Vy9MAXUwmQIDXV69qebt2l KhTyyUYmYJzjsxZAXaqRRU4tJUMACO91UgokVg4vHklAqnK74ztMRe4boLAUpO2lmFqy 0NAgEF784A2+jkBW1awpgycbnYTRfZdqdB6Kg6I1rFJDexq/ApDZ1FZUhE0199ByOoe2 375w== X-Gm-Message-State: AOJu0Yy8KZzokAzn3vFS7mWF0l85/Ew1ptzLLMJ4TfMSAuFTj828XlNh dw54aVaRRJoKLbsokf5LooKAo3vP62pJ1DxaNHJtpnMdebtplGqdP53nn7489zr0qp6IWnbWaED rtTP95r6X64jF1GVW876NxCvxM/vDruAMdyo2WY0YLLT43d+mhLtkTaLFwGDTPuWjyH+SWptqaE QMoJIRsT4xqI3u1qoDEl5IUE2jx3XEtKjxNslLPbkc4w== X-Google-Smtp-Source: AGHT+IHihZdyHyfULq3k3SPbHSjAVf2aBdLL59RQgVmDVcATLaNxfdiJV+DFZw7TPrHh1QfnsePt6jF/F74ck4/2KvA= X-Received: by 2002:a05:6512:3986:b0:52b:796f:8af5 with SMTP id 2adb3069b0e04-52bab4db844mr1651507e87.34.1717582053818; Wed, 05 Jun 2024 03:07:33 -0700 (PDT) Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Eric Debief Date: Wed, 5 Jun 2024 12:07:07 +0200 Message-ID: Subject: [PATCH 1/3] : XDMA's channel Stream mode support To: dmaengine@vger.kernel.org Cc: Lizhi Hou From ffe05a12ee7d9e9450f24deb54c2b5b901a5eebb Mon Sep 17 00:00:00 2001 From: Eric DEBIEF Date: Thu, 23 May 2024 17:21:23 +0200 Subject: XDMA stream mode initial support. If the Channel is in STREAM Mode, a C2H Write back structure is allocated and used. This is an initial support as the write back is allocated even if the feature is disabled for the Channel. The End of Packet condition is not handled yet. So, the stream CAN only be correctly closed by the host and not the XDMA. Signed-off-by: Eric DEBIEF --- drivers/dma/xilinx/xdma-regs.h | 5 +++ drivers/dma/xilinx/xdma.c | 64 +++++++++++++++++++++++++++++++--- 2 files changed, 65 insertions(+), 4 deletions(-) } @@ -705,7 +731,8 @@ xdma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t address, src = &addr; dst = &dev_addr; } else { - dev_addr = xdma_chan->cfg.src_addr; + dev_addr = xdma_chan->cfg.src_addr ? + xdma_chan->cfg.src_addr : xdma_chan->c2h_wback->dma_addr; src = &dev_addr; dst = &addr; } @@ -801,8 +828,16 @@ static int xdma_device_config(struct dma_chan *chan, static void xdma_free_chan_resources(struct dma_chan *chan) { struct xdma_chan *xdma_chan = to_xdma_chan(chan); + struct xdma_device *xdev = xdma_chan->xdev_hdl; + struct device *dev = xdev->dma_dev.dev; vchan_free_chan_resources(&xdma_chan->vchan); + if (xdma_chan->c2h_wback != NULL) { + dev_dbg(dev, "Free C2H write back: %p", xdma_chan->c2h_wback); + dma_pool_free(xdma_chan->desc_pool, + xdma_chan->c2h_wback, + xdma_chan->c2h_wback->dma_addr); + } dma_pool_destroy(xdma_chan->desc_pool); xdma_chan->desc_pool = NULL; } @@ -816,6 +851,7 @@ static int xdma_alloc_chan_resources(struct dma_chan *chan) struct xdma_chan *xdma_chan = to_xdma_chan(chan); struct xdma_device *xdev = xdma_chan->xdev_hdl; struct device *dev = xdev->dma_dev.dev; + dma_addr_t c2h_wback_addr; while (dev && !dev_is_pci(dev)) dev = dev->parent; @@ -824,13 +860,33 @@ static int xdma_alloc_chan_resources(struct dma_chan *chan) return -EINVAL; } - xdma_chan->desc_pool = dma_pool_create(dma_chan_name(chan), dev, XDMA_DESC_BLOCK_SIZE, - XDMA_DESC_BLOCK_ALIGN, XDMA_DESC_BLOCK_BOUNDARY); + //Allocate the pool WITH the C2H write back + xdma_chan->desc_pool = dma_pool_create(dma_chan_name(chan), + dev, + XDMA_DESC_BLOCK_SIZE + + sizeof(struct xdma_c2h_stream_write_back), + XDMA_DESC_BLOCK_ALIGN, + XDMA_DESC_BLOCK_BOUNDARY); if (!xdma_chan->desc_pool) { xdma_err(xdev, "unable to allocate descriptor pool"); return -ENOMEM; } + /* Allocate the C2H write back out of the pool in streaming mode only*/ + if ((xdma_chan->dir == DMA_DEV_TO_MEM) && + (xdma_chan->stream_mode == true)) { + xdma_chan->c2h_wback = dma_pool_alloc(xdma_chan->desc_pool, + GFP_NOWAIT, + &c2h_wback_addr); + if (!xdma_chan->c2h_wback) { + xdma_err(xdev, "unable to allocate C2H write back block"); + return -ENOMEM; + } + xdma_chan->c2h_wback->dma_addr = c2h_wback_addr; + dev_dbg(dev, "Allocate C2H write back: %p", xdma_chan->c2h_wback); + } + + return 0; } diff --git a/drivers/dma/xilinx/xdma-regs.h b/drivers/dma/xilinx/xdma-regs.h index 6ad08878e938..780ac3c9d34d 100644 --- a/drivers/dma/xilinx/xdma-regs.h +++ b/drivers/dma/xilinx/xdma-regs.h @@ -95,6 +95,11 @@ struct xdma_hw_desc { #define XDMA_CHAN_CHECK_TARGET(id, target) \ (((u32)(id) >> 16) == XDMA_CHAN_MAGIC + (target)) +/* macro about channel's interface mode */ +#define XDMA_CHAN_ID_STREAM_BIT BIT(15) +#define XDMA_CHAN_IN_STREAM_MODE(id) \ + (((u32)(id) & XDMA_CHAN_ID_STREAM_BIT) != 0) + /* bits of the channel control register */ #define CHAN_CTRL_RUN_STOP BIT(0) #define CHAN_CTRL_IE_DESC_STOPPED BIT(1) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index e2c3f629681e..c2a56f8ff1ac 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -51,6 +51,20 @@ struct xdma_desc_block { dma_addr_t dma_addr; }; +/** + * struct xdma_c2h_stream_write_back - Write back block , written by the XDMA. + * @magic_status_bit : magic (0x52B4) once written + * @length: effective transfer length (in bytes) + * @PADDING to be aligned on 32 bytes + * @associated dma address + */ +struct xdma_c2h_stream_write_back { + __le32 magic_status_bit; + __le32 length; + u32 padding_1[6]; + dma_addr_t dma_addr; +}; + /** * struct xdma_chan - Driver specific DMA channel structure * @vchan: Virtual channel @@ -61,6 +75,8 @@ struct xdma_desc_block { * @dir: Transferring direction of the channel * @cfg: Transferring config of the channel * @irq: IRQ assigned to the channel + * @c2h_wback : Meta data write back only for C2H channels in stream mode + */ struct xdma_chan { struct virt_dma_chan vchan; @@ -73,6 +89,8 @@ struct xdma_chan { u32 irq; struct completion last_interrupt; bool stop_requested; + bool stream_mode; + struct xdma_c2h_stream_write_back *c2h_wback; }; /** @@ -472,6 +490,8 @@ static int xdma_alloc_channels(struct xdma_device *xdev, xchan->base = base + i * XDMA_CHAN_STRIDE; xchan->dir = dir; xchan->stop_requested = false; + xchan->stream_mode = XDMA_CHAN_IN_STREAM_MODE(identifier); + xchan->c2h_wback = NULL; init_completion(&xchan->last_interrupt); ret = xdma_channel_init(xchan); @@ -480,6 +500,11 @@ static int xdma_alloc_channels(struct xdma_device *xdev, xchan->vchan.desc_free = xdma_free_desc; vchan_init(&xchan->vchan, &xdev->dma_dev); + dev_dbg(&xdev->pdev->dev, "configured channel %s[%d] in %s Interface", + (dir == DMA_MEM_TO_DEV) ? "H2C" : "C2H", + j, + (xchan->stream_mode == false) ? "Memory Mapped" : "Stream"); + j++; } @@ -628,7 +653,8 @@ xdma_prep_device_sg(struct dma_chan *chan, struct scatterlist *sgl, src = &addr; dst = &dev_addr; } else { - dev_addr = xdma_chan->cfg.src_addr; + dev_addr = xdma_chan->cfg.src_addr ? + xdma_chan->cfg.src_addr : xdma_chan->c2h_wback->dma_addr; src = &dev_addr; dst = &addr; From patchwork Wed Jun 5 10:07:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Debief X-Patchwork-Id: 13686545 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA1B2190070 for ; Wed, 5 Jun 2024 10:07:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717582060; cv=none; b=FESuNBnOB1PP1UoBV1ma6Q4lXW1+sZlfjZPiZVEIEkbsRxJMe8fPyynRoYOViNxzH4A2yMQmYo8vOm6pc3doGmZpGkxDkpO0ADBNiJsHhYqj0cpwDHRDLBOtk73y9emdLKnxmBnDKnkJMrYI78lrcfxTSowS9fhaURcPa3/tx4A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717582060; c=relaxed/simple; bh=FoGZHxTp8eP5yGnrvKq7en6xXyZU38qjm48ef3UFK+0=; h=MIME-Version:From:Date:Message-ID:Subject:To:Cc:Content-Type; b=prl208JwAybYN9woRGxwUAfzKMIzXcMHDJl1Dz95FEbrdWpDJg5hITIGNiQGe97hqvbMR4P8WaPL/mgocsDtPMireYLYw+GOgWUuNqlczRVMwy6wfqR7EtRCqQMzXs6P6aLJkO3zhXpPMlZQxM4hCc9cSzVfez9u4AHuKK0j7l8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=digigram.com; spf=pass smtp.mailfrom=digigram.com; dkim=pass (1024-bit key) header.d=digigram.com header.i=@digigram.com header.b=alkmxNsa; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=digigram.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=digigram.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=digigram.com header.i=@digigram.com header.b="alkmxNsa" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-42155dfc484so6335365e9.1 for ; Wed, 05 Jun 2024 03:07:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=digigram.com; s=google; t=1717582057; x=1718186857; darn=vger.kernel.org; h=cc:to:subject:message-id:date:from:mime-version:from:to:cc:subject :date:message-id:reply-to; bh=ULRX1pmmSfWpj2F3DT/mr/MfnQljB+A05Dy9I4dgzmU=; b=alkmxNsaZXQH8yVtVYK03tZ0XhCLuwsFse69+cHGNr/N8UXkCudn/jQjW9boaTGp5L qgDgKa6CC4zKLfgOY7PP82SF6yXk41WZOO8YAjocncQjWe5nQApJ/zVe5ZLT813m1H1K /av13U1UaLmcoq/ZYOma0PHx8rH6woAoPLvGI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717582057; x=1718186857; h=cc:to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=ULRX1pmmSfWpj2F3DT/mr/MfnQljB+A05Dy9I4dgzmU=; b=xGY6qzwB7h/AGmumvMFgO3rIQBu15sfSPGEZ8CRQG6hfYD7+Qu3sUgCSqAxbTQ0Sa5 kNzu4OszIZ8QzyPBHs4Y83Py5/T5fAJuwMx0kMxDw31vPDPog4tt1PUSOzegV7EoAJiF 1JIZzVeyrPqCvKxXyPqD2DK1eIDGdM+O1h5DK1vVU1SX4lD6OKNe7doVdx1LYnjFOyTW 3fs4Kc2cqDoYP6GHYyVXisTgIVQ+yCha0AgdjoJq9Po08X68Zq6jDPgVS5BZdJ0QCQYG i6Mhgcd9yhTtMR/brTWrCLnWn5QS5Gu6FoIWyUA28oogNPD2RjhbH773LF4D93/TMvUH fbTQ== X-Gm-Message-State: AOJu0Yz5doE6N8qHDja6nWafYUwYkqHUDEhy8+C5TrMyzgo/+jZG5+A9 q1unM0Mkta1Oo7viNXRtv3l5G1+vjBvI858JxOIWHUR8vgXPJ7X101EzTDsfirLnFosgI9lmgre p1hJu9KOIH+wKxODpw4H4XQX7xNq1KHSozz6rbYoLchUNW6xbQXDSCVweUgHSNQPiOVo/Cwcz/0 an/Vg0RhJznCV6/DYN7TI7VIEATisoVdQ0lmEzeus= X-Google-Smtp-Source: AGHT+IF4nJ8UNz5gqOzsHB1S/opWMw29hf6ZGgaZxIHU0PArDWSpoaIDy1PXeYI3q/3fux+VxWotor40VhrJALtEFD4= X-Received: by 2002:a5d:52c1:0:b0:354:f92f:fcfe with SMTP id ffacd0b85a97d-35e8ef1898emr1507646f8f.35.1717582056672; Wed, 05 Jun 2024 03:07:36 -0700 (PDT) Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Eric Debief Date: Wed, 5 Jun 2024 12:07:11 +0200 Message-ID: Subject: [PATCH 2/3] : XDMA's channel Stream mode support To: dmaengine@vger.kernel.org Cc: Lizhi Hou From f68193ed7891d3367085f8c2af202c1fc2d8abb2 Mon Sep 17 00:00:00 2001 From: Eric DEBIEF Date: Fri, 24 May 2024 17:03:38 +0200 Subject: XDMA stream support: set wb desc addr only if allocated. WriteBack descriptor is allocated only in STREAM Mode. Signed-off-by: Eric DEBIEF --- drivers/dma/xilinx/xdma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) dst = &addr; @@ -731,7 +731,7 @@ xdma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t address, src = &addr; dst = &dev_addr; } else { - dev_addr = xdma_chan->cfg.src_addr ? + dev_addr = xdma_chan->c2h_wback == NULL ? xdma_chan->cfg.src_addr : xdma_chan->c2h_wback->dma_addr; src = &dev_addr; dst = &addr; -- 2.34.1 diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index c2a56f8ff1ac..3c7fcad761e8 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -653,7 +653,7 @@ xdma_prep_device_sg(struct dma_chan *chan, struct scatterlist *sgl, src = &addr; dst = &dev_addr; } else { - dev_addr = xdma_chan->cfg.src_addr ? + dev_addr = xdma_chan->c2h_wback == NULL ? xdma_chan->cfg.src_addr : xdma_chan->c2h_wback->dma_addr; src = &dev_addr; From patchwork Wed Jun 5 10:07:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Debief X-Patchwork-Id: 13686546 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25B0419006F for ; Wed, 5 Jun 2024 10:07:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717582064; cv=none; b=iTi8CZcINChA60sAbTP7KGC8PM9hpNI3k941fyT3X1aqFqPFqjfp1aFEFaoT+K6Zmmz/I0h1hrztZKt7MhW1O8HMypo4OZV3UKJ4k6NJ4vWINeRK7UGwYbFqiNIVDmJLrbpfKmrqZUSjW/C/fuJX/ZpVPRt9SBMb0e7TdPW/RiI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717582064; c=relaxed/simple; bh=CcGzG1hpNdJEFY4tqni4lhHA0GJzAXaDwyrHV+GJb9o=; h=MIME-Version:From:Date:Message-ID:Subject:To:Cc:Content-Type; b=gJJV7tB05dJa+VYtbDBfTj6yGeEhavnrA30b8If0m69Cv544iKfa8NogZlqVT8aNiv2WI6w09DHIwRiNVG1iI9UeTwUYb6FCOZCoU8CkXZEi1Y66y2CfbnPL46viDsrebx1yrASFVxw3ic8Yik4LBjxFFRnNNt8MvN0ewBf83FM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=digigram.com; spf=pass smtp.mailfrom=digigram.com; dkim=pass (1024-bit key) header.d=digigram.com header.i=@digigram.com header.b=E9P3ao0f; arc=none smtp.client-ip=209.85.167.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=digigram.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=digigram.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=digigram.com header.i=@digigram.com header.b="E9P3ao0f" Received: by mail-lf1-f52.google.com with SMTP id 2adb3069b0e04-52b7ffd9f6eso6637223e87.3 for ; Wed, 05 Jun 2024 03:07:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=digigram.com; s=google; t=1717582061; x=1718186861; darn=vger.kernel.org; h=cc:to:subject:message-id:date:from:mime-version:from:to:cc:subject :date:message-id:reply-to; bh=GSIkQ7xeaTPYBDRPGg4aRUM5IWx1vIJgABOS8XYZ24A=; b=E9P3ao0ffQR69ATW3yy7YMQhUSGixHdRfpqwnYJVHlNY4pvG7ZZLQuDmEgOO9+0AA7 3dPp71vfzz7NCtrk/DJ+nhlDN2d0rCaA6LT9eOlnKukDICpmchi8wUpxsYeEh0e4QWSy 41EDQJNYHTfjYWFvIe3JCpqjuKdeH669F+mas= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717582061; x=1718186861; h=cc:to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=GSIkQ7xeaTPYBDRPGg4aRUM5IWx1vIJgABOS8XYZ24A=; b=cJMQsjmUslA8NmKAUCMA8xpq4HWSn0X9cN4zC/po6O2T2gyshLMjfWpWIuG6NXtiZP OSIwpEU0lZ7N4McWPm3QjH1MYRB23E6+8bO6KrkBwH2K8VP6LlMkaWO4MH0I27auBpkg Rb17v9581RrlLrdtEphJmo/ZFXsyUqIvmpJSyIn5baBscbWJzIX4QFObM8b8PJYYLezq EcOdHK5mAeX8I6z4IvVvN98EgTslfvGZauPmLsuMDRPcSHrgklTmZZSyaXWtucAoF1hy qSS+F+9lT3dPP/0mEISyEwF/Am7/XjCXHFfwSoJGAIO9Le0PnEY6oACBaTxlGraOd8jb /tvA== X-Gm-Message-State: AOJu0YwXeT6kM3TkQkqIT5re/jwGv+Uaq8NcPB4AjViQl8FmwpMNrYIC X05w6rpFonld7Jzww6f15Dg8+cBEJ6xlESezsp0S6gB6I9eWdL7sfT1JEyM7N8r1En4UpbhfT2y gRoMAZTVuP35EZrTnn2RbTyblySB6L3RExDsjjsvUhzktO77MOFh64nrE22/RQ7J1rjuYMI5M4U A8H9BlRaqZooZAfmRXEWlJr4gQGEfdrWWxy6M19zs= X-Google-Smtp-Source: AGHT+IGgjKyhJYWIk9VO6RsUz7mbHSDH0lyLsN4I/tcJ5qA0gNsGFp8u+ea7YU+aIuMFk41JebuWWqxp6d4wCb5sCvw= X-Received: by 2002:ac2:4adc:0:b0:523:41ba:a297 with SMTP id 2adb3069b0e04-52bab4b1291mr1250525e87.5.1717582061007; Wed, 05 Jun 2024 03:07:41 -0700 (PDT) Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Eric Debief Date: Wed, 5 Jun 2024 12:07:15 +0200 Message-ID: Subject: [PATCH 3/3] : XDMA's channel Stream mode support To: dmaengine@vger.kernel.org Cc: Lizhi Hou From 0a2c8951b770e2791b5fa7f8ec242074bcbf5c1f Mon Sep 17 00:00:00 2001 From: Eric DEBIEF Date: Mon, 27 May 2024 17:06:08 +0200 Subject: Add XDMA EOP support in C2H stream. In XDMA'isr the C2H EOP condition is checked with the Writeback descriptor. If true, the stream transfer considered as completed. Signed-off-by: Eric DEBIEF --- drivers/dma/xilinx/xdma-regs.h | 5 +++++ drivers/dma/xilinx/xdma.c | 18 +++++++++++++++++- 2 files changed, 22 insertions(+), 1 deletion(-) * xdma_channel_isr - XDMA channel interrupt handler * @irq: IRQ number @@ -941,7 +957,7 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id) u32 st; bool repeat_tx; - if (xchan->stop_requested) + if ((xchan->stop_requested) || xdma_is_c2h_eop(xchan)) complete(&xchan->last_interrupt); spin_lock(&xchan->vchan.lock); -- 2.34.1 diff --git a/drivers/dma/xilinx/xdma-regs.h b/drivers/dma/xilinx/xdma-regs.h index 780ac3c9d34d..5765f8f5eb96 100644 --- a/drivers/dma/xilinx/xdma-regs.h +++ b/drivers/dma/xilinx/xdma-regs.h @@ -100,6 +100,11 @@ struct xdma_hw_desc { #define XDMA_CHAN_IN_STREAM_MODE(id) \ (((u32)(id) & XDMA_CHAN_ID_STREAM_BIT) != 0) +/* C2H Write back */ +#define XDMA_CHAN_C2H_WB_EOP_BIT BIT(0) +#define XDMA_CHAN_C2H_WB_MAGIC_VAL (0x52B4 << 16) +#define XDMA_CHAN_C2H_WB_MAGIC_MASK GENMASK(31, 16) + /* bits of the channel control register */ #define CHAN_CTRL_RUN_STOP BIT(0) #define CHAN_CTRL_IE_DESC_STOPPED BIT(1) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index 3c7fcad761e8..247d775ffec2 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -925,6 +925,22 @@ static enum dma_status xdma_tx_status(struct dma_chan *chan, dma_cookie_t cookie return ret; } + +/** + * xdma_is_c2h_eop - C2H channel End of Packet condition status + * @xchan : the XDMA channel to be checked + */ +static bool xdma_is_c2h_eop(struct xdma_chan *xchan) +{ + if ((xchan->c2h_wback != NULL) && + ((xchan->c2h_wback->magic_status_bit & XDMA_CHAN_C2H_WB_MAGIC_MASK) == + XDMA_CHAN_C2H_WB_MAGIC_VAL)) { + return (xchan->c2h_wback->magic_status_bit & XDMA_CHAN_C2H_WB_EOP_BIT) != 0; + } else { + return false; + } +} + /**