From patchwork Wed Jun 5 20:10:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13687422 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28C96C25B76 for ; Wed, 5 Jun 2024 20:10:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3432910E804; Wed, 5 Jun 2024 20:10:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="DXZ609p7"; dkim-atps=neutral Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5AEC610E38F for ; Wed, 5 Jun 2024 20:10:26 +0000 (UTC) Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-57a52dfd081so211386a12.2 for ; Wed, 05 Jun 2024 13:10:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717618224; x=1718223024; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9Vw9DX3CSwtkdBUffdnArBNjtVj7mHBTphGyv2QQ9qI=; b=DXZ609p7vFLMnMOZGitlQVagy9fmYRCpExrR6hXKif7Mil1FodwwFRoaG7ojGEV2mU LwAzYlrKLMXq1XLtioPEH7vRZ2dz/X2s/PotJ/LaOEmP+tBoBR8FflmMXJCgx+ZzwSga 0YQnmjbDMXYeIxDDpzxQv+upePG3D6OJeQonv9kB7r6zBypzQQG/xx+8xMP/+m9svi6u 8ZRRah1nalupaiFGSQ4XLENVxK8HodKO2hpwnPuwBqiu/oHclhEqEieduz9C9Ab/irqZ 5CgtCLEXZwJHxxRi2tPp2bMzuWKq/zHAgVBFo3/hCHmS4oOayiYtZrTi/BCygCr+zr1B nwcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717618224; x=1718223024; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9Vw9DX3CSwtkdBUffdnArBNjtVj7mHBTphGyv2QQ9qI=; b=qiEnLySUkd3PDrfOb70LKvFa08OtCz/SzhhUnmx8S3qMZDShpDBy7s4fe4UuEscPhb rIRsh80b3luJFSY9BFF0Xpkr1vqcMP+FVuUjmmkv4Dlw/5pQ0mT9lbPbYkmNZbWfn4v0 T4DJMyAL03gKFf4ni0VJAWIeg8oQc15M1QBOj/yFnOFLVg80UETB5YyyyTVYdscuEWNs 0P/B+jLMGFGua16uoRXCLzqLSEKwVkFdcn34SkclQ2qPmLHGmoH03i9uPbPbPQ3DzfSt fF0mU4rgKiayyh07JCq/jpAaqtJ6Tu1Aw0te4dIC5daG1M9jDlOXkuHq7qaNm6ukGf4b tmSQ== X-Forwarded-Encrypted: i=1; AJvYcCX7Egh+WQV7gQzOIVgp2URTA475iTvRSECoY6VRYt72TvF9kYDWSoqKKR+Dbu33RKFKGLUWgewwdFNhvoVQNVIiO2Z32MTldH+mlciy+G+v X-Gm-Message-State: AOJu0YyF67OCeJWaLueJBNlu13PF3oNKQN6bW5HB+xoLewzayGnLat9H VnoATArLCwv2rZpzwK/13oDPiAnas4STja+/ZA16iQ1ffaVLrJb1o29fOdLCKdUA28H4oC+GHwp QGgA= X-Google-Smtp-Source: AGHT+IEqlV2I5Db8a+ZFkhPsAYnoI1F1oliPNdAwUP8AaIYo4Qee83CiizfDot/q8uaYVI2GD+cyRg== X-Received: by 2002:a50:d497:0:b0:578:6198:d6ff with SMTP id 4fb4d7f45d1cf-57a8bca263cmr2379893a12.33.1717618224135; Wed, 05 Jun 2024 13:10:24 -0700 (PDT) Received: from [127.0.1.1] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a31be4e36sm9717473a12.53.2024.06.05.13.10.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 13:10:23 -0700 (PDT) From: Konrad Dybcio Date: Wed, 05 Jun 2024 22:10:14 +0200 Subject: [PATCH v2 1/7] soc: qcom: Move some socinfo defines to the header MIME-Version: 1.0 Message-Id: <20240605-topic-smem_speedbin-v2-1-8989d7e3d176@linaro.org> References: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> In-Reply-To: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.14-dev X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In preparation for parsing the chip "feature code" (FC) and "product code" (PC) (essentially the parameters that let us conclusively characterize the sillicon we're running on, including various speed bins), move the socinfo version defines to the public header. Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/socinfo.c | 8 -------- include/linux/soc/qcom/socinfo.h | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 8087941a7887..beb23e292323 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -21,14 +21,6 @@ #include -/* - * SoC version type with major number in the upper 16 bits and minor - * number in the lower 16 bits. - */ -#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff) -#define SOCINFO_MINOR(ver) ((ver) & 0xffff) -#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff)) - /* Helper macros to create soc_id table */ #define qcom_board_id(id) QCOM_ID_ ## id, __stringify(id) #define qcom_board_id_named(id, name) QCOM_ID_ ## id, (name) diff --git a/include/linux/soc/qcom/socinfo.h b/include/linux/soc/qcom/socinfo.h index e78777bb0f4a..10e0a4c287f4 100644 --- a/include/linux/soc/qcom/socinfo.h +++ b/include/linux/soc/qcom/socinfo.h @@ -12,6 +12,14 @@ #define SMEM_SOCINFO_BUILD_ID_LENGTH 32 #define SMEM_SOCINFO_CHIP_ID_LENGTH 32 +/* + * SoC version type with major number in the upper 16 bits and minor + * number in the lower 16 bits. + */ +#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff) +#define SOCINFO_MINOR(ver) ((ver) & 0xffff) +#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff)) + /* Socinfo SMEM item structure */ struct socinfo { __le32 fmt; From patchwork Wed Jun 5 20:10:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13687423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4797BC27C55 for ; Wed, 5 Jun 2024 20:10:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C382110E80A; Wed, 5 Jun 2024 20:10:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="aEgx1PaE"; dkim-atps=neutral Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) by gabe.freedesktop.org (Postfix) with ESMTPS id CE49A10E402 for ; Wed, 5 Jun 2024 20:10:27 +0000 (UTC) Received: by mail-lj1-f172.google.com with SMTP id 38308e7fff4ca-2e72224c395so1979781fa.3 for ; Wed, 05 Jun 2024 13:10:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717618226; x=1718223026; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jMT/dov4rCwVnOSBADCi4X7D61kduzPQ+R9fcxd3Uto=; b=aEgx1PaEz+96TwMsXiRwutVM8bPU/eef+odVKNg2gBfxAh8uvXQ6VmFKOX0auDGM0r UDc+6fx4RdFnIDudFjDUed51LpYNNEmK4KcqyPv6vkr7hbiJ1z/WpKEuAP3BxKZLbxaI Fm5sMDfjlKrWhBA10sLx3UNQ2yCYEGGhGYz/DemAwflj8CPY0CGjv5xIYJl8gHr26bcj YuFjGSRJzbiMF/Yea/USD3RFW/cQ7HxyjVcS7wI+Bnag8P6sdw9WothqMVc23nW5u2aZ hcNvV1vpXEq9GnAdoN5aYmDEnq0eYNLp1j9YvNRLoBpO/VjCUlCwVWQtx67x10Qdpv6C dR2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717618226; x=1718223026; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jMT/dov4rCwVnOSBADCi4X7D61kduzPQ+R9fcxd3Uto=; b=Q3zPyshiob5E6Xf31hwWVrSbidXEE6YKPprXozJT24qWxsUuT+2+bkmX8wTHZQJoN6 YJWjdQnU0pcTk2pbwNpB4zp9SpQ1AD4UEToXBEAoQ56Uv6QD/oWIkIa9k1qwKvLZ9XuU dYnldI0Xnc6aJe8r0m7c5DE2oYr5dW15POPZcx/N3ShlvfiLb2AxFhD6M+zaS2H9rYRe YNQC44zmMWxjWwgv86RgQSRPTIaQWht1x2b4ahhFSzrfF1KfpqQnP617ijV3Zhf5hv93 I13dXBlpKC/XVeNeghYBuQyaE729xzwo+2wLWxB5uaLj8JqzRRycZ34/61KGRAXDPZk2 6NKg== X-Forwarded-Encrypted: i=1; AJvYcCUJw2szP1OfNXmycB8dnbU1GtbeDZDyv7/X8QZnLbj+4YKniYQyOPGAY6J7ZZ6yg5ENMPOs3zgwnxLncjqYln47tFwcmMWUDiJGUYkKN7ta X-Gm-Message-State: AOJu0Yx6cdc1Bl51nESsaVAqcuq4D4KJ+V8oYCYQbxtbWXsuktOG0FuW 8YqetG8FYmobBYpZUA+AdFXYFuMc9ZsWv7VoLnDBYMOc/yH/JXLVbZzjv+qlBlA= X-Google-Smtp-Source: AGHT+IEuGR6zo172budNUpiwYhBQNuR5eJEdRRfWLY7Lr+ygWqIyqGnJ89qQjCt+KNbyocrh3WLYOQ== X-Received: by 2002:a2e:9305:0:b0:2e9:8497:46ce with SMTP id 38308e7fff4ca-2eac7a71477mr20869651fa.46.1717618225806; Wed, 05 Jun 2024 13:10:25 -0700 (PDT) Received: from [127.0.1.1] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a31be4e36sm9717473a12.53.2024.06.05.13.10.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 13:10:25 -0700 (PDT) From: Konrad Dybcio Date: Wed, 05 Jun 2024 22:10:15 +0200 Subject: [PATCH v2 2/7] soc: qcom: smem: Add a feature code getter MIME-Version: 1.0 Message-Id: <20240605-topic-smem_speedbin-v2-2-8989d7e3d176@linaro.org> References: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> In-Reply-To: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.14-dev X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Recent (SM8550+ ish) Qualcomm SoCs have a new mechanism for precisely identifying the specific SKU and the precise speed bin (in the general meaning of this word, anyway): a pair of values called Product Code and Feature Code. Based on this information, we can deduce the available frequencies for things such as Adreno. In the case of Adreno specifically, Pcode is useless for non-prototype SoCs. Introduce a getter for the feature code and export it. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/smem.c | 33 +++++++++++++++++++++++++++++++++ include/linux/soc/qcom/smem.h | 1 + include/linux/soc/qcom/socinfo.h | 26 ++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 50039e983eba..e4411771f482 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -821,6 +821,39 @@ int qcom_smem_get_soc_id(u32 *id) } EXPORT_SYMBOL_GPL(qcom_smem_get_soc_id); +/** + * qcom_smem_get_feature_code() - return the feature code + * @code: On success, return the feature code here. + * + * Look up the feature code identifier from SMEM and return it. + * + * Return: 0 on success, negative errno on failure. + */ +int qcom_smem_get_feature_code(u32 *code) +{ + struct socinfo *info; + u32 raw_code; + + info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL); + if (IS_ERR(info)) + return PTR_ERR(info); + + /* This only makes sense for socinfo >= 16 */ + if (__le32_to_cpu(info->fmt) < SOCINFO_VERSION(0, 16)) + return -EOPNOTSUPP; + + raw_code = __le32_to_cpu(info->feature_code); + + /* Ensure the value makes sense */ + if (raw_code > SOCINFO_FC_INT_MAX) + raw_code = SOCINFO_FC_UNKNOWN; + + *code = raw_code; + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_smem_get_feature_code); + static int qcom_smem_get_sbl_version(struct qcom_smem *smem) { struct smem_header *header; diff --git a/include/linux/soc/qcom/smem.h b/include/linux/soc/qcom/smem.h index 03187bc95851..f946e3beca21 100644 --- a/include/linux/soc/qcom/smem.h +++ b/include/linux/soc/qcom/smem.h @@ -13,6 +13,7 @@ int qcom_smem_get_free_space(unsigned host); phys_addr_t qcom_smem_virt_to_phys(void *p); int qcom_smem_get_soc_id(u32 *id); +int qcom_smem_get_feature_code(u32 *code); int qcom_smem_bust_hwspin_lock_by_host(unsigned int host); diff --git a/include/linux/soc/qcom/socinfo.h b/include/linux/soc/qcom/socinfo.h index 10e0a4c287f4..608950443eee 100644 --- a/include/linux/soc/qcom/socinfo.h +++ b/include/linux/soc/qcom/socinfo.h @@ -3,6 +3,8 @@ #ifndef __QCOM_SOCINFO_H__ #define __QCOM_SOCINFO_H__ +#include + /* * SMEM item id, used to acquire handles to respective * SMEM region. @@ -82,4 +84,28 @@ struct socinfo { __le32 boot_core; }; +/* Internal feature codes */ +enum qcom_socinfo_feature_code { + /* External feature codes */ + SOCINFO_FC_UNKNOWN = 0x0, + SOCINFO_FC_AA, + SOCINFO_FC_AB, + SOCINFO_FC_AC, + SOCINFO_FC_AD, + SOCINFO_FC_AE, + SOCINFO_FC_AF, + SOCINFO_FC_AG, + SOCINFO_FC_AH, +}; + +/* Internal feature codes */ +/* Valid values: 0 <= n <= 0xf */ +#define SOCINFO_FC_Yn(n) (0xf1 + (n)) +#define SOCINFO_FC_INT_MAX SOCINFO_FC_Yn(0xf) + +/* Product codes */ +#define SOCINFO_PC_UNKNOWN 0 +#define SOCINFO_PCn(n) ((n) + 1) +#define SOCINFO_PC_RESERVE (BIT(31) - 1) + #endif From patchwork Wed Jun 5 20:10:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13687428 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 275ADC27C52 for ; Wed, 5 Jun 2024 20:10:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C67910E81C; Wed, 5 Jun 2024 20:10:47 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="vjfgihwn"; dkim-atps=neutral Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) by gabe.freedesktop.org (Postfix) with ESMTPS id 49BCE10E807 for ; Wed, 5 Jun 2024 20:10:29 +0000 (UTC) Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-57a2f032007so242488a12.0 for ; Wed, 05 Jun 2024 13:10:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717618227; x=1718223027; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hB/7Kb1VW4gFTXC7Yg+4jPgSlPqTTRx/zg0Jbjaqk2Q=; b=vjfgihwntthsxrrbWL44AQm+xVs9cDwgDG+Ll2TJHdfawWDZI74wYFBFhoQD1Rz/NL mAhOdxK3biVIUorI3DLMdDIOvdG3kB+r3P8lV4GQDp/ktg/PPgUeJQX9NFJtckyr2Auo ltenO57SD+IKrL8gf49O9TMR7nV7sPb4LVlMUxWjy+W5nrUixcB80MoUO3ar+cjc9byo Z6Hm+7IBTLvUA2rspkj9RVoE1+Q5r/SdqLxVVmgeYn7b7qSqQqEdYG8/9gZJxfODzUQC LEm/32EpRUlNq+PEmcSCX6NRLSyHpnZkg8mEtmDkEEqX7dxo6o87Q6jrXyw7WZS/9gzV qnEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717618227; x=1718223027; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hB/7Kb1VW4gFTXC7Yg+4jPgSlPqTTRx/zg0Jbjaqk2Q=; b=he0Ar+2FoVn9N4K2s+AlqQv64jSE31jMCDy+ddmioIL/bOix7auJBTp05JprtA2qbS ruHrLcVv0GhUP8xZVQwUTzhCFtAANmxRxfbRXxWmLYnny/hx5UMy2vx7MTGbCT6WvJ1O B3bJCWHP/wsAJJ47B2+lWsdYvBTRUw89AP/A+T7reY4GR9vOGhZi+3POwS+XppYfs8ex YpMGj46c476jIp6VQ/3pGPdEbOG2hvKFm9mTOe1iEvdhQ5Rd3TrKjDqT4nIwm5nz4ssb 0foXhS9mfXXNMU7popBFzMQ4SnlCAapeHF90Qi7l72uvDhdv0jIHmSr2zHLnEgsGtPZI jPxw== X-Forwarded-Encrypted: i=1; AJvYcCVaMUmyfOjC0WnOLaHI++6TqYp/YKnbvdsYbEW2zVZmeQad0paz0QRHbPlZP8PotRq5O97gP8GumVSy/ESwPwu8g4l4hkTPKujBWSV6KZGb X-Gm-Message-State: AOJu0Yyjm6TZ5RdDUteSHj4er+AsNSDhJbFnbGS3d/BCATb/dkzUbx45 ejhMPMPcaDIaa3aRMDdBFhXIvYjkQ7HEoG8+0BGPA6Q8sGvbB9ccVFnGSyTOFyY= X-Google-Smtp-Source: AGHT+IE1HK1zb72A1yjGoZvPGwo5Mrz8Ux6oOc+nkRD2t2RiWJ2159E6+Z5bPtsUlRepkwL8ZiNiyg== X-Received: by 2002:a50:a455:0:b0:578:6c3e:3b8f with SMTP id 4fb4d7f45d1cf-57a8b67c37fmr2448706a12.2.1717618227416; Wed, 05 Jun 2024 13:10:27 -0700 (PDT) Received: from [127.0.1.1] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a31be4e36sm9717473a12.53.2024.06.05.13.10.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 13:10:27 -0700 (PDT) From: Konrad Dybcio Date: Wed, 05 Jun 2024 22:10:16 +0200 Subject: [PATCH v2 3/7] drm/msm/adreno: Implement SMEM-based speed bin MIME-Version: 1.0 Message-Id: <20240605-topic-smem_speedbin-v2-3-8989d7e3d176@linaro.org> References: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> In-Reply-To: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.14-dev X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is abstracted through SMEM, instead of being directly available in a fuse. Add support for SMEM-based speed binning, which includes getting "feature code" and "product code" from said source and parsing them to form something that lets us match OPPs against. Due to the product code being ignored in the context of Adreno on production parts (as of SM8650), hardcode it to SOCINFO_PC_UNKNOWN. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 41 +++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 12 ++++++--- 4 files changed, 53 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 973872ad0474..3f84417ff027 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2894,13 +2894,15 @@ static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) return UINT_MAX; } -static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) +static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, + struct device *dev, + const struct adreno_info *info) { u32 supp_hw; u32 speedbin; int ret; - ret = adreno_read_speedbin(dev, &speedbin); + ret = adreno_read_speedbin(adreno_gpu, dev, &speedbin); /* * -ENOENT means that the platform doesn't support speedbin which is * fine @@ -3060,7 +3062,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); - ret = a6xx_set_supported_hw(&pdev->dev, config->info); + ret = a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); if (ret) { a6xx_llc_slices_destroy(a6xx_gpu); kfree(a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index c3703a51287b..901ef767e491 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -6,6 +6,8 @@ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. */ +#include + #include "adreno_gpu.h" bool hang_debug = false; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 074fb498706f..055072260b3d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -21,6 +21,9 @@ #include "msm_gem.h" #include "msm_mmu.h" +#include +#include + static u64 address_space_size = 0; MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space"); module_param(address_space_size, ullong, 0600); @@ -1057,9 +1060,39 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) adreno_ocmem->hdl); } -int adreno_read_speedbin(struct device *dev, u32 *speedbin) +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *fuse) { - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + u32 fcode; + int ret; + + /* + * Try reading the speedbin via a nvmem cell first + * -ENOENT means "no nvmem-cells" and essentially means "old DT" or + * "nvmem fuse is irrelevant", simply assume it's fine. + */ + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", fuse); + if (!ret) + return 0; + else if (ret != -ENOENT) + return dev_err_probe(dev, ret, "Couldn't read the speed bin fuse value\n"); + +#ifdef CONFIG_QCOM_SMEM + /* + * Only check the feature code - the product code only matters for + * proto SoCs unavailable outside Qualcomm labs, as far as GPU bin + * matching is concerned. + * + * Ignore EOPNOTSUPP, as not all SoCs expose this info through SMEM. + */ + ret = qcom_smem_get_feature_code(&fcode); + if (!ret) { + *fuse = ADRENO_SKU_ID(fcode); + } else if (ret != -EOPNOTSUPP) + return dev_err_probe(dev, ret, "Couldn't get feature code from SMEM\n"); +#endif + + return 0; } int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, @@ -1098,9 +1131,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) + if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) speedbin = 0xffff; - adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); + adreno_gpu->speedbin = speedbin; gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 77526892eb8c..8f2b70eaf6ad 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -81,7 +81,12 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a702_hwcg[], a730_hwcg[], a740_hwcg[]; struct adreno_speedbin { - uint16_t fuse; + /* <= 16-bit for NVMEM fuses, 32b for SOCID values */ + uint32_t fuse; +/* As of SM8650, PCODE on production SoCs is meaningless wrt the GPU bin */ +#define ADRENO_SKU_ID_FCODE GENMASK(15, 0) +#define ADRENO_SKU_ID(fcode) (SOCINFO_PC_UNKNOWN << 16 | fcode) + uint16_t speedbin; }; @@ -136,7 +141,7 @@ struct adreno_gpu { struct msm_gpu base; const struct adreno_info *info; uint32_t chip_id; - uint16_t speedbin; + uint32_t speedbin; const struct adreno_gpu_funcs *funcs; /* interesting register offsets to dump: */ @@ -519,7 +524,8 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); -int adreno_read_speedbin(struct device *dev, u32 *speedbin); +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *speedbin); /* * For a5xx and a6xx targets load the zap shader that is used to pull the GPU From patchwork Wed Jun 5 20:10:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13687424 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C567C25B76 for ; Wed, 5 Jun 2024 20:10:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7BBE810E809; Wed, 5 Jun 2024 20:10:37 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="x8mIs6Pj"; dkim-atps=neutral Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0888610E809 for ; Wed, 5 Jun 2024 20:10:30 +0000 (UTC) Received: by mail-lj1-f180.google.com with SMTP id 38308e7fff4ca-2eaac465915so2436131fa.1 for ; Wed, 05 Jun 2024 13:10:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717618229; x=1718223029; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rsxI5OJmE2RBtxZTRf/cc3jqaLSF49oqnXau0+l27fM=; b=x8mIs6Pjf+NJa3HEBbsizxX50dvsagWChX8jcD+AtyXJZw1jBCYvSmf9HbJscE8okc 1B6V0J+WCtyQMp1t8qNnx1UKHV47n7pEfw5DUaNAfkoKVuDR7UuCwaxHbiY5hiwbs3gp 12wcchBRQdFzgzS9vBwAAg/LTAUXr+/FlrKkFpahncILdhscB8jPgp5FTDr28JDwOeSN nMfwYciIV5iFR/Lknqr3+AgfW1llfgPp7ZX1hr2fS/PMMTplYgql5YlFt2BQ0zu9h+ZX xCSnaseHMq4AZdNVTT0XQg2bg3oJ6j0L/nsbDko/rMni8OT6AIRhq4oELdFAvrBcBvXR Wx7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717618229; x=1718223029; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rsxI5OJmE2RBtxZTRf/cc3jqaLSF49oqnXau0+l27fM=; b=wmhQDG+OQZ4dt3eQh4alaMHbixAlQWGuuIBZTMetYB9IEdyjR/4t62LaPrKT14EqVR CzcI+CfRvNWwilmYs8kcz/Wal/GQlTsDDkcxLYvWEhN01aHM3zdc/xG9XdqnYhYPwy3y 4bJOmA4A04HZvx3sv7bIAplJyIQbm93wr1lQneeaSo74na7i0YHeJ5ZB0AH/I0z0Z75W WT+07OlGokUcUqSkvKrCrHlvF9YGX0nLRstKfJhAMwm0M85gKJxX3m/DfGkOuPz+s1dL wGipxsbaTzJssGDReTZFmKt3b0aFG9Px7lbnOQCbFk/e9krIlKBUlnbM+ua6vv7t/BKu jx9g== X-Forwarded-Encrypted: i=1; AJvYcCUOXVM5Soy2ZmB6DgaMUapcLZtNAMnCaVoXgaVpZ+0gxpZZyP+c1G3DW0axSmmbJj72UVLTDYFKagZWd2nWk+Nxfj9Aa7v7Gj7RJvYZiNmx X-Gm-Message-State: AOJu0YyV2uxc9jEnWqKHBBns07NOf6DDcr3mb5PgxujUjj4m3IKSNhO/ YMEUC02/860qW4CEF3k4hCaG5UaT2lKy0wM5yqBpujZNg1M1qhwrZ88lOP/DV9Q= X-Google-Smtp-Source: AGHT+IHZPDBP/2G+iM8crT7CqzDpqiOTqjkerYD9t+xoHL3b/RsYHVFEDdIehn61CCgVDhqj+ckVNw== X-Received: by 2002:a05:651c:b2a:b0:2ea:d142:d2b2 with SMTP id 38308e7fff4ca-2ead142d3d6mr1982801fa.34.1717618229093; Wed, 05 Jun 2024 13:10:29 -0700 (PDT) Received: from [127.0.1.1] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a31be4e36sm9717473a12.53.2024.06.05.13.10.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 13:10:28 -0700 (PDT) From: Konrad Dybcio Date: Wed, 05 Jun 2024 22:10:17 +0200 Subject: [PATCH v2 4/7] drm/msm/adreno: Add speedbin data for SM8550 / A740 MIME-Version: 1.0 Message-Id: <20240605-topic-smem_speedbin-v2-4-8989d7e3d176@linaro.org> References: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> In-Reply-To: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.14-dev X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add speebin data for A740, as found on SM8550 and derivative SoCs. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 901ef767e491..e00eef8099ae 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -570,6 +570,10 @@ static const struct adreno_info gpulist[] = { .zapfw = "a740_zap.mdt", .hwcg = a740_hwcg, .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + { ADRENO_SKU_ID(SOCINFO_FC_AC), 0 }, + { ADRENO_SKU_ID(SOCINFO_FC_AF), 0 }, + ), }, { .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ .family = ADRENO_7XX_GEN3, From patchwork Wed Jun 5 20:10:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13687425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0CFEEC27C52 for ; Wed, 5 Jun 2024 20:10:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 26D5F10E811; Wed, 5 Jun 2024 20:10:40 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Ovv+zy1F"; dkim-atps=neutral Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) by gabe.freedesktop.org (Postfix) with ESMTPS id 91F9810E807 for ; Wed, 5 Jun 2024 20:10:32 +0000 (UTC) Received: by mail-lf1-f50.google.com with SMTP id 2adb3069b0e04-52b8b7b8698so339414e87.1 for ; Wed, 05 Jun 2024 13:10:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717618230; x=1718223030; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vAbdSxwRmKncrPynMCBXXpukCSmqzvxbpgxPB115kMQ=; b=Ovv+zy1FYJF2lxAACTGcmqD1yH33u54BeKb4BTfiP+0/7om9EcImpvBeOAd9R8dOq0 8M2gEypx3i36B/9u3QpQZJ7qH1p1YwaUxz8FWBCB65LXNEJDE3q7Hom1PVmyliCegf7G +ZMXWaYoPKIszR681xMTLC/0L1xcnfALvEY73bDqekdMU2uiFncCi30aFdYtdNTZnC+n qxcOP/6PwffDYXCEPhjl/Kcw16fD4U4/pxzg6gPEOcFPOfGmysCtFGKhB9i+x6KC+Xx6 u9fAH1+yYmz4XubQKR3keqNkj0rW1qEdNswV6fmMxtAQKWS2QPnYDKBu62E5dCVmZtIX fs2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717618230; x=1718223030; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vAbdSxwRmKncrPynMCBXXpukCSmqzvxbpgxPB115kMQ=; b=FUdgJEE/RCH6P7w7pgcqNy8uoE2Fr0MYmvzEhkUhzqyy8vZ726jwedvRTah2XYMUD4 iPL9xl4H3TWcW/OQiJD1rp9qYD6W/UMrK3XzpyIrzjFcapth+MM04tceKFay12ptkGX7 HHNhOCC2UOOpsww3uX5yC/yCGsTm37RZcT2+5+FoTNh8ReQ7gCmEPC6D4lwPWEGmpMNi gm5V2UFBtgSTiWuMmZn+KlintbqFYffkfUernUPtd/LioFBRaAYkMGFy63ulLzzEpoHt WnUJgodvXAQppwlVJU9Mg+bkHJWNdY8GtiSvO3yLI2Vtaa3SNkkvM/7yE21BumAaCX6Q cvCQ== X-Forwarded-Encrypted: i=1; AJvYcCVOKeeXezNVNkGFx8TDQVMZaFF08AH6N2/ZnvBkHCum2D546zVOm7rJ3C9sHf3TT1Ze58YgHK65tGipPyTeuK3zSgAF8NjndMJ0WJ/xqdHZ X-Gm-Message-State: AOJu0YxB33sHMVl69lxaFf/4UVBFwF603VmazVDd8lbUQRxPNd3prCRP bNlS59zh7Q6WmUcwvs0lkzcSxbYWdSpVoVBXDxT14nSk3PGQHJXg5o3YjIB4okqFbTIA2E+Mmz5 FHZ8= X-Google-Smtp-Source: AGHT+IGmE9OokaTql4LLWxH8WUk7Bm6os+aJLAvG1X8lHm2C2s5wY34QXKPicExRZInMxGNV/wgPkA== X-Received: by 2002:ac2:5322:0:b0:522:80d:5dc5 with SMTP id 2adb3069b0e04-52bab4bd036mr2102755e87.27.1717618230691; Wed, 05 Jun 2024 13:10:30 -0700 (PDT) Received: from [127.0.1.1] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a31be4e36sm9717473a12.53.2024.06.05.13.10.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 13:10:30 -0700 (PDT) From: Konrad Dybcio Date: Wed, 05 Jun 2024 22:10:18 +0200 Subject: [PATCH v2 5/7] drm/msm/adreno: Define A530 speed bins explicitly MIME-Version: 1.0 Message-Id: <20240605-topic-smem_speedbin-v2-5-8989d7e3d176@linaro.org> References: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> In-Reply-To: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.14-dev X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In preparation for commonizing the speedbin handling code. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_device.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index e00eef8099ae..66f7868ff476 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -258,6 +258,12 @@ static const struct adreno_info gpulist[] = { ADRENO_QUIRK_FAULT_DETECT_MASK, .init = a5xx_gpu_init, .zapfw = "a530_zap.mdt", + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + { 2, 2 }, + { 3, 3 }, + ), }, { .chip_ids = ADRENO_CHIP_IDS(0x05040001), .family = ADRENO_5XX, From patchwork Wed Jun 5 20:10:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13687426 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47D43C27C55 for ; Wed, 5 Jun 2024 20:10:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 08FE810E815; Wed, 5 Jun 2024 20:10:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ITs5z3C5"; dkim-atps=neutral Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2560C10E80F for ; Wed, 5 Jun 2024 20:10:34 +0000 (UTC) Received: by mail-lj1-f172.google.com with SMTP id 38308e7fff4ca-2ea9386cde0so2364341fa.2 for ; Wed, 05 Jun 2024 13:10:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717618232; x=1718223032; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=oK9nE6TjsLWeKUxIQ1Zr5Vx3uwM6i2437SAG5zcYC9A=; b=ITs5z3C5X7O+AdeUg9PAZBzXycBrupUJlnrJIpkdy3A5EjtP5NxFpfdhs95AgRQAOz TpHd82oTPKcScMD8Q0vI8PT+guQY7Xp3peIsfBLx/zXMvb9ZmrTJuAxzeiqJmPN4bHhl Mf5nluNWOQsoBK0uXd2flxX83lYQ6+a3IKC0aJiaUbmDEcpf33IUD110IcduahTKFdh8 qCV9wmE9DC6pmn1ne5NkoQE8QuvCWfbYcD0eJCPq/212aK+AqJTy3bo0+A2BmFrAYuDx EVrZaoiFrlkKJ6yHjFrUzjPw16OWAAXiWx6ObUb0bD/DEZlmaSy2z7xkmjnw2bFg6Gtu 6Bqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717618232; x=1718223032; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oK9nE6TjsLWeKUxIQ1Zr5Vx3uwM6i2437SAG5zcYC9A=; b=BxG1h/wFph3z2JfOT6rZqP7NpOwwoNmF+IqlN2vP+2NwH1RkKcZ+Cl5/H00IFeteDg 0qKZvcjP3ci5Mi7poatCwuRDODsA3rrsyp9fDOZ8yoqZyTFOeYfiPLBXwGKVL/N8aiqT UnUc4lIywGbc5D39qYDD/LUIhBnI4qHsVlwZT+JA6citPP5R5gXVBQUjkO1hKwstuTSZ 0yR8C9HHSVCXr52b+pG+WbKFC5v46dav9nT5mdItxki/JdEeao9imHz1DF6hm9ItWXZB kMg/45h3Ywrz+og9dge9t79bDrIOeY/UNS5wpQdNt1aImPhtyx3iQPLRTcVRTbFeO1Vg CvKA== X-Forwarded-Encrypted: i=1; AJvYcCVIH2L/t6anhB5DaqLkhunCrabv2gsbUuHbnkZvCSYtzSDfQwlNtR/ezOmwxIicEDpE6onV5Uihk1sCyLHVxerAQxHh+r9jq7xLKiIkJHHJ X-Gm-Message-State: AOJu0YxvLFT3hatipnOqD25eLJ27jUJuYwslOzSyFjYH32EuuickKFEx o7wmE/wTvKIACDcNIm56rw02BQzC5ixudWRYJy7QLuhi6WNKe93LqiNTsqx6jIk= X-Google-Smtp-Source: AGHT+IHIJnv5expD62cIeLSgdkL+o4v02vMiaIVkqDuv9Nd7/I1vQ38SX5m6e6wv9ZmQwahHa3gnAg== X-Received: by 2002:a2e:9305:0:b0:2e9:8497:46ce with SMTP id 38308e7fff4ca-2eac7a71477mr20870721fa.46.1717618232370; Wed, 05 Jun 2024 13:10:32 -0700 (PDT) Received: from [127.0.1.1] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a31be4e36sm9717473a12.53.2024.06.05.13.10.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 13:10:32 -0700 (PDT) From: Konrad Dybcio Date: Wed, 05 Jun 2024 22:10:19 +0200 Subject: [PATCH v2 6/7] drm/msm/adreno: Redo the speedbin assignment MIME-Version: 1.0 Message-Id: <20240605-topic-smem_speedbin-v2-6-8989d7e3d176@linaro.org> References: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> In-Reply-To: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.14-dev X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" There is no need to reinvent the wheel for simple read-match-set logic. Make speedbin discovery and assignment generation independent. This implicitly removes the bogus 0x80 / BIT(7) speed bin on A5xx, which has no representation in hardware whatshowever. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 34 -------------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56 --------------------------------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 51 ++++++++++++++++++++++++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 -- 4 files changed, 45 insertions(+), 99 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index c003f970189b..eed6a2eb1731 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1704,38 +1704,6 @@ static const struct adreno_gpu_funcs funcs = { .get_timestamp = a5xx_get_timestamp, }; -static void check_speed_bin(struct device *dev) -{ - struct nvmem_cell *cell; - u32 val; - - /* - * If the OPP table specifies a opp-supported-hw property then we have - * to set something with dev_pm_opp_set_supported_hw() or the table - * doesn't get populated so pick an arbitrary value that should - * ensure the default frequencies are selected but not conflict with any - * actual bins - */ - val = 0x80; - - cell = nvmem_cell_get(dev, "speed_bin"); - - if (!IS_ERR(cell)) { - void *buf = nvmem_cell_read(cell, NULL); - - if (!IS_ERR(buf)) { - u8 bin = *((u8 *) buf); - - val = (1 << bin); - kfree(buf); - } - - nvmem_cell_put(cell); - } - - devm_pm_opp_set_supported_hw(dev, &val, 1); -} - struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv = dev->dev_private; @@ -1763,8 +1731,6 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) a5xx_gpu->lm_leakage = 0x4E001A; - check_speed_bin(&pdev->dev); - nr_rings = 4; if (config->info->revn == 510) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 3f84417ff027..d256e27ee581 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2882,55 +2882,6 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return progress; } -static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) -{ - if (!info->speedbins) - return UINT_MAX; - - for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) - if (info->speedbins[i].fuse == fuse) - return BIT(info->speedbins[i].speedbin); - - return UINT_MAX; -} - -static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, - struct device *dev, - const struct adreno_info *info) -{ - u32 supp_hw; - u32 speedbin; - int ret; - - ret = adreno_read_speedbin(adreno_gpu, dev, &speedbin); - /* - * -ENOENT means that the platform doesn't support speedbin which is - * fine - */ - if (ret == -ENOENT) { - return 0; - } else if (ret) { - dev_err_probe(dev, ret, - "failed to read speed-bin. Some OPPs may not be supported by hardware\n"); - return ret; - } - - supp_hw = fuse_to_supp_hw(info, speedbin); - - if (supp_hw == UINT_MAX) { - DRM_DEV_ERROR(dev, - "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", - speedbin); - supp_hw = BIT(0); /* Default */ - } - - ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); - if (ret) - return ret; - - return 0; -} - static const struct adreno_gpu_funcs funcs = { .base = { .get_param = adreno_get_param, @@ -3062,13 +3013,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); - ret = a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); - if (ret) { - a6xx_llc_slices_destroy(a6xx_gpu); - kfree(a6xx_gpu); - return ERR_PTR(ret); - } - if (is_a7xx) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); else if (adreno_has_gmu_wrapper(adreno_gpu)) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 055072260b3d..8b2bc5f147e8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1060,8 +1060,8 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) adreno_ocmem->hdl); } -int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, - struct device *dev, u32 *fuse) +static int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *fuse) { u32 fcode; int ret; @@ -1095,6 +1095,46 @@ int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, return 0; } +#define ADRENO_SPEEDBIN_FUSE_NODATA 0xFFFF /* Made-up large value, expected by mesa */ +static int adreno_set_speedbin(struct adreno_gpu *adreno_gpu, struct device *dev) +{ + const struct adreno_info *info = adreno_gpu->info; + u32 fuse = ADRENO_SPEEDBIN_FUSE_NODATA; + u32 supp_hw = UINT_MAX; + int ret; + + /* No speedbins defined for this GPU SKU => allow all defined OPPs */ + if (!info->speedbins) { + adreno_gpu->speedbin = ADRENO_SPEEDBIN_FUSE_NODATA; + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + + /* + * If a real error (not counting older devicetrees having no nvmem references) + * occurs when trying to get the fuse value, bail out. + */ + ret = adreno_read_speedbin(adreno_gpu, dev, &fuse); + if (ret) { + return ret; + } else if (fuse == ADRENO_SPEEDBIN_FUSE_NODATA) { + /* The info struct has speedbin data, but the DT is too old => allow all OPPs */ + DRM_DEV_INFO(dev, "No GPU speed bin fuse, please update your device tree\n"); + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + + adreno_gpu->speedbin = fuse; + + /* Traverse the known speedbins */ + for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) { + if (info->speedbins[i].fuse == fuse) { + supp_hw = BIT(info->speedbins[i].speedbin); + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + } + + return dev_err_probe(dev, -EINVAL, "Unknown speed bin fuse value: 0x%x\n", fuse); +} + int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs, int nr_rings) @@ -1104,7 +1144,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu_config adreno_gpu_config = { 0 }; struct msm_gpu *gpu = &adreno_gpu->base; const char *gpu_name; - u32 speedbin; int ret; adreno_gpu->funcs = funcs; @@ -1131,9 +1170,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) - speedbin = 0xffff; - adreno_gpu->speedbin = speedbin; + ret = adreno_set_speedbin(adreno_gpu, dev); + if (ret) + return ret; gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 8f2b70eaf6ad..30e8b9919adb 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -524,9 +524,6 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); -int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, - struct device *dev, u32 *speedbin); - /* * For a5xx and a6xx targets load the zap shader that is used to pull the GPU * out of secure mode From patchwork Wed Jun 5 20:10:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13687427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74030C25B76 for ; Wed, 5 Jun 2024 20:10:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B38A910E818; Wed, 5 Jun 2024 20:10:43 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="XSOerStk"; dkim-atps=neutral Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) by gabe.freedesktop.org (Postfix) with ESMTPS id D67FF10E809 for ; Wed, 5 Jun 2024 20:10:35 +0000 (UTC) Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-a68a288b8a4so11732666b.2 for ; Wed, 05 Jun 2024 13:10:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717618234; x=1718223034; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2zhSqnuAi2a4A8OlqdMxl1Xx25B3ZvBd8bPE6idYqUw=; b=XSOerStkuAfQIP9SMTQd4yF/4408IMV2i7HFOCoH21L//rxma7DycfoKY4yNPh0gwx XbpeD2fOS1wFlsVOeYJIKCbUqvTh5JBFmvnubdOKTlGAACU7L+qz2TcKn0XPl1ZV5dnU nvyQWgIA1v0Ncz/PPgMFQoQUXFrFal2mUrKUiucxxZDebkYOVD3Agzar2xuWAbjdgbuK +Tbqw+0HxnQQ1jg9G2CJPTFspAEhLnPN/BoQ4VARnCNsM6JroYRcR4EdZT3r1DMDgQYS Vhh/GfFafny2gjSUP/AlX5rgiiXsgnWCiP1p0QIjFU/s896ZuHHHBSEZvYiQX8i44FkW ATnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717618234; x=1718223034; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2zhSqnuAi2a4A8OlqdMxl1Xx25B3ZvBd8bPE6idYqUw=; b=fOHUyChDExWAo/013EdUI4cPgzOexgHifThmhn/xcuLZphjy2BoB/Le9DeHNjNo7UI X+xh42ORuA++qOPFzNCEswN1j5/b7y8BhrU3azo2RED/V1DBa0s/6szW6svwC7aHAuP4 LbaMk9Xu4gKqfIcGlH0Jm4pqJX7CTIWxmZl8X5JHWtsxzCKEYTgE0qKjVY2M+SEUhmsA 25ho96nl4QuTNpOCTddBMfTBqLjo0sSamBEmpJ81O0davpvEUuqHOuWVnp5HdBzNu0UU 3NPW9FMsFHdI3TeoLFnP6vCQJxRW44w8/e0IflBr157nnAoiBepi5JTiyQ57807OptiC c69Q== X-Forwarded-Encrypted: i=1; AJvYcCVH+lCjhxxZHW5bvXVMziQqCIbcEQ4Jc6Ua/K6p3zUpbI5rRrENC34mG5uBnsvoYWMPHQZSFULm8IOfT3nkOjW9fQcmoi16jg8Tv5jRFcIQ X-Gm-Message-State: AOJu0Yy7Xg9gKtw/rJQcDdTSxfYSb2LJPPCgwb74w1b1VKKuEkmB4fe3 fASNrgW96PFxzR7qziuOA4b9G4MfCrWJ2VX+xyZcvs3CwDKNIB2/d1+bOD23REg= X-Google-Smtp-Source: AGHT+IFDsc8B06V+5iEYvzet3jVlB0i+L5L9Nrt/H40mqNDBPty8TYTHLtrCt5rS5peLfSWm/ftVxA== X-Received: by 2002:a50:9f2b:0:b0:578:881e:7b77 with SMTP id 4fb4d7f45d1cf-57a8bc9c0aamr3181953a12.34.1717618233978; Wed, 05 Jun 2024 13:10:33 -0700 (PDT) Received: from [127.0.1.1] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a31be4e36sm9717473a12.53.2024.06.05.13.10.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 13:10:33 -0700 (PDT) From: Konrad Dybcio Date: Wed, 05 Jun 2024 22:10:20 +0200 Subject: [PATCH v2 7/7] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs MIME-Version: 1.0 Message-Id: <20240605-topic-smem_speedbin-v2-7-8989d7e3d176@linaro.org> References: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> In-Reply-To: <20240605-topic-smem_speedbin-v2-0-8989d7e3d176@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.14-dev X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the speedbin masks to ensure only the desired OPPs are available on chips of a given bin. Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index c55a818af935..5f5ddfe205b0 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2119,48 +2119,67 @@ zap-shader { memory-region = <&gpu_micro_code_mem>; }; - /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; + opp-719000000 { + opp-hz = /bits/ 64 <719000000>; + opp-level = ; + opp-supported-hw = <0x1>; + }; + opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-615000000 { opp-hz = /bits/ 64 <615000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-475000000 { opp-hz = /bits/ 64 <475000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-401000000 { opp-hz = /bits/ 64 <401000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-295000000 { opp-hz = /bits/ 64 <295000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-220000000 { opp-hz = /bits/ 64 <220000000>; opp-level = ; + opp-supported-hw = <0x3>; + }; + + opp-124800000 { + opp-hz = /bits/ 64 <124800000>; + opp-level = ; + opp-supported-hw = <0x3>; }; }; };