From patchwork Thu Jun 6 13:36:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13688516 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3B606C25B75 for ; Thu, 6 Jun 2024 13:37:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nd5oHS99x0xxKSNnDBqwfWwdY5sH6Zfq9tvh6q+wleE=; b=kqgqmgTiFQQGP4 DCLSlQjnZmHztiNENpHCpTU6fXGRI0Az7AxX2VgdTgW/NsVPCbwQHDOYSk8dpTrvYW1n0ZHrT10CI M21KiSPmfrZGKYs3bHK2beuYGxAYr12eBz++5ZWwbKhn7BWkaujvCamC0xL0vxtlplxig1/yx9qay cXpGQ1oJT6VVHydgKoWiOXhAVbQ6Y5Q5Xa6NYrpkkCtfUhpeENTvwViAg2f/V6Y72bLCY4ZU4/tU7 xVx5vaPYzhh/7f23hlssDFVGH/TdS6y/2YNll/8ZJqu0KXOA/fxASRqYdT1YM6DQk9Xh8kAkzcsZp kvWe7C1iQ9ibOS0NYS+A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFDIQ-00000009vYX-0ZA6; Thu, 06 Jun 2024 13:36:50 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFDIJ-00000009vSr-27re for linux-arm-kernel@lists.infradead.org; Thu, 06 Jun 2024 13:36:45 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 70D08339; Thu, 6 Jun 2024 06:37:04 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A0A8A3F792; Thu, 6 Jun 2024 06:36:39 -0700 (PDT) From: Luca Fancellu To: linux-arm-kernel@lists.infradead.org Cc: diego.sueiro@arm.com Subject: [boot-wrapper 1/7] aarch64: Rename labels and prepare for lower EL booting Date: Thu, 6 Jun 2024 14:36:22 +0100 Message-Id: <20240606133628.3330423-2-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606133628.3330423-1-luca.fancellu@arm.com> References: <20240606133628.3330423-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240606_063643_627572_1F11DA2C X-CRM114-Status: UNSURE ( 8.81 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The current code can boot from a lower EL than EL3, but the flag 'flag_no_el3' have the meaning of "Don't drop to a lower EL", so rename the flag to flag_keep_el. This is a preparation work to boot on Armv8-R AArch64 which has no EL3. Signed-off-by: Luca Fancellu Reviewed-by: Andre Przywara --- arch/aarch64/boot.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index da5fa6548b65..7727475925c1 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -92,7 +92,7 @@ reset_no_el3: bl setup_stack mov w0, #1 - ldr x1, =flag_no_el3 + ldr x1, =flag_keep_el str w0, [x1] bl cpu_init_bootwrapper @@ -124,7 +124,7 @@ ASM_FUNC(jump_kernel) bl find_logical_id bl setup_stack // Reset stack pointer - ldr w0, flag_no_el3 + ldr w0, flag_keep_el cmp w0, #0 // Prepare Z flag mov x0, x20 @@ -133,7 +133,7 @@ ASM_FUNC(jump_kernel) mov x3, x23 b.eq 1f - br x19 // No EL3 + br x19 // Keep EL 1: mov x4, #SPSR_KERNEL @@ -151,5 +151,5 @@ ASM_FUNC(jump_kernel) .data .align 3 -flag_no_el3: +flag_keep_el: .long 0 From patchwork Thu Jun 6 13:36:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13688515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE717C25B75 for ; Thu, 6 Jun 2024 13:36:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=t/w+uroKNev7wvCJh+l058pGAhW98Hu7LWc8jFm5xz4=; b=Zke2mSUD+VHeaz TM3HUWAhP8rvAmWXHm0EmoCPwQQewJyleux+5CrwBa/IXvlrhGKIuZONLjGSjkplY6of0t5B+AdJM 11OztbGqBZso/o40JEaqWWDxRqaybpTcAbYJ3h8EOIUueIX5/NN6KBndHgcP6fP5+HkBLQ9QCQFrr 1XaFCRN2UrO33/cF+IW691yFAXxQhUOvPlpuBOj3HBFw4mAyTPNDJrW+526aCNFTxDeQ4T3766GIH S2a+KD9AjL6TR3I/VRHV+dfEOA2ra2dfU01XkbCLSMyEwZSYP5s1wYlzhcP+ayF8EVBQk3v27kQFF jfOUE3s1Cmp3qrY3C3vw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFDIM-00000009vWV-0tCb; Thu, 06 Jun 2024 13:36:46 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFDIJ-00000009vSv-25FR for linux-arm-kernel@lists.infradead.org; Thu, 06 Jun 2024 13:36:44 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 19CEBDA7; Thu, 6 Jun 2024 06:37:05 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 49C173F792; Thu, 6 Jun 2024 06:36:40 -0700 (PDT) From: Luca Fancellu To: linux-arm-kernel@lists.infradead.org Cc: diego.sueiro@arm.com Subject: [boot-wrapper 2/7] aarch64: Prepare for lower EL booting Date: Thu, 6 Jun 2024 14:36:23 +0100 Message-Id: <20240606133628.3330423-3-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606133628.3330423-1-luca.fancellu@arm.com> References: <20240606133628.3330423-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240606_063643_623158_3F6047BB X-CRM114-Status: UNSURE ( 9.98 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Store the value of the initial SPSR into a variable during EL3 initialization and load it from the variable before dropping EL, this is done as preparation work to be able to boot from a different exception level. Signed-off-by: Luca Fancellu Reviewed-by: Andre Przywara --- arch/aarch64/boot.S | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 7727475925c1..211077af17c8 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -51,6 +51,10 @@ reset_at_el3: b.eq err_invalid_id bl setup_stack + mov w0, #SPSR_KERNEL + ldr x1, =spsr_to_elx + str w0, [x1] + bl cpu_init_bootwrapper bl cpu_init_el3 @@ -135,7 +139,7 @@ ASM_FUNC(jump_kernel) b.eq 1f br x19 // Keep EL -1: mov x4, #SPSR_KERNEL +1: ldr w4, spsr_to_elx /* * If bit 0 of the kernel address is set, we're entering in AArch32 @@ -153,3 +157,5 @@ ASM_FUNC(jump_kernel) .align 3 flag_keep_el: .long 0 +spsr_to_elx: + .long 0 From patchwork Thu Jun 6 13:36:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13688519 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60269C27C5F for ; Thu, 6 Jun 2024 13:37:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OI1RJycisca69YMiyLY77JG3QMB1QBfGJOB+K/pfhSE=; b=WEqc31FDXy9Ivx rBOsRuPD01LRHdtBYHKPt/mYR4sE8zW59FhlPEYVngYhvmEosY/lwCJ0hdHOOAsI7nkXJQlF4a/jl 3t33bShUi/815340/kRtXystRIfKyrWvW46DzMs0U5Lb1+guwWaUsPUYD3Em/JybwNUrdYCngJ3t3 nuiSC/9qR97aq18xqS1lw1wzZE3IKVUOu5472/2smCLzqLjsrrcAbMp5HOPFBUw5B81AwCFeLWuhw OkKolKROsNdyTawt6sFQS3ZTuTZr/d+DTcfyNydIDkeIP0fgvbHq3PzTxb7ueiPD3eeocCA8fXg9i ztAwqOP6x/HL5yVKnbfw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFDIQ-00000009vYp-3DLL; Thu, 06 Jun 2024 13:36:50 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFDIK-00000009vT4-0XqM for linux-arm-kernel@lists.infradead.org; Thu, 06 Jun 2024 13:36:45 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B712A1042; Thu, 6 Jun 2024 06:37:05 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E72093F792; Thu, 6 Jun 2024 06:36:40 -0700 (PDT) From: Luca Fancellu To: linux-arm-kernel@lists.infradead.org Cc: diego.sueiro@arm.com Subject: [boot-wrapper 3/7] aarch64: Remove TSCXT bit set from SCTLR_EL2_RESET Date: Thu, 6 Jun 2024 14:36:24 +0100 Message-Id: <20240606133628.3330423-4-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606133628.3330423-1-luca.fancellu@arm.com> References: <20240606133628.3330423-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240606_063644_291213_A8185155 X-CRM114-Status: GOOD ( 11.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From the specification SCTLR_EL2.TSCXT is RES1 only "When FEAT_CSV2_2 is not implemented, FEAT_CSV2_1p2 is not implemented, HCR_EL2.E2H == 1 and HCR_EL2.TGE == 1", so given that HCR_EL2.E2H is set by bootwrapper before to a value of zero, the condition above can't happen and from the specification the bit is RES0. Fix the macro removing the bit. Signed-off-by: Luca Fancellu Reviewed-by: Andre Przywara --- arch/aarch64/include/asm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 124ef916ddfc..846b89f8405d 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -30,8 +30,8 @@ BIT(11) | BIT(5) | BIT(4)) #define SCTLR_EL2_RES1 \ - (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(18) | \ - BIT(16) | BIT(11) | BIT(5) | BIT(4)) + (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(18) | BIT(16) | \ + BIT(11) | BIT(5) | BIT(4)) #define SCTLR_EL1_RES1 \ (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(11) | \ From patchwork Thu Jun 6 13:36:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13688517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BA2EC27C54 for ; Thu, 6 Jun 2024 13:37:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Yb7Ys4CjObM48K7PgalQmGiWoBNB6bUMDA38N9Ja7V4=; b=BmY3Z1K1jb8bgR jOzt0WsyPLCIwJnhIJolnC7ZiKJxpfE46Fjcok895M65yojItq7JND7dzBXu86BXxmSnVkNwZ8XQ+ 5C8QoH4TKdSq0/fqQ9hssnMTco59NvbMuJ3sC7ls1/1cxpRpngQUx5SAvHnbCYrVtKNaTW4usIOa6 e+/vP0mguFvUGbsfT/MdoRd4f01Yrjyv2aovyPJwBTaXE7zo72F5WV4GYNXzVHUNZ647wYLeE1sN4 WYEI7NytuwPGfKVuLUlpeG2ZsZzK5+r0xzY9M3N/lsTa1jkX4DWmo9XGntfBqr5mx2KhGCNYHj+Me uyUcz6oCshmUqTAhiYGg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFDIR-00000009vZB-28Ni; Thu, 06 Jun 2024 13:36:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFDIK-00000009vTM-1qWU for linux-arm-kernel@lists.infradead.org; Thu, 06 Jun 2024 13:36:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 605E71576; Thu, 6 Jun 2024 06:37:06 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 904C63F792; Thu, 6 Jun 2024 06:36:41 -0700 (PDT) From: Luca Fancellu To: linux-arm-kernel@lists.infradead.org Cc: diego.sueiro@arm.com Subject: [boot-wrapper 4/7] gic-v3: Prepare for gicv3 with EL2 Date: Thu, 6 Jun 2024 14:36:25 +0100 Message-Id: <20240606133628.3330423-5-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606133628.3330423-1-luca.fancellu@arm.com> References: <20240606133628.3330423-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240606_063644_596295_AAE31050 X-CRM114-Status: GOOD ( 11.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is a preparation for allowing boot-wrapper configuring the gicv3 with EL2. When supporting boot at EL2 for Armv8-R, the architecture does not define ICC_CTLR_EL2. See [https://developer.arm.com/documentation/ihi0069/latest/]. As the caller, gic_secure_init expects the ICC_CTLR to be written, we change the function into gic_init_icc_ctlr(). In the GIC spec, the r/w bits in this register ([6:0]) either affect EL3 IRQ routing (not applicable since no EL3), non-secure IRQ handling (not applicable since only secure state in Armv8-R aarch64), or are aliased to ICC_CTLR_EL1 bits. So, based on this, the new gic_init_icc_ctlr() would be: When currentEL is EL3, init ICC_CTLR_EL3 as before. When currentEL is not EL3, init ICC_CTLR_EL1 with ICC_CTLR_EL1_RESET. Signed-off-by: Luca Fancellu Reviewed-by: Andre Przywara --- arch/aarch32/include/asm/gic-v3.h | 7 +++++++ arch/aarch64/include/asm/gic-v3.h | 20 +++++++++++++++++--- common/gic-v3.c | 2 +- 3 files changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h index b28136af7fe1..fdfbef859517 100644 --- a/arch/aarch32/include/asm/gic-v3.h +++ b/arch/aarch32/include/asm/gic-v3.h @@ -11,6 +11,8 @@ #include +#define ICC_CTLR_RESET (0UL) + static inline void gic_write_icc_sre(uint32_t val) { mcr(ICC_SRE, val); @@ -21,4 +23,9 @@ static inline void gic_write_icc_ctlr(uint32_t val) mcr(ICC_CTLR, val); } +static inline void gic_init_icc_ctlr() +{ + gic_write_icc_ctlr(ICC_CTLR_RESET); +} + #endif diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h index 24474807c6fe..aca7ab140ed5 100644 --- a/arch/aarch64/include/asm/gic-v3.h +++ b/arch/aarch64/include/asm/gic-v3.h @@ -11,14 +11,28 @@ #include +#define ICC_CTLR_EL3_RESET (0UL) +#define ICC_CTLR_EL1_RESET (0UL) + +static inline uint32_t current_el(void) +{ + return mrs(CurrentEL); +} + static inline void gic_write_icc_sre(uint32_t val) { - msr(ICC_SRE_EL3, val); + if (current_el() == CURRENTEL_EL3) + msr(ICC_SRE_EL3, val); + else + msr(ICC_SRE_EL2, val); } -static inline void gic_write_icc_ctlr(uint32_t val) +static inline void gic_init_icc_ctlr() { - msr(ICC_CTLR_EL3, val); + if (current_el() == CURRENTEL_EL3) + msr(ICC_CTLR_EL3, ICC_CTLR_EL3_RESET); + else + msr(ICC_CTLR_EL1, ICC_CTLR_EL1_RESET); } #endif diff --git a/common/gic-v3.c b/common/gic-v3.c index 6207007959bd..a0fe5642257e 100644 --- a/common/gic-v3.c +++ b/common/gic-v3.c @@ -117,6 +117,6 @@ void gic_secure_init(void) gic_write_icc_sre(ICC_SRE_Enable | ICC_SRE_DIB | ICC_SRE_DFB | ICC_SRE_SRE); isb(); - gic_write_icc_ctlr(0); + gic_init_icc_ctlr(); isb(); } From patchwork Thu Jun 6 13:36:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13688522 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C19F5C27C54 for ; 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Thu, 06 Jun 2024 13:36:55 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFDIL-00000009vW3-2tTp for linux-arm-kernel@lists.infradead.org; Thu, 06 Jun 2024 13:36:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0AE8A15A1; Thu, 6 Jun 2024 06:37:07 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 39A543F792; Thu, 6 Jun 2024 06:36:42 -0700 (PDT) From: Luca Fancellu To: linux-arm-kernel@lists.infradead.org Cc: diego.sueiro@arm.com Subject: [boot-wrapper 5/7] aarch64: Introduce EL2 boot code for Armv8-R AArch64 Date: Thu, 6 Jun 2024 14:36:26 +0100 Message-Id: <20240606133628.3330423-6-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606133628.3330423-1-luca.fancellu@arm.com> References: <20240606133628.3330423-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240606_063645_999970_A3FD4142 X-CRM114-Status: GOOD ( 18.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Armv8-R AArch64 profile does not support the EL3 exception level. The Armv8-R AArch64 profile allows for an (optional) VMSAv8-64 MMU at EL1, which allows to run off-the-shelf Linux. However EL2 only supports a PMSA, which is not supported by Linux, so we need to drop into EL1 before entering the kernel. We add a new err_invalid_arch symbol as a dead loop. If we detect the current Armv8-R aarch64 only supports with PMSA, meaning we cannot boot Linux anymore, then we jump to err_invalid_arch. During Armv8-R aarch64 init, to make sure nothing unexpected traps into EL2, we auto-detect and config FIEN and EnSCXT in HCR_EL2. The boot sequence is: If CurrentEL == EL3, then goto EL3 initialisation and drop to lower EL before entering the kernel. If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R aarch64), if id_aa64mmfr0_el1.MSA_frac == 0x2, then goto Armv8-R AArch64 initialisation and drop to EL1 before entering the kernel. else, which means VMSA unsupported and cannot boot Linux, goto err_invalid_arch (dead loop). Else, no initialisation and keep the current EL before entering the kernel. Signed-off-by: Luca Fancellu --- arch/aarch64/boot.S | 63 ++++++++++++++++++++++++++++++++-- arch/aarch64/include/asm/cpu.h | 10 ++++++ arch/aarch64/init.c | 24 +++++++++++++ 3 files changed, 94 insertions(+), 3 deletions(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 211077af17c8..b2b9863b8d6a 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -22,7 +22,8 @@ * EL2 must be implemented. * * - EL2 (Non-secure) - * Entering at EL2 is partially supported. + * Entering at EL2 is partially supported for Armv8-A. + * Entering at EL2 is supported for Armv8-R. * PSCI is not supported when entered in this exception level. */ ASM_FUNC(_start) @@ -76,7 +77,50 @@ reset_at_el2: msr sctlr_el2, x0 isb - b reset_no_el3 + /* Detect Armv8-R AArch64 */ + mrs x1, id_aa64mmfr0_el1 + /* + * Check MSA, bits [51:48]: + * 0xf means Armv8-R AArch64. + * If not 0xf, proceed in Armv8-A EL2. + */ + ubfx x0, x1, #48, #4 // MSA + cmp x0, 0xf + bne reset_no_el3 + + /* + * Armv8-R AArch64 is found, check if Linux can be booted. + * Check MSA_frac, bits [55:52]: + * 0x2 means EL1&0 translation regime also supports VMSAv8-64. + */ + ubfx x0, x1, #52, #4 // MSA_frac + cmp x0, 0x2 + /* + * If not 0x2, no VMSA, so cannot boot Linux and dead loop. + * Also, since the architecture guarantees that those CPUID + * fields never lose features when the value in a field + * increases, we use blt to cover it. + */ + blt err_invalid_arch + + /* Start Armv8-R Linux at EL1 */ + mov w0, #SPSR_KERNEL_EL1 + ldr x1, =spsr_to_elx + str w0, [x1] + + cpuid x0, x1 + bl find_logical_id + cmp x0, #MPIDR_INVALID + b.eq err_invalid_id + bl setup_stack + + bl cpu_init_bootwrapper + + bl cpu_init_armv8r_el2 + + bl gic_secure_init + + b start_bootmethod /* * EL1 initialization @@ -104,6 +148,7 @@ reset_no_el3: b start_bootmethod err_invalid_id: +err_invalid_arch: b . /* @@ -121,10 +166,14 @@ ASM_FUNC(jump_kernel) ldr x0, =SCTLR_EL1_KERNEL msr sctlr_el1, x0 + mrs x5, CurrentEL + cmp x5, #CURRENTEL_EL2 + b.eq 1f + ldr x0, =SCTLR_EL2_KERNEL msr sctlr_el2, x0 - cpuid x0, x1 +1: cpuid x0, x1 bl find_logical_id bl setup_stack // Reset stack pointer @@ -147,10 +196,18 @@ ASM_FUNC(jump_kernel) */ bfi x4, x19, #5, #1 + mrs x5, CurrentEL + cmp x5, #CURRENTEL_EL2 + b.eq 1f + msr elr_el3, x19 msr spsr_el3, x4 eret +1: msr elr_el2, x19 + msr spsr_el2, x4 + eret + .ltorg .data diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 846b89f8405d..6b2f5fbe4502 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -58,7 +58,13 @@ #define SCR_EL3_TCR2EN BIT(43) #define SCR_EL3_PIEN BIT(45) +#define VTCR_EL2_MSA BIT(31) + #define HCR_EL2_RES1 BIT(1) +#define HCR_EL2_APK_NOTRAP BIT(40) +#define HCR_EL2_API_NOTRAP BIT(41) +#define HCR_EL2_FIEN_NOTRAP BIT(47) +#define HCR_EL2_ENSCXT_NOTRAP BIT(53) #define ID_AA64DFR0_EL1_PMSVER BITS(35, 32) #define ID_AA64DFR0_EL1_TRACEBUFFER BITS(47, 44) @@ -88,7 +94,9 @@ #define ID_AA64PFR1_EL1_MTE BITS(11, 8) #define ID_AA64PFR1_EL1_SME BITS(27, 24) +#define ID_AA64PFR0_EL1_RAS BITS(31, 28) #define ID_AA64PFR0_EL1_SVE BITS(35, 32) +#define ID_AA64PFR0_EL1_CSV2 BITS(59, 56) #define ID_AA64SMFR0_EL1 s3_0_c0_c4_5 #define ID_AA64SMFR0_EL1_FA64 BIT(63) @@ -114,6 +122,7 @@ #define SPSR_I (1 << 7) /* IRQ masked */ #define SPSR_F (1 << 6) /* FIQ masked */ #define SPSR_T (1 << 5) /* Thumb */ +#define SPSR_EL1H (5 << 0) /* EL1 Handler mode */ #define SPSR_EL2H (9 << 0) /* EL2 Handler mode */ #define SPSR_HYP (0x1a << 0) /* M[3:0] = hyp, M[4] = AArch32 */ @@ -153,6 +162,7 @@ #else #define SCTLR_EL1_KERNEL SCTLR_EL1_RES1 #define SPSR_KERNEL (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H) +#define SPSR_KERNEL_EL1 (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL1H) #endif #ifndef __ASSEMBLY__ diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 37cb45fde446..8006f2705193 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -145,6 +145,30 @@ void cpu_init_el3(void) msr(CNTFRQ_EL0, COUNTER_FREQ); } +void cpu_init_armv8r_el2(void) +{ + unsigned long hcr = mrs(hcr_el2); + + msr(vpidr_el2, mrs(midr_el1)); + msr(vmpidr_el2, mrs(mpidr_el1)); + + /* VTCR_MSA: VMSAv8-64 support */ + msr(vtcr_el2, VTCR_EL2_MSA); + + if (mrs_field(ID_AA64PFR0_EL1, CSV2) <= 2) + hcr |= HCR_EL2_ENSCXT_NOTRAP; + + if (mrs_field(ID_AA64PFR0_EL1, RAS) <= 2) + hcr |= HCR_EL2_FIEN_NOTRAP; + + if (cpu_has_pauth()) + hcr |= HCR_EL2_APK_NOTRAP | HCR_EL2_API_NOTRAP; + + msr(hcr_el2, hcr); + isb(); + msr(CNTFRQ_EL0, COUNTER_FREQ); +} + #ifdef PSCI extern char psci_vectors[]; From patchwork Thu Jun 6 13:36:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13688520 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6792AC27C65 for ; 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Thu, 06 Jun 2024 13:36:52 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFDIL-00000009vVR-1J23 for linux-arm-kernel@lists.infradead.org; Thu, 06 Jun 2024 13:36:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A723D1596; Thu, 6 Jun 2024 06:37:07 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D71963F792; Thu, 6 Jun 2024 06:36:42 -0700 (PDT) From: Luca Fancellu To: linux-arm-kernel@lists.infradead.org Cc: diego.sueiro@arm.com Subject: [boot-wrapper 6/7] aarch64: Support PSCI for Armv8-R AArch64 Date: Thu, 6 Jun 2024 14:36:27 +0100 Message-Id: <20240606133628.3330423-7-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606133628.3330423-1-luca.fancellu@arm.com> References: <20240606133628.3330423-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240606_063645_483766_2922243F X-CRM114-Status: GOOD ( 12.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for PSCI when booting Linux on Armv8-R AArch64, allow the autoconf parameter --enable-psci to take an argument which is the conduit to be used, it can be empty or 'smc' to select the smc conduit, it can be 'hvc' for the hvc conduit. Depending on the selected conduit, the vector table will be installed on the VBAR_EL3 or VBAR_EL2 register. Signed-off-by: Luca Fancellu Reviewed-by: Andre Przywara --- Makefile.am | 5 ++++- arch/aarch64/init.c | 15 ++++++++++++--- configure.ac | 16 +++++++++++----- 3 files changed, 27 insertions(+), 9 deletions(-) diff --git a/Makefile.am b/Makefile.am index 6ebece25b230..34fbfb1f4ff8 100644 --- a/Makefile.am +++ b/Makefile.am @@ -49,11 +49,14 @@ endif if PSCI DEFINES += -DPSCI +if PSCI_HVC +DEFINES += -DPSCI_HVC +endif ARCH_OBJ += psci.o COMMON_OBJ += psci.o PSCI_NODE := psci { \ compatible = \"arm,psci\"; \ - method = \"smc\"; \ + method = \"$(PSCI_METHOD)\"; \ cpu_on = <$(PSCI_CPU_ON)>; \ cpu_off = <$(PSCI_CPU_OFF)>; \ }; diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 8006f2705193..3305e69270a4 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -174,10 +174,19 @@ extern char psci_vectors[]; bool cpu_init_psci_arch(void) { - if (mrs(CurrentEL) != CURRENTEL_EL3) + switch (mrs(CurrentEL)) { +#if !defined(PSCI_HVC) + case CURRENTEL_EL3: + msr(VBAR_EL3, (unsigned long)psci_vectors); + break; +#else + case CURRENTEL_EL2: + msr(VBAR_EL2, (unsigned long)psci_vectors); + break; +#endif + default: return false; - - msr(VBAR_EL3, (unsigned long)psci_vectors); + } isb(); return true; diff --git a/configure.ac b/configure.ac index 9e3b7226cd69..44459a4c849e 100644 --- a/configure.ac +++ b/configure.ac @@ -83,13 +83,19 @@ AS_IF([test "x$X_IMAGE" != "x"], # Allow a user to pass --enable-psci AC_ARG_ENABLE([psci], AS_HELP_STRING([--disable-psci], [disable the psci boot method]), - [USE_PSCI=$enableval], [USE_PSCI="yes"]) -AM_CONDITIONAL([PSCI], [test "x$USE_PSCI" = "xyes"]) -AS_IF([test "x$USE_PSCI" = "xyes"], [], [USE_PSCI=no]) - -AS_IF([test "x$USE_PSCI" != "xyes" -a "x$KERNEL_ES" = "x32"], + [case "${enableval}" in + yes|smc) USE_PSCI=smc ;; + hvc) USE_PSCI=hvc ;; + no) ;; + *) AC_MSG_ERROR([Bad value "${enableval}" for --enable-psci. Use "smc" or "hvc"]) ;; + esac]) +AM_CONDITIONAL([PSCI], [test "x$USE_PSCI" = "xyes" -o "x$USE_PSCI" = "xsmc" -o "x$USE_PSCI" = "xhvc"]) +AM_CONDITIONAL([PSCI_HVC], [test "x$USE_PSCI" = "xhvc"]) + +AS_IF([test "x$USE_PSCI" = "xno" -a "x$KERNEL_ES" = "x32"], [AC_MSG_ERROR([With an AArch32 kernel, boot method must be PSCI.])] ) +AC_SUBST([PSCI_METHOD], [$USE_PSCI]) # Allow a user to pass --with-initrd AC_ARG_WITH([initrd], From patchwork Thu Jun 6 13:36:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13688521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA239C25B75 for ; Thu, 6 Jun 2024 13:37:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OZbKRQszPDY4rm1V0oD7gTe2E8FExZ3CE4EHbC62E6U=; b=XY4oiOfagKsz1Q IjrekpwMN6h5qC08vBAyv0CLBhriuRXHJSrHOw4YcLLykurt1UqTCDojQsuKsSsyNuhxdzeJJ30l6 XaSxksdBqboR9ifCHxyEisyY0rMqhADapgdYEHVGRMMkTrvKnUNWUC3zBYJz90VqwYXtGZvRPd45G zKcO7Pi3pwUKvtu0CiXIj11Q9QuOmco6QxNmUXlBYV7dgw8vT/HBRSU7K2WW0hb68rOocDDqDuJMw xm7nvwWA3RwyrF+QuAlDg3TYNy+a+EvfnmAkW/vLpEDzbpbVbPO/Uc0a9td1jGlVHqxAzSN+EzGsr /qCzaYHN3UPyAVQqmEqg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFDIW-00000009vcp-1oRy; Thu, 06 Jun 2024 13:36:56 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFDIL-00000009vWa-4As5 for linux-arm-kernel@lists.infradead.org; Thu, 06 Jun 2024 13:36:48 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5060D15BF; Thu, 6 Jun 2024 06:37:08 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 804AB3F792; Thu, 6 Jun 2024 06:36:43 -0700 (PDT) From: Luca Fancellu To: linux-arm-kernel@lists.infradead.org Cc: diego.sueiro@arm.com Subject: [boot-wrapper 7/7] aarch64: Start Xen on Armv8-R at EL2 Date: Thu, 6 Jun 2024 14:36:28 +0100 Message-Id: <20240606133628.3330423-8-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606133628.3330423-1-luca.fancellu@arm.com> References: <20240606133628.3330423-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240606_063646_234692_5115FAC6 X-CRM114-Status: GOOD ( 11.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When bootwrapper is compiled with Xen support and it is started at EL2 on Armv8-R AArch64, keep the current EL and jump to the Xen image. Additionally, don't permit the usage of hvc conduit when Xen kernel is passed, because it's not supported. Signed-off-by: Luca Fancellu --- Makefile.am | 1 + arch/aarch64/boot.S | 7 +++++++ configure.ac | 3 +++ 3 files changed, 11 insertions(+) diff --git a/Makefile.am b/Makefile.am index 34fbfb1f4ff8..bafce34682c3 100644 --- a/Makefile.am +++ b/Makefile.am @@ -112,6 +112,7 @@ XEN_CHOSEN := xen,xen-bootargs = \"$(XEN_CMDLINE)\"; \ compatible = \"xen,linux-zimage\", \"xen,multiboot-module\"; \ reg = <0x0 $(DOM0_OFFSET) 0x0 $(KERNEL_SIZE)>; \ }; +DEFINES += -DXEN endif if INITRD diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index b2b9863b8d6a..0b30b82ad6d9 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -88,6 +88,7 @@ reset_at_el2: cmp x0, 0xf bne reset_no_el3 +#if !defined(XEN) /* * Armv8-R AArch64 is found, check if Linux can be booted. * Check MSA_frac, bits [55:52]: @@ -107,6 +108,12 @@ reset_at_el2: mov w0, #SPSR_KERNEL_EL1 ldr x1, =spsr_to_elx str w0, [x1] +#else + /* Start XEN on Armv8-R at EL2 */ + mov w0, #1 + ldr x1, =flag_keep_el + str w0, [x1] +#endif cpuid x0, x1 bl find_logical_id diff --git a/configure.ac b/configure.ac index 44459a4c849e..a5175db4148a 100644 --- a/configure.ac +++ b/configure.ac @@ -95,6 +95,9 @@ AM_CONDITIONAL([PSCI_HVC], [test "x$USE_PSCI" = "xhvc"]) AS_IF([test "x$USE_PSCI" = "xno" -a "x$KERNEL_ES" = "x32"], [AC_MSG_ERROR([With an AArch32 kernel, boot method must be PSCI.])] ) +AS_IF([test "x$USE_PSCI" = "xhvc" -a "x$X_IMAGE" != "x"], + [AC_MSG_ERROR([With Xen kernel, PSCI conduit must be smc.])] +) AC_SUBST([PSCI_METHOD], [$USE_PSCI]) # Allow a user to pass --with-initrd