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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703fd50bc86sm1150919b3a.175.2024.06.06.06.49.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 06:49:41 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Jim Shu , "Fea . Wang" , Frank Chang Subject: [PATCH v4 1/6] target/riscv: Reuse the conversion function of priv_spec Date: Thu, 6 Jun 2024 21:54:49 +0800 Message-Id: <20240606135454.119186-2-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606135454.119186-1-fea.wang@sifive.com> References: <20240606135454.119186-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=fea.wang@sifive.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Jim Shu Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 13 ++++--------- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 69a08e8c2c..fd0f09c468 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1790,7 +1790,7 @@ static int priv_spec_from_str(const char *priv_spec_str) return priv_version; } -static const char *priv_spec_to_str(int priv_version) +const char *priv_spec_to_str(int priv_version) { switch (priv_version) { case PRIV_VERSION_1_10_0: diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6fe0d712b4..b4c9e13774 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -830,4 +830,5 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); /* Implemented in th_csr.c */ void th_register_custom_csrs(RISCVCPU *cpu); +const char *priv_spec_to_str(int priv_version); #endif /* RISCV_CPU_H */ diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index fa8a17cc60..4c6141f947 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -76,16 +76,11 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, static const char *cpu_priv_ver_to_str(int priv_ver) { - switch (priv_ver) { - case PRIV_VERSION_1_10_0: - return "v1.10.0"; - case PRIV_VERSION_1_11_0: - return "v1.11.0"; - case PRIV_VERSION_1_12_0: - return "v1.12.0"; - } + const char *priv_spec_str = priv_spec_to_str(priv_ver); - g_assert_not_reached(); + g_assert(priv_spec_str); + + return priv_spec_str; } static void riscv_cpu_synchronize_from_tb(CPUState *cs, From patchwork Thu Jun 6 13:54:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Fea.Wang" X-Patchwork-Id: 13688534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 409BDC27C55 for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703fd50bc86sm1150919b3a.175.2024.06.06.06.49.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 06:49:45 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang Subject: [PATCH v4 2/6] target/riscv: Define macros and variables for ss1p13 Date: Thu, 6 Jun 2024 21:54:50 +0800 Message-Id: <20240606135454.119186-3-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606135454.119186-1-fea.wang@sifive.com> References: <20240606135454.119186-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=fea.wang@sifive.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add macros and variables for RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 4 +++- target/riscv/cpu_cfg.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b4c9e13774..90b8f1b08f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -96,12 +96,14 @@ extern RISCVCPUProfile *riscv_profiles[]; #define PRIV_VER_1_10_0_STR "v1.10.0" #define PRIV_VER_1_11_0_STR "v1.11.0" #define PRIV_VER_1_12_0_STR "v1.12.0" +#define PRIV_VER_1_13_0_STR "v1.13.0" enum { PRIV_VERSION_1_10_0 = 0, PRIV_VERSION_1_11_0, PRIV_VERSION_1_12_0, + PRIV_VERSION_1_13_0, - PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, + PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0, }; #define VEXT_VERSION_1_00_0 0x00010000 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index e1e4f32698..fb7eebde52 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -136,6 +136,7 @@ struct RISCVCPUConfig { * TCG always implement/can't be user disabled, * based on spec version. */ + bool has_priv_1_13; bool has_priv_1_12; bool has_priv_1_11; From patchwork Thu Jun 6 13:54:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Fea.Wang" X-Patchwork-Id: 13688533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 613B2C25B75 for ; Thu, 6 Jun 2024 13:51:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sFDV5-0000oi-0G; Thu, 06 Jun 2024 09:49:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sFDV2-0000nr-Po for qemu-devel@nongnu.org; Thu, 06 Jun 2024 09:49:52 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sFDV1-0008Tt-Ao for qemu-devel@nongnu.org; Thu, 06 Jun 2024 09:49:52 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-70255d5ddc7so847398b3a.3 for ; Thu, 06 Jun 2024 06:49:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717681790; x=1718286590; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L6wLMki1LmAn7oxGxrUEW0kbk4sc1N/F5qCG2xNjuRg=; b=JakJ3R2fn4Jsp4VfCVEX21ltqrYpOpc2XLWMwyu0x9uNCdEub6EUK3SVb0qt0013MW CH384ABka7Yta9Ode4Plvt8fjh3UHHTJt9WlEMYf93J/zu5982p21UclMUyBfexnxn/U R+OjFw4yPf2u77Y/MMWzNLa8RWr/946JdTWhSyfkqC7pRL8v5AJGSwSHe+GvXPv21xfG u1urc0Q2noEglVuXYI14cx8+l0kBTGJTOfqMVIs6COMpYlXfdCiTg/9ff9rOLjBwU5g+ 5n4xsgnPwodpZv8wRKyQrzDBZZTMOmtTjZ3Hwz7gvtM7kUdjc8nZhEsk4clwhA77OkuV qb5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717681790; x=1718286590; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L6wLMki1LmAn7oxGxrUEW0kbk4sc1N/F5qCG2xNjuRg=; b=F+fM6dduuMkJvrxZ3+k9pXUsSpEKlPZ673Afk6uwp0nJTqh1sJKOnWx1ISFNRhMJND GCAgM7ZO5olyvDTsRdWEVhOXLnIZ13CzTvD0UZiNshd9x2PLm/HTkhFqy3YmtZEvomhs iXvU9j1GBkF04zvnocE/BubYgM9suMkCB6g66w4RZW/Kun8mxio1w2fz7DcPNMMijm+3 7yEYv3A0nvdVSYzq41EXpROtyh5QnsGGVEp3fc+Q1g79z+bmBYUjBV5ruyoyx9wY/G4A nCXZk3Z1I4n4tO00tGSd9LFmXDrBzkLmB1m1c72CEfSP7W4vanq55NXITLhfq4sglcYW AzVg== X-Gm-Message-State: AOJu0YxzT3Lto+S1uAgzHZDYpj6BfUapo9zohV/hDOJ8cpb0GYAWR2fT gGzwno+U/OgzA+ww08XxGM4jjJZ8nkoF0kWyObVJJc4jeSotqiL1nUHX12IK1t/bL0pJ0iIGHGa lcIuj+Wxa/j5smOLXgfRwIbOvicMmnyPZZgME+2J39Cj8ulQJulOfiGKJ0sBc/BaPsp0mpcHcgG qzqSjetvTdI6XWYv0Ekydbx8+mVz0Z0wMwQGI= X-Google-Smtp-Source: AGHT+IHjmp64ORkua8NR/qN+Wy4JpmNP++CIZLQSFFwXZWRAAbrZ5Riz2KkLH3iHtXMMUSbZdepEVw== X-Received: by 2002:a05:6a20:3955:b0:1af:8a3a:35d7 with SMTP id adf61e73a8af0-1b2b712dfabmr6446686637.39.1717681789270; Thu, 06 Jun 2024 06:49:49 -0700 (PDT) Received: from hsinchu36-syssw02.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703fd50bc86sm1150919b3a.175.2024.06.06.06.49.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 06:49:48 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang Subject: [PATCH v4 3/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0 Date: Thu, 6 Jun 2024 21:54:51 +0800 Message-Id: <20240606135454.119186-4-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606135454.119186-1-fea.wang@sifive.com> References: <20240606135454.119186-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=fea.wang@sifive.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in mstateen0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a470fda9be..c895aa0334 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -315,6 +315,7 @@ #define SMSTATEEN0_CS (1ULL << 0) #define SMSTATEEN0_FCSR (1ULL << 1) #define SMSTATEEN0_JVT (1ULL << 2) +#define SMSTATEEN0_P1P13 (1ULL << 56) #define SMSTATEEN0_HSCONTXT (1ULL << 57) #define SMSTATEEN0_IMSIC (1ULL << 58) #define SMSTATEEN0_AIA (1ULL << 59) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ee33019b03..a19e1afa1f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2252,6 +2252,10 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, wr_mask |= SMSTATEEN0_FCSR; } + if (env->priv_ver >= PRIV_VERSION_1_13_0) { + wr_mask |= SMSTATEEN0_P1P13; + } + return write_mstateen(env, csrno, wr_mask, new_val); } @@ -2287,6 +2291,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (env->priv_ver >= PRIV_VERSION_1_13_0) { + wr_mask |= SMSTATEEN0_P1P13; + } + return write_mstateenh(env, csrno, wr_mask, new_val); } From patchwork Thu Jun 6 13:54:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Fea.Wang" X-Patchwork-Id: 13688529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D9BBAC27C5F for ; Thu, 6 Jun 2024 13:50:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sFDV7-0000qE-Ti; Thu, 06 Jun 2024 09:49:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sFDV6-0000pA-Ox for qemu-devel@nongnu.org; Thu, 06 Jun 2024 09:49:56 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sFDV4-0008UH-Ez for qemu-devel@nongnu.org; Thu, 06 Jun 2024 09:49:56 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-7023b6d810bso811942b3a.3 for ; Thu, 06 Jun 2024 06:49:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717681793; x=1718286593; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cEG1fPkJ+g/jXimIp5Gy6n7CLs83yHdB825jkzDzPOg=; b=ahTAZAZ8Vsy1cibU2EqGF9r9grVd1frTGBu2oHtowTum6mjrBpkRs/6FbzgjQQ4DiF jFSfF0I3aufsEVE3V/+bvtnzTi5rQkArWezH8SXMot0tTYVtjGD8pQPRD51zkW3hfs3K TAHqlQZBH0PGsVF8X867P4y1nGCvZhq7KsRhA+sKCbp2XtHmrsJ20LNq3edBRR37+djp vGNtimVtfF9jELL12xBvR6ztTVJM3MSVkja+/PV7V/OQS+y73jHfkr+AWJI6DwxfRKur R174Ov6DFYDGqcG2bflexDOGTkJgtd0CLzKLP+0b7IIrXDuqaxk5NXTQ5wWNlPwvRAH9 MG/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717681793; x=1718286593; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cEG1fPkJ+g/jXimIp5Gy6n7CLs83yHdB825jkzDzPOg=; b=ptIIquJknF+mj6uvfGyZ+714eY/doe2KEHDIAcMdjg66uhsaXeJ2+HnqKKE2aM3rh6 oeFNUGPr9AWGfjAJEQtCl3SU5DWZYRikKFDwzopiYo0VUUk+ZY8wcEGOGOq1D2WnMLOu kfL8Xc23NECXHkzFZAaCYN6OMMp7FJbldT23JwP9gecxSyIPHpBFwVp8aTm8P5RG/1+b JZ2SKGv0fYuELTfE5mr+kRknhj8lQv37OhFxjlsGIRib/riZzVptqIWeTwpVnyO0fZnS gePs5X1w9M1mtOgrMM7bFuWoaAlL46UeygtwIUoIOP2JSLK5iPqhJifRVLHlY+QLv91w 4PjQ== X-Gm-Message-State: AOJu0Yz0yfpDpzZWiwD7l01SvAdQYMUxyChn6x0W3g2t/DQMJYiqV1/u c52cWhqkSPhwGc4z5w/0p0d2/nsfo9pTHT9+26RvNLhrNPZUDof4gesl1V+cHY9/bPTN559pghv 6GyomntdI5StG18WnAM61Q4otSOxpM26Js/EkFp9j0uabPINexffKJPJRz7N6PuPK5KLhW6FJVG RmqAmh2hlr5Y2Kv2tvs9yKcBL40/pQcyPvYrs= X-Google-Smtp-Source: AGHT+IHdKISYxbIDFt7eqi9B3TUfLTHowMV9NWWnXgAGoNuJH6r/6Pn0q/CLElQptWDdrCUqcIbEcQ== X-Received: by 2002:a05:6a20:8423:b0:1a9:d9bb:acdc with SMTP id adf61e73a8af0-1b2b6ff70bfmr6534936637.28.1717681792576; Thu, 06 Jun 2024 06:49:52 -0700 (PDT) Received: from hsinchu36-syssw02.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703fd50bc86sm1150919b3a.175.2024.06.06.06.49.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 06:49:52 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang Subject: [PATCH v4 4/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 Date: Thu, 6 Jun 2024 21:54:52 +0800 Message-Id: <20240606135454.119186-5-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606135454.119186-1-fea.wang@sifive.com> References: <20240606135454.119186-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=fea.wang@sifive.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH and HEDELEGH for exception codes 32-47 for reserving and exception codes 48-63 for custom use. Add the CSR number though the implementation is just reading zero and writing ignore. Besides, for accessing HEDELEGH, it should be controlled by mstateen0 'P1P13' bit. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index c895aa0334..096a51b331 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -156,6 +156,8 @@ /* 32-bit only */ #define CSR_MSTATUSH 0x310 +#define CSR_MEDELEGH 0x312 +#define CSR_HEDELEGH 0x612 /* Machine Trap Handling */ #define CSR_MSCRATCH 0x340 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a19e1afa1f..6f15612e76 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3229,6 +3229,33 @@ static RISCVException write_hedeleg(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException read_hedelegh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + RISCVException ret; + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + + /* Reserved, now read zero */ + *val = 0; + return RISCV_EXCP_NONE; +} + +static RISCVException write_hedelegh(CPURISCVState *env, int csrno, + target_ulong val) +{ + RISCVException ret; + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + + /* Reserved, now write ignore */ + return RISCV_EXCP_NONE; +} + static RISCVException rmw_hvien64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -4633,6 +4660,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, + [CSR_MEDELEGH] = { "medelegh", any32, read_zero, write_ignore, + .min_priv_ver = PRIV_VERSION_1_13_0 }, + [CSR_HEDELEGH] = { "hedelegh", hmode32, read_hedelegh, write_hedelegh, + .min_priv_ver = PRIV_VERSION_1_13_0 }, /* Machine Trap Handling */ [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, From patchwork Thu Jun 6 13:54:53 2024 Content-Type: text/plain; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703fd50bc86sm1150919b3a.175.2024.06.06.06.49.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 06:49:55 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang Subject: [PATCH v4 5/6] target/riscv: Reserve exception codes for sw-check and hw-err Date: Thu, 6 Jun 2024 21:54:53 +0800 Message-Id: <20240606135454.119186-6-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606135454.119186-1-fea.wang@sifive.com> References: <20240606135454.119186-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=fea.wang@sifive.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 096a51b331..c257c5ed7d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -673,6 +673,8 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */ + RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */ RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16, From patchwork Thu Jun 6 13:54:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Fea.Wang" X-Patchwork-Id: 13688531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01ECEC25B75 for ; Thu, 6 Jun 2024 13:50:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sFDVG-0000tf-2x; Thu, 06 Jun 2024 09:50:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sFDVD-0000sr-GY for qemu-devel@nongnu.org; Thu, 06 Jun 2024 09:50:04 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sFDVB-0008Vc-UH for qemu-devel@nongnu.org; Thu, 06 Jun 2024 09:50:03 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-7025c5e6b94so824803b3a.0 for ; Thu, 06 Jun 2024 06:50:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717681800; x=1718286600; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=usOqXbXkbJ9HZDlyGy80tWgPo2DcyM3jU9sVK9mHWJY=; b=V41fEu4tn9Frhsxr0S/sK000Saoo0jPdyip4YdbAWezn5tTZcaG+60GORd/g24QPXA 9F9nOcQ95bRe3A6T1pgdGRDN5tcFS8hdhbls4dyxH57oZ9zbPBJpI7zfB0V8eJF4nUfy n+quNBcSvpJwxrAaaYj57UqnsEHfS1Kvsi9P0NMIEzXtM9nTmmNTyAv7v7SE11EoVRJ8 kDa8rfI48jmPYh+k0Eq4Aq0YdA0J5pIUkzD5x2eG+C2cbw7XP5q9htsG/SePIYvVqEyj JMVctEmV3I9hM1L8Ns6QQ+tZqn13Cx73r2jGGAUNkJWEdzg3V2SWwljhymaS58JFfe7l M2xA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717681800; x=1718286600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=usOqXbXkbJ9HZDlyGy80tWgPo2DcyM3jU9sVK9mHWJY=; b=J8mPK2vzf0pm4vVB5P173TFpC3E+/QfgA3bOFh10YEB2mhzd9YORbobZjVzo5EPB5p ZGjkLEN9aYcktPXOeYoWOkgeMjuurOOBPeqh3F+kGQCMSZjybz5wxRZJolJvWRACaHMW lRNW/Fpsg94efik9TqW+tnA38k5sDvmRbBaaAEI6dbwy12QRspzgIe79RxMq11mWkiSX Nrc46qxyP0bMpvlIbsc39nuxuiFsWY4fEd+WBtcT7jXM6tkIsZKdC3WR/KpuWBl3mjEE jKAaU9mGrKILbV+wVgIkgjlRpwaChEOB6GSNnduDKVgDYE36mn5LrH2f0AmaXJ0sLJqq Z6Aw== X-Gm-Message-State: AOJu0YzXebb082C6IAc7S85p0yyM/8077ND0PGpG+/f4y2/OQAE4x2yB 5oj0FAu+ATBVJ1NtH+YkirUe2gOP6xvPGj0F6Qq33lb96dlA/eowqP/anruA2aP1zCGF7eRrbuQ 8ehYfmYXXtQE13IH1uOtxolfoEsbvtuUFvarQoNLQEid9DTdjAEuW+7C2tkUoTl4s0He5eigX2j n+w/HrfbwbxPL5cuSj2xQzx3qwewtpVUZc91Q= X-Google-Smtp-Source: AGHT+IFpm4pG3TsS7kmwb10xDXEYL9i/Udy7tN3biW8ZeVQgclq0r3hr7Ert7f6b4kX6A+6mE2i3jg== X-Received: by 2002:a05:6a00:298c:b0:6ec:d76b:6fac with SMTP id d2e1a72fcca58-703e594ad8amr6043039b3a.12.1717681799964; Thu, 06 Jun 2024 06:49:59 -0700 (PDT) Received: from hsinchu36-syssw02.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703fd50bc86sm1150919b3a.175.2024.06.06.06.49.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 06:49:59 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang Subject: [PATCH v4 6/6] target/riscv: Support the version for ss1p13 Date: Thu, 6 Jun 2024 21:54:54 +0800 Message-Id: <20240606135454.119186-7-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606135454.119186-1-fea.wang@sifive.com> References: <20240606135454.119186-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=fea.wang@sifive.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 6 +++++- target/riscv/tcg/tcg-cpu.c | 4 ++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fd0f09c468..4760cb2cc1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1779,7 +1779,9 @@ static int priv_spec_from_str(const char *priv_spec_str) { int priv_version = -1; - if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) { + if (!g_strcmp0(priv_spec_str, PRIV_VER_1_13_0_STR)) { + priv_version = PRIV_VERSION_1_13_0; + } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) { priv_version = PRIV_VERSION_1_12_0; } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) { priv_version = PRIV_VERSION_1_11_0; @@ -1799,6 +1801,8 @@ const char *priv_spec_to_str(int priv_version) return PRIV_VER_1_11_0_STR; case PRIV_VERSION_1_12_0: return PRIV_VER_1_12_0_STR; + case PRIV_VERSION_1_13_0: + return PRIV_VER_1_13_0_STR; default: return NULL; } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 4c6141f947..eb6f7b9d12 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -318,6 +318,10 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu) cpu->cfg.has_priv_1_12 = true; } + if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { + cpu->cfg.has_priv_1_13 = true; + } + /* zic64b is 1.12 or later */ cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && cpu->cfg.cbop_blocksize == 64 &&