From patchwork Thu Feb 28 12:37:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 10832993 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4661E13B5 for ; Thu, 28 Feb 2019 12:38:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 346A32EBAB for ; Thu, 28 Feb 2019 12:38:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 243472EBC4; Thu, 28 Feb 2019 12:38:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8E40D2EBAB for ; Thu, 28 Feb 2019 12:38:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726232AbfB1MiB (ORCPT ); Thu, 28 Feb 2019 07:38:01 -0500 Received: from mail-eopbgr820054.outbound.protection.outlook.com ([40.107.82.54]:54112 "EHLO NAM01-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730931AbfB1MiA (ORCPT ); Thu, 28 Feb 2019 07:38:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.onmicrosoft.com; s=selector1-analog-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XeAodR0TIrrn30+3kptjQCjNwyoSV6WtqNEa1b5y9Ug=; b=GGztICeDbmUjayi6nosifWFUuPHf1fPpa6yuVufK1LQldXxPaSVsOXPKLUGa3Tl+9jpIWqHItOO+hcSPGg+gqEzOGHEMqf+KN6wcLlRM3M+3XHujktQuUy1imIEYl+aldpsIojiu1pQc8UCE4OiHZWei8qFL0/oIMtEZ1centBQ= Received: from CY1PR03CA0027.namprd03.prod.outlook.com (2603:10b6:600::37) by DM6PR03MB3756.namprd03.prod.outlook.com (2603:10b6:5:50::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1643.16; Thu, 28 Feb 2019 12:37:53 +0000 Received: from CY1NAM02FT019.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e45::200) by CY1PR03CA0027.outlook.office365.com (2603:10b6:600::37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.1665.15 via Frontend Transport; Thu, 28 Feb 2019 12:37:53 +0000 Authentication-Results: spf=pass (sender IP is 137.71.25.55) smtp.mailfrom=analog.com; kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=bestguesspass action=none header.from=analog.com; Received-SPF: Pass (protection.outlook.com: domain of analog.com designates 137.71.25.55 as permitted sender) receiver=protection.outlook.com; client-ip=137.71.25.55; helo=nwd2mta1.analog.com; Received: from nwd2mta1.analog.com (137.71.25.55) by CY1NAM02FT019.mail.protection.outlook.com (10.152.75.177) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.1643.11 via Frontend Transport; Thu, 28 Feb 2019 12:37:53 +0000 Received: from NWD2HUBCAS7.ad.analog.com (nwd2hubcas7.ad.analog.com [10.64.69.107]) by nwd2mta1.analog.com (8.13.8/8.13.8) with ESMTP id x1SCbqHu024758 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=OK); Thu, 28 Feb 2019 04:37:52 -0800 Received: from saturn.analog.com (10.50.1.244) by NWD2HUBCAS7.ad.analog.com (10.64.69.107) with Microsoft SMTP Server id 14.3.408.0; Thu, 28 Feb 2019 07:37:51 -0500 From: Alexandru Ardelean To: , CC: , Lars-Peter Clausen , Alexandru Ardelean Subject: [V2 PATCH] dmaengine: axi-dmac: Split too large segments Date: Thu, 28 Feb 2019 14:37:43 +0200 Message-ID: <20190228123743.12431-1-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:137.71.25.55;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(376002)(346002)(39860400002)(136003)(396003)(2980300002)(54534003)(189003)(199004)(43544003)(51416003)(26005)(2906002)(246002)(8676002)(106466001)(5660300002)(426003)(54906003)(110136005)(77096007)(336012)(305945005)(7696005)(50226002)(6666004)(53416004)(356004)(186003)(7636002)(8936002)(72206003)(966005)(107886003)(36756003)(4326008)(478600001)(16586007)(126002)(1076003)(50466002)(48376002)(486006)(476003)(44832011)(316002)(2616005)(47776003)(106002)(6306002);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR03MB3756;H:nwd2mta1.analog.com;FPR:;SPF:Pass;LANG:en;PTR:nwd2mail10.analog.com;MX:1;A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e79174c7-f6e7-4f37-1f9f-08d69d798f01 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(4608103)(4709054)(2017052603328)(7153060);SRVR:DM6PR03MB3756; X-MS-TrafficTypeDiagnostic: DM6PR03MB3756: X-MS-Exchange-PUrlCount: 1 X-Microsoft-Exchange-Diagnostics: 1;DM6PR03MB3756;20:1UYJyVSjtQp9rEgGx9y3DyEsVCacJysiAWo+3JHDZ5x1a0fDkg/UQBX4Ri4KguEuDtRUbR6Gl8AYZZv9UgKnv6uIz4HjwFeu9vqVAXlDysxBBtNCl+TdaydhsO13Lulw6oMz15PyJzn+DU7oW1HOTWJ5AziBaEVCzru2efQThdYIQfB/sExjSBBWh2G/3JxzxdGbTHiFY6YruPv259RDqWroh4Lj99Fc0bjaON3KzEXA77xS2yQ6qieeN3yEU2Jp8slCRyC62D9zkgMUoQJ53rGr1dbA9MOuBThaeIJSO1CblKcwtljWpG7mjhNXRKs0Bvc8gKdn+5mKzXkgdfQagz1oMiOk8tBaLmAqhv5pg+UxeaaLd0AZuw+/KmygsrcBP3lvGJQranXH38DOijrkCPr7MQDaS57q9IdJxoGHVS3OfBy8uLHvg7i3cAUqsgv8WCVMovhoNug7kmyLeknNsvgv0ywNR+in7EL62YBBUBrwgOkHtnZk+X7beMGZAWKK X-Microsoft-Antispam-PRVS: X-Forefront-PRVS: 0962D394D2 X-Microsoft-Exchange-Diagnostics: 1;DM6PR03MB3756;23:a5ZLf6FsW/KPE5TeVkj5lzQ3fWWsrdWZyfurqzir8SYvwer/KFReTz57MhKRXVCKTWuc3942qQKlMfVB6ALrJ7VAc4uTp5gQe9783yUXGWaNUSCK/OJJoaMN3ZZDfpTlhUQiXKE762bzWgiar1jHpXo1I8KMnwyWR1DMaHzl1Zk0/dfDZ4rD2+r6fZKpxxxesntcPPkkr3Yd9OrqC9olLKgRarmOh8TkzX45dzHy8GGRKvz6n2pPjLl5jqx6Um/dNJSRQO0V+QkUpH770uO4e8Tw59DduqTy91fdZyVE9yDisfHw5wM4mtfoS8wzgnXgnH42+MoVB1+/8G8whtin1K5HQkiSjNp97/d+Za/agNxhQo9CyND8FbKU0kdJyR/Ft1XKsh5a9l1pZuZEVHKHoZ6CsXy1D0/8JB4vO5CbtzkBJ/0sQ2OJS3p7SLL6CTsvi/A6oBRBCyctiPbwpaFHyGtpUxweRX31d+/so5yymp91uuA1hAPHUPZ5i3+fj/6CdkIaD8/EpkaJGTu2S4V2Xe5aLJ8wuw+5m0BmrY5lOilTXipTMQZxhvFIs8oqSAdl276ZA8NLIYNQPfClcDIJdQZrUeatJpf/3x/HjnzJKP4hA8dIDz1XKYue6nPEkKEmYmgCJtp/xfGTBn1sKqIgWmq+CoZT76V1DXbxbmcl5WyjBzBJc+SIKcJMdq8K0hb+KHsoTqgFJOq37upTqv6Xlmmwr78Kkz/pytjBJ+4SU+O7QKV6+UibVwwdS4kylJe03XiH/0O7zs8YHr0ur77GO33O+cCzd+6bcNZ5C5nrtuHkbVErNxIIjq5+SzHmKOD48BWSGRYE1QRMECNLsoDUHgIErqfYNekm8uH2BF4F862Vx0lYXZuJPtjrKurQoNbWj92XHG8yyPYwsTVIXBIE7lM+eGV4PqSdJxoQ2Tr59AUwGeWqun2lLYNZLNq7QoGcyHXfIv2QwYxOpLiOrXUHBsli38SsHily1ohVx2o35TqX3CU3tPE/xaNbEqEgJ913dsS1OcTXrys7obG8MLjYNccr8VkMDlTpyBtYHFKPgLGU9GOg5LqTxbT0UNqn+eB5HGD1LfUrbCEK1VYbm4g4mQ== X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: 9ynr3JQqYIplyutyLnQwweU4ljebwCJXDgCMPNC/IAWHZ4b67vCe8OGKqEW4G+jKdastbT6kEXpSF0CItkAYbEsejDn70xTUJZnTqqvWcZfZiz3d9wejjZ6LP7MQjWojqDpHQuHR9ZZlcZYCArO//Q9hqD9hVxPIVbnZ3V/9Qbq7ispIKdmzfhsYReFsWctHksfCW+7Zcc5403gtq/S/Xl44k6LqqBVYjtnFmbl9UWyKDF+j52fgIgoF09cBbB9QaKCG40Ro/ZeRlElQJb8vKUBKLG3aRfUYGCkn+bXIK5+dOvw5+GWhvHdMHZQR8/f0Xf7VN/H2pPkDWpJNFa6lO26cZrNESmt6LRinbyMTcGewOvXsXOYbjlFIC4lZSTV61CkJt0izG+b4qUnpGAm/7bc77YQU9BERra4VvqMAey4= X-OriginatorOrg: analog.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2019 12:37:53.1770 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e79174c7-f6e7-4f37-1f9f-08d69d798f01 X-MS-Exchange-CrossTenant-Id: eaa689b4-8f87-40e0-9c6f-7228de4d754a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=eaa689b4-8f87-40e0-9c6f-7228de4d754a;Ip=[137.71.25.55];Helo=[nwd2mta1.analog.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR03MB3756 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Lars-Peter Clausen The axi-dmac driver currently rejects transfers with segments that are larger than what the hardware can handle. Re-work the driver so that these large segments are split into multiple segments instead where each segment is smaller or equal to the maximum segment size. This allows the driver to handle transfers with segments of arbitrary size. Signed-off-by: Lars-Peter Clausen Signed-off-by: Alexandru Ardelean --- Changelog V1->V2: * reworked this patch to not use the `sg_nents_for_dma()` helper from https://patchwork.kernel.org/patch/9389821/ After some discussion with Andy Shevchenko and some thought about it, it probably does not make sense to have this helper for this driver only, since a more generic solution could be implemented via DMAEngine API. This generic solution is not yet implemented (as I understood it from the discussion). drivers/dma/dma-axi-dmac.c | 83 +++++++++++++++++++++++++++++--------- 1 file changed, 63 insertions(+), 20 deletions(-) diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c index ffc0adc2f6ce..17869132e05f 100644 --- a/drivers/dma/dma-axi-dmac.c +++ b/drivers/dma/dma-axi-dmac.c @@ -83,6 +83,7 @@ struct axi_dmac_sg { unsigned int dest_stride; unsigned int src_stride; unsigned int id; + bool last; bool schedule_when_free; }; @@ -166,7 +167,7 @@ static int axi_dmac_dest_is_mem(struct axi_dmac_chan *chan) static bool axi_dmac_check_len(struct axi_dmac_chan *chan, unsigned int len) { - if (len == 0 || len > chan->max_length) + if (len == 0) return false; if ((len & chan->align_mask) != 0) /* Not aligned */ return false; @@ -379,6 +380,50 @@ static struct axi_dmac_desc *axi_dmac_alloc_desc(unsigned int num_sgs) return desc; } +static struct axi_dmac_sg *axi_dmac_fill_linear_sg(struct axi_dmac_chan *chan, + enum dma_transfer_direction direction, dma_addr_t addr, + unsigned int num_periods, unsigned int period_len, + struct axi_dmac_sg *sg) +{ + unsigned int num_segments, i; + unsigned int segment_size; + unsigned int len; + + /* Split into multiple equally sized segments if necessary */ + num_segments = DIV_ROUND_UP(period_len, chan->max_length); + segment_size = DIV_ROUND_UP(period_len, num_segments); + /* Take care of alignment */ + segment_size = ((segment_size - 1) | chan->align_mask) + 1; + + for (i = 0; i < num_periods; i++) { + len = period_len; + + while (len > segment_size) { + if (direction == DMA_DEV_TO_MEM) + sg->dest_addr = addr; + else + sg->src_addr = addr; + sg->x_len = segment_size; + sg->y_len = 1; + sg++; + addr += segment_size; + len -= segment_size; + } + + if (direction == DMA_DEV_TO_MEM) + sg->dest_addr = addr; + else + sg->src_addr = addr; + sg->x_len = len; + sg->y_len = 1; + sg->last = true; + sg++; + addr += len; + } + + return sg; +} + static struct dma_async_tx_descriptor *axi_dmac_prep_slave_sg( struct dma_chan *c, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction direction, @@ -386,16 +431,24 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_slave_sg( { struct axi_dmac_chan *chan = to_axi_dmac_chan(c); struct axi_dmac_desc *desc; + struct axi_dmac_sg *dsg; struct scatterlist *sg; + unsigned int num_sgs; unsigned int i; if (direction != chan->direction) return NULL; - desc = axi_dmac_alloc_desc(sg_len); + num_sgs = 0; + for_each_sg(sgl, sg, sg_len, i) + num_sgs += DIV_ROUND_UP(sg_dma_len(sg), chan->max_length); + + desc = axi_dmac_alloc_desc(num_sgs); if (!desc) return NULL; + dsg = desc->sg; + for_each_sg(sgl, sg, sg_len, i) { if (!axi_dmac_check_addr(chan, sg_dma_address(sg)) || !axi_dmac_check_len(chan, sg_dma_len(sg))) { @@ -403,12 +456,8 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_slave_sg( return NULL; } - if (direction == DMA_DEV_TO_MEM) - desc->sg[i].dest_addr = sg_dma_address(sg); - else - desc->sg[i].src_addr = sg_dma_address(sg); - desc->sg[i].x_len = sg_dma_len(sg); - desc->sg[i].y_len = 1; + dsg = axi_dmac_fill_linear_sg(chan, direction, sg_dma_address(sg), 1, + sg_dma_len(sg), dsg); } desc->cyclic = false; @@ -423,7 +472,7 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_dma_cyclic( { struct axi_dmac_chan *chan = to_axi_dmac_chan(c); struct axi_dmac_desc *desc; - unsigned int num_periods, i; + unsigned int num_periods, num_segments; if (direction != chan->direction) return NULL; @@ -436,20 +485,14 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_dma_cyclic( return NULL; num_periods = buf_len / period_len; + num_segments = DIV_ROUND_UP(period_len, chan->max_length); - desc = axi_dmac_alloc_desc(num_periods); + desc = axi_dmac_alloc_desc(num_periods * num_segments); if (!desc) return NULL; - for (i = 0; i < num_periods; i++) { - if (direction == DMA_DEV_TO_MEM) - desc->sg[i].dest_addr = buf_addr; - else - desc->sg[i].src_addr = buf_addr; - desc->sg[i].x_len = period_len; - desc->sg[i].y_len = 1; - buf_addr += period_len; - } + axi_dmac_fill_linear_sg(chan, direction, buf_addr, num_periods, + buf_len, desc->sg); desc->cyclic = true; @@ -647,7 +690,7 @@ static int axi_dmac_probe(struct platform_device *pdev) of_node_put(of_channels); pdev->dev.dma_parms = &dmac->dma_parms; - dma_set_max_seg_size(&pdev->dev, dmac->chan.max_length); + dma_set_max_seg_size(&pdev->dev, UINT_MAX); dma_dev = &dmac->dma_dev; dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);