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Wysocki" , Viresh Kumar , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Chris Morgan , Sudeep Holla , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Stephen Boyd , Rob Herring , Ryan Walklin Subject: [PATCH 1/3] cpufreq: sun50i: add Allwinner H700 speed bin Date: Fri, 7 Jun 2024 21:20:33 +1200 Message-ID: <20240607092140.33112-2-ryan@testtoast.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240607092140.33112-1-ryan@testtoast.com> References: <20240607092140.33112-1-ryan@testtoast.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Support for the Allwinner H618, H618 and H700 was added to the sun50i cpufreq-nvmem driver recently [1] however at the time some operating points supported by the H700 (1.008, 1.032 and 1.512 GHz) and in use by vendor BSPs were found to be unstable during testing, so the H700 speed bin and the 1.032 GHz OPP were not included in the mainline driver. Retesting with kernel 6.10rc2 (which carries additional fixes for the driver) now shows stable operation with these points. Add the H700 speed bin to the driver. Signed-off-by: Ryan Walklin Reviewed-by: Andre Przywara --- [1] https://lore.kernel.org/linux-sunxi/20240418154408.1740047-1-andre.przywara@arm.com --- drivers/cpufreq/sun50i-cpufreq-nvmem.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c index 0b882765cd66f..969f22aadd950 100644 --- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c +++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c @@ -91,6 +91,9 @@ static u32 sun50i_h616_efuse_xlate(u32 speedbin) case 0x5d00: value = 0; break; + case 0x6c00: + value = 5; + break; default: pr_warn("sun50i-cpufreq-nvmem: unknown speed bin 0x%x, using default bin 0\n", speedbin & 0xffff); From patchwork Fri Jun 7 09:20:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Walklin X-Patchwork-Id: 13689549 X-Patchwork-Delegate: viresh.linux@gmail.com Received: from wfout7-smtp.messagingengine.com (wfout7-smtp.messagingengine.com [64.147.123.150]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58DAF15B15F for ; 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Fri, 7 Jun 2024 05:22:00 -0400 (EDT) From: Ryan Walklin To: Yangtao Li , "Rafael J . Wysocki" , Viresh Kumar , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Chris Morgan , Sudeep Holla , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Stephen Boyd , Rob Herring , Ryan Walklin Subject: [PATCH 2/3] arm64: dts: allwinner: h616: add additional CPU OPPs for the H700 Date: Fri, 7 Jun 2024 21:20:34 +1200 Message-ID: <20240607092140.33112-3-ryan@testtoast.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240607092140.33112-1-ryan@testtoast.com> References: <20240607092140.33112-1-ryan@testtoast.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The H700 now shows stable operation with the 1.008, 1.032 and 1.512 GHz DVFS operating points. The 1.5GHz OPP requires a VDD-CPU of 1.16V, obtained from the vendor BSP. This voltage is slightly above the recommended operating voltage for the H616 (H700 datasheet not publicly available) but well within the absolute maximum of 1.3V. Add the additional 1.032 GHz operating point to the H616 CPU-OPP table, and enable the 1.008 and 1.512 points for the H700. Signed-off-by: Ryan Walklin Reviewed-by: Andre Przywara --- .../dts/allwinner/sun50i-h616-cpu-opp.dtsi | 25 +++++++++++++------ 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi index aca22a7f0191c..dd10aaf472b66 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi @@ -11,7 +11,7 @@ opp-480000000 { opp-hz = /bits/ 64 <480000000>; opp-microvolt = <900000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; + opp-supported-hw = <0x3f>; }; opp-600000000 { @@ -25,7 +25,7 @@ opp-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <900000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; + opp-supported-hw = <0x2d>; }; opp-792000000 { @@ -50,8 +50,16 @@ opp-1008000000 { opp-microvolt-speed2 = <950000>; opp-microvolt-speed3 = <950000>; opp-microvolt-speed4 = <1020000>; + opp-microvolt-speed5 = <900000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; + opp-supported-hw = <0x3f>; + }; + + opp-1032000000 { + opp-hz = /bits/ 64 <1032000000>; + opp-microvolt = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x20>; }; opp-1104000000 { @@ -59,8 +67,9 @@ opp-1104000000 { opp-microvolt-speed0 = <1000000>; opp-microvolt-speed2 = <1000000>; opp-microvolt-speed3 = <1000000>; + opp-microvolt-speed5 = <950000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; + opp-supported-hw = <0x2d>; }; opp-1200000000 { @@ -70,8 +79,9 @@ opp-1200000000 { opp-microvolt-speed2 = <1050000>; opp-microvolt-speed3 = <1050000>; opp-microvolt-speed4 = <1100000>; + opp-microvolt-speed5 = <1020000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; + opp-supported-hw = <0x3f>; }; opp-1320000000 { @@ -85,15 +95,16 @@ opp-1416000000 { opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <1100000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; + opp-supported-hw = <0x2d>; }; opp-1512000000 { opp-hz = /bits/ 64 <1512000000>; opp-microvolt-speed1 = <1100000>; opp-microvolt-speed3 = <1100000>; + opp-microvolt-speed5 = <1160000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0a>; + opp-supported-hw = <0x2a>; }; }; }; From patchwork Fri Jun 7 09:20:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Walklin X-Patchwork-Id: 13689550 X-Patchwork-Delegate: viresh.linux@gmail.com Received: from wfhigh2-smtp.messagingengine.com (wfhigh2-smtp.messagingengine.com [64.147.123.153]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4816F15B966 for ; Fri, 7 Jun 2024 09:22:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 7 Jun 2024 05:22:07 -0400 (EDT) From: Ryan Walklin To: Yangtao Li , "Rafael J . Wysocki" , Viresh Kumar , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Chris Morgan , Sudeep Holla , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Stephen Boyd , Rob Herring , Ryan Walklin Subject: [PATCH 3/3] arm64: dts: allwinner: rg35xx: Enable DVFS CPU frequency scaling Date: Fri, 7 Jun 2024 21:20:35 +1200 Message-ID: <20240607092140.33112-4-ryan@testtoast.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240607092140.33112-1-ryan@testtoast.com> References: <20240607092140.33112-1-ryan@testtoast.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Anbernic RG35XX device variants (-2024, -H, -Plus and -SP) are the only currently known devices to have an Allwinner H700 SoC. The closely related RG28XX also has the H700 but a mainline DT for this device has not yet been submitted. Include the H616 CPU OPP table in the base device DTS, and increase the DCDC1 regulator (vdd-cpu) upper voltage range to 1.16V, allowing the CPU to reach 1.5GHz. Signed-off-by: Ryan Walklin Reviewed-by: Andre Przywara --- .../boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts index ee30584b6ad70..afb49e65859f9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "sun50i-h616.dtsi" - +#include "sun50i-h616-cpu-opp.dtsi" #include #include #include @@ -221,7 +221,7 @@ regulators { reg_dcdc1: dcdc1 { regulator-always-on; regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; + regulator-max-microvolt = <1160000>; regulator-name = "vdd-cpu"; };