From patchwork Fri Jun 7 09:57:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13689573 X-Patchwork-Delegate: kuba@kernel.org Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06D1D157A76; Fri, 7 Jun 2024 09:59:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717754382; cv=none; b=XzDAOCPQFujclX7Cdaesu2ctqMDzmHSL52bSTnhEWGWiDJ+36+gxI+ohOIJCoWrORWEz4uCInN/5/LHXJb3c58LnJPLITaL9Xmy4krc474Bjjxmixqe9FCAyed4tInyD/zmPNeQGxcb7ge0pCjVjJ8V7N6NBQD87DuQnAwFgtyI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717754382; c=relaxed/simple; bh=ELHG6KXsCPxpq8rAjFOjUunqXofuwXSI9tyRIUTmPAc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AT8fKew9PbhCihNyUk0LiE3yFOUd9h9WzoMqPCvzbuE8NRI2f3SM/eejOrn31Lo9M86dgc6ZAfuv3k3ojFWHUcfEJEr7vxtLihmj6NMID//b7h/gG7mBmUq0b1cTDlWSvNpYpLb0+aYCZxoStjHwwZ2EREbrphwnSjHWC5OCZwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=AxAUXL9U; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="AxAUXL9U" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45792a2M010983; Fri, 7 Jun 2024 11:59:19 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= MATnV0OWqMTL3XMj64kWzJNas3kxCFy5hM5TuSEEvLY=; b=AxAUXL9UMNVMZZB+ iFEeVMIzu/Hz5WW0knPgOIhSmwGtHo7HUavf+tCtVv8jrtSBjN1t2OYOOF+Yhtbl r9ZMXtKx3xhdSLS+qdcMaIlb8HTi3X1QgvMCygXscbSybOXVqBpUhPa2PCH/JZSV T0G8gP7vPIw8RBOvw6Zm+VZj0DJ/iu1TqaY0LvSb4alf50w601I4XmwwmNjqr/je ZthMKFSt7lUl16jjNM+KzudH2NnNMto3GwBntJ8tklQb8qgG/oUlHQ8GIyHEn4lt hFvEWLGh+cpehww/+0SXDI/GsIYJ7m+DfEGKirT8VYUd/tBWji1VNL+afUTjicEk 1zat/g== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ykbv54d4r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Jun 2024 11:59:18 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 949234004B; Fri, 7 Jun 2024 11:59:14 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A1417214D13; Fri, 7 Jun 2024 11:58:00 +0200 (CEST) Received: from localhost (10.252.19.205) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 7 Jun 2024 11:58:00 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [PATCH v5 01/12] dt-bindings: net: add STM32MP13 compatible in documentation for stm32 Date: Fri, 7 Jun 2024 11:57:43 +0200 Message-ID: <20240607095754.265105-2-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240607095754.265105-1-christophe.roullier@foss.st.com> References: <20240607095754.265105-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-07_04,2024-06-06_02,2024-05-17_01 X-Patchwork-Delegate: kuba@kernel.org New STM32 SOC have 2 GMACs instances. GMAC IP version is SNPS 4.20. Signed-off-by: Christophe Roullier --- .../devicetree/bindings/net/stm32-dwmac.yaml | 43 ++++++++++++++++--- 1 file changed, 36 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index 7ccf75676b6d5..f6e5e0626a3fb 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -22,18 +22,17 @@ select: enum: - st,stm32-dwmac - st,stm32mp1-dwmac + - st,stm32mp13-dwmac required: - compatible -allOf: - - $ref: snps,dwmac.yaml# - properties: compatible: oneOf: - items: - enum: - st,stm32mp1-dwmac + - st,stm32mp13-dwmac - const: snps,dwmac-4.20a - items: - enum: @@ -75,12 +74,15 @@ properties: st,syscon: $ref: /schemas/types.yaml#/definitions/phandle-array items: - - items: + - minItems: 2 + items: - description: phandle to the syscon node which encompases the glue register - description: offset of the control register + - description: field to set mask in register description: Should be phandle/offset pair. The phandle to the syscon node which - encompases the glue register, and the offset of the control register + encompases the glue register, the offset of the control register and + the mask to set bitfield in control register st,ext-phyclk: description: @@ -112,12 +114,39 @@ required: unevaluatedProperties: false +allOf: + - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp1-dwmac + - st,stm32-dwmac + then: + properties: + st,syscon: + items: + minItems: 2 + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp13-dwmac + then: + properties: + st,syscon: + items: + minItems: 3 + maxItems: 3 + examples: - | #include #include - #include - #include //Example 1 ethernet0: ethernet@5800a000 { compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; From patchwork Fri Jun 7 09:57:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13689574 X-Patchwork-Delegate: kuba@kernel.org Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71701157E76; Fri, 7 Jun 2024 09:59:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717754383; cv=none; b=AMtD12YT3BI0eQYdP9f4PIMvgBPNuyzQERstY/lLE7MIFXa3IL2PKwICFeqaNpM4BWAVEm1f0vhYm/On7pspKF5ppO1e08hnmaNA/76ScToA6lOJ6ehslKm9g/SmK88Im09x1CgM4958f0UMWOh5WCeTEWbxc/16FtlyRP00Ayk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717754383; c=relaxed/simple; bh=CzcWoMBzn29QzER+PxKqVEeUMc90IdZvWfmL2zf9o+A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LNMrypFWgkNc9zToJC6sI1beEQRv8K6uVO6duZjdlpzGk8lchZJe8dybyD9Vjt4RVo3fL8ZqLRVY3RDog24D2R9vlyriHAx+wzjIpZC0m5VoyCrzAWA73j9e4RV5DyFiUd4w7u3KckJwFqgzyeYbw4xj1uFO16VwCuYLdgGphs0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=AC7wwMnS; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="AC7wwMnS" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45791ZEB002163; Fri, 7 Jun 2024 11:59:18 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= hN/g428LiD5uWJnzYnUfLINd1g5a/rCwKHJfJu6r5Uo=; b=AC7wwMnSdaEimooI UzQppoovXQ48/6fFFcLQz5G78bnsMoXx5HVh2uBMG0kpfFKS284UT96QlB02XGCE MNLLXFY+zFxyB46miEx6z0ghYKAfo+eOyrLXvyD59OQd/4TUhPhArI9PM0BQ9mMw L2xUjc994uCYQB2MfckWK0YO3BeXL4shqF+tG1lAhMJ5Z+nkOr2MYTM20+IxvcNm pLdPS0MndA1ZYpawZwF32UyZ9+9pHKLl1d0FKtxEd/pPrDjUNytW0+eqG+FA2FNx ZjbMdNufwDXWsHsCa4ebfiGSVuBGOAP91hBlfrOxEsTnHBdteq+G7h/5/SBF7Bjf oXGrCQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ygekj867v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Jun 2024 11:59:18 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 38C5F4004A; Fri, 7 Jun 2024 11:59:14 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9A1C2214D17; Fri, 7 Jun 2024 11:58:01 +0200 (CEST) Received: from localhost (10.252.19.205) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 7 Jun 2024 11:58:01 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [PATCH v5 02/12] net: stmmac: dwmac-stm32: Separate out external clock rate validation Date: Fri, 7 Jun 2024 11:57:44 +0200 Message-ID: <20240607095754.265105-3-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240607095754.265105-1-christophe.roullier@foss.st.com> References: <20240607095754.265105-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-07_04,2024-06-06_02,2024-05-17_01 X-Patchwork-Delegate: kuba@kernel.org From: Marek Vasut Pull the external clock frequency validation into a separate function, to avoid conflating it with external clock DT property decoding and clock mux register configuration. This should make the code easier to read and understand. This does change the code behavior slightly. The clock mux PMCR register setting now depends solely on the DT properties which configure the clock mux between external clock and internal RCC generated clock. The mux PMCR register settings no longer depend on the supplied clock frequency, that supplied clock frequency is now only validated, and if the clock frequency is invalid for a mode, it is rejected. Previously, the code would switch the PMCR register clock mux to internal RCC generated clock if external clock couldn't provide suitable frequency, without checking whether the RCC generated clock frequency is correct. Such behavior is risky at best, user should have configured their clock correctly in the first place, so this behavior is removed here. Signed-off-by: Marek Vasut Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 51 +++++++++++++++---- 1 file changed, 41 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index c92dfc4ecf570..2fd2620ebed69 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -157,25 +157,54 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat, bool resume) return stm32_dwmac_clk_enable(dwmac, resume); } +static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat) +{ + struct stm32_dwmac *dwmac = plat_dat->bsp_priv; + const u32 clk_rate = clk_get_rate(dwmac->clk_eth_ck); + + switch (plat_dat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + if (clk_rate == ETH_CK_F_25M) + return 0; + break; + case PHY_INTERFACE_MODE_RMII: + if (clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) + return 0; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + if (clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) + return 0; + break; + default: + break; + } + + dev_err(dwmac->dev, "Mode %s does not match eth-ck frequency %d Hz", + phy_modes(plat_dat->mac_interface), clk_rate); + return -EINVAL; +} + static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) { struct stm32_dwmac *dwmac = plat_dat->bsp_priv; - u32 reg = dwmac->mode_reg, clk_rate; - int val; + u32 reg = dwmac->mode_reg; + int val, ret; - clk_rate = clk_get_rate(dwmac->clk_eth_ck); dwmac->enable_eth_ck = false; switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: - if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk) + if (dwmac->ext_phyclk) dwmac->enable_eth_ck = true; val = SYSCFG_PMCR_ETH_SEL_MII; pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); break; case PHY_INTERFACE_MODE_GMII: val = SYSCFG_PMCR_ETH_SEL_GMII; - if (clk_rate == ETH_CK_F_25M && - (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { + if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) { dwmac->enable_eth_ck = true; val |= SYSCFG_PMCR_ETH_CLK_SEL; } @@ -183,8 +212,7 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) break; case PHY_INTERFACE_MODE_RMII: val = SYSCFG_PMCR_ETH_SEL_RMII; - if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) && - (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) { + if (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk) { dwmac->enable_eth_ck = true; val |= SYSCFG_PMCR_ETH_REF_CLK_SEL; } @@ -195,8 +223,7 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: val = SYSCFG_PMCR_ETH_SEL_RGMII; - if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) && - (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { + if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) { dwmac->enable_eth_ck = true; val |= SYSCFG_PMCR_ETH_CLK_SEL; } @@ -209,6 +236,10 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) return -EINVAL; } + ret = stm32mp1_validate_ethck_rate(plat_dat); + if (ret) + return ret; + /* Need to update PMCCLRR (clear register) */ regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, dwmac->ops->syscfg_eth_mask); From patchwork Fri Jun 7 09:57:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13689575 X-Patchwork-Delegate: kuba@kernel.org Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE1B8157A56; Fri, 7 Jun 2024 09:59:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [PATCH v5 03/12] net: stmmac: dwmac-stm32: Separate out external clock selector Date: Fri, 7 Jun 2024 11:57:45 +0200 Message-ID: <20240607095754.265105-4-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240607095754.265105-1-christophe.roullier@foss.st.com> References: <20240607095754.265105-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-07_04,2024-06-06_02,2024-05-17_01 X-Patchwork-Delegate: kuba@kernel.org From: Marek Vasut Pull the external clock selector into a separate function, to avoid conflating it with external clock rate validation and clock mux register configuration. This should make the code easier to read and understand. The dwmac->enable_eth_ck variable in the end indicates whether the MAC clock are supplied by external oscillator (true) or internal RCC clock IP (false). The dwmac->enable_eth_ck value is set based on multiple DT properties, some of them deprecated, some of them specific to bus mode. The following DT properties and variables are taken into account. In each case, if the property is present or true, MAC clock is supplied by external oscillator. - "st,ext-phyclk", assigned to variable dwmac->ext_phyclk - Used in any mode (MII/RMII/GMII/RGMII) - The only non-deprecated DT property of the three - "st,eth-clk-sel", assigned to variable dwmac->eth_clk_sel_reg - Valid only in GMII/RGMII mode - Deprecated property, backward compatibility only - "st,eth-ref-clk-sel", assigned to variable dwmac->eth_ref_clk_sel_reg - Valid only in RMII mode - Deprecated property, backward compatibility only The stm32mp1_select_ethck_external() function handles the aforementioned DT properties and sets dwmac->enable_eth_ck accordingly. The stm32mp1_set_mode() is adjusted to call stm32mp1_select_ethck_external() first and then only use dwmac->enable_eth_ck to determine hardware clock mux settings. No functional change intended. Signed-off-by: Marek Vasut Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 50 ++++++++++++++----- 1 file changed, 38 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index 2fd2620ebed69..767994061ea82 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -157,6 +157,37 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat, bool resume) return stm32_dwmac_clk_enable(dwmac, resume); } +static int stm32mp1_select_ethck_external(struct plat_stmmacenet_data *plat_dat) +{ + struct stm32_dwmac *dwmac = plat_dat->bsp_priv; + + switch (plat_dat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + dwmac->enable_eth_ck = dwmac->ext_phyclk; + return 0; + case PHY_INTERFACE_MODE_GMII: + dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg || + dwmac->ext_phyclk; + return 0; + case PHY_INTERFACE_MODE_RMII: + dwmac->enable_eth_ck = dwmac->eth_ref_clk_sel_reg || + dwmac->ext_phyclk; + return 0; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg || + dwmac->ext_phyclk; + return 0; + default: + dwmac->enable_eth_ck = false; + dev_err(dwmac->dev, "Mode %s not supported", + phy_modes(plat_dat->mac_interface)); + return -EINVAL; + } +} + static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat) { struct stm32_dwmac *dwmac = plat_dat->bsp_priv; @@ -194,28 +225,25 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) u32 reg = dwmac->mode_reg; int val, ret; - dwmac->enable_eth_ck = false; + ret = stm32mp1_select_ethck_external(plat_dat); + if (ret) + return ret; + switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: - if (dwmac->ext_phyclk) - dwmac->enable_eth_ck = true; val = SYSCFG_PMCR_ETH_SEL_MII; pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); break; case PHY_INTERFACE_MODE_GMII: val = SYSCFG_PMCR_ETH_SEL_GMII; - if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) { - dwmac->enable_eth_ck = true; + if (dwmac->enable_eth_ck) val |= SYSCFG_PMCR_ETH_CLK_SEL; - } pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n"); break; case PHY_INTERFACE_MODE_RMII: val = SYSCFG_PMCR_ETH_SEL_RMII; - if (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk) { - dwmac->enable_eth_ck = true; + if (dwmac->enable_eth_ck) val |= SYSCFG_PMCR_ETH_REF_CLK_SEL; - } pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n"); break; case PHY_INTERFACE_MODE_RGMII: @@ -223,10 +251,8 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: val = SYSCFG_PMCR_ETH_SEL_RGMII; - if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) { - dwmac->enable_eth_ck = true; + if (dwmac->enable_eth_ck) val |= SYSCFG_PMCR_ETH_CLK_SEL; - } pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n"); break; default: From patchwork Fri Jun 7 09:57:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13689576 X-Patchwork-Delegate: kuba@kernel.org Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67C1B15E5B7; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [PATCH v5 04/12] net: stmmac: dwmac-stm32: Extract PMCR configuration Date: Fri, 7 Jun 2024 11:57:46 +0200 Message-ID: <20240607095754.265105-5-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240607095754.265105-1-christophe.roullier@foss.st.com> References: <20240607095754.265105-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-07_04,2024-06-06_02,2024-05-17_01 X-Patchwork-Delegate: kuba@kernel.org From: Marek Vasut Pull the PMCR clock mux configuration into a separate function. This is the final change of three, which moves external clock rate validation, external clock selector decoding, and clock mux configuration into separate functions. This should make the code easier to understand. No functional change intended. Signed-off-by: Marek Vasut Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 27 ++++++++++++------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index 767994061ea82..aa413edd1ef71 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -219,15 +219,11 @@ static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat) return -EINVAL; } -static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) +static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat) { struct stm32_dwmac *dwmac = plat_dat->bsp_priv; u32 reg = dwmac->mode_reg; - int val, ret; - - ret = stm32mp1_select_ethck_external(plat_dat); - if (ret) - return ret; + int val; switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: @@ -262,10 +258,6 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) return -EINVAL; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [PATCH v5 05/12] net: stmmac: dwmac-stm32: Clean up the debug prints Date: Fri, 7 Jun 2024 11:57:47 +0200 Message-ID: <20240607095754.265105-6-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240607095754.265105-1-christophe.roullier@foss.st.com> References: <20240607095754.265105-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-07_04,2024-06-06_02,2024-05-17_01 X-Patchwork-Delegate: kuba@kernel.org From: Marek Vasut Use dev_err()/dev_dbg() and phy_modes() to print PHY mode instead of pr_debug() and hand-written PHY mode decoding. This way, each debug print has associated device with it and duplicated mode decoding is removed. Signed-off-by: Marek Vasut Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index aa413edd1ef71..75981ac2cbb56 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -228,19 +228,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat) switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: val = SYSCFG_PMCR_ETH_SEL_MII; - pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); break; case PHY_INTERFACE_MODE_GMII: val = SYSCFG_PMCR_ETH_SEL_GMII; if (dwmac->enable_eth_ck) val |= SYSCFG_PMCR_ETH_CLK_SEL; - pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n"); break; case PHY_INTERFACE_MODE_RMII: val = SYSCFG_PMCR_ETH_SEL_RMII; if (dwmac->enable_eth_ck) val |= SYSCFG_PMCR_ETH_REF_CLK_SEL; - pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n"); break; case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: @@ -249,15 +246,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat) val = SYSCFG_PMCR_ETH_SEL_RGMII; if (dwmac->enable_eth_ck) val |= SYSCFG_PMCR_ETH_CLK_SEL; - pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n"); break; default: - pr_debug("SYSCFG init : Do not manage %d interface\n", - plat_dat->mac_interface); + dev_err(dwmac->dev, "Mode %s not supported", + phy_modes(plat_dat->mac_interface)); /* Do not manage others interfaces */ return -EINVAL; } + dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); + /* Need to update PMCCLRR (clear register) */ regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, dwmac->ops->syscfg_eth_mask); @@ -291,19 +289,19 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: val = SYSCFG_MCU_ETH_SEL_MII; - pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); break; case PHY_INTERFACE_MODE_RMII: val = SYSCFG_MCU_ETH_SEL_RMII; - pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n"); break; default: - pr_debug("SYSCFG init : Do not manage %d interface\n", - plat_dat->mac_interface); + dev_err(dwmac->dev, "Mode %s not supported", + phy_modes(plat_dat->mac_interface)); /* Do not manage others interfaces */ return -EINVAL; } + dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); + return regmap_update_bits(dwmac->regmap, reg, dwmac->ops->syscfg_eth_mask, val << 23); } From patchwork Fri Jun 7 09:57:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13689577 X-Patchwork-Delegate: kuba@kernel.org Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DF7F157498; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [PATCH v5 06/12] net: stmmac: dwmac-stm32: Fix Mhz to MHz Date: Fri, 7 Jun 2024 11:57:48 +0200 Message-ID: <20240607095754.265105-7-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240607095754.265105-1-christophe.roullier@foss.st.com> References: <20240607095754.265105-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-07_04,2024-06-06_02,2024-05-17_01 X-Patchwork-Delegate: kuba@kernel.org From: Marek Vasut Trivial, fix up the comments using 'Mhz' to 'MHz'. No functional change. Signed-off-by: Marek Vasut Signed-off-by: Christophe Roullier --- drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index 75981ac2cbb56..bed2be129b2d2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -58,7 +58,7 @@ * Below table summarizes the clock requirement and clock sources for * supported phy interface modes. * __________________________________________________________________________ - *|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125Mhz from PHY| + *|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125MHz from PHY| *| | | 25MHz | 50MHz | | * --------------------------------------------------------------------------- *| MII | - | eth-ck | n/a | n/a | @@ -367,7 +367,7 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, /* Gigabit Ethernet 125MHz clock selection. */ dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel"); - /* Ethernet 50Mhz RMII clock selection */ + /* Ethernet 50MHz RMII clock selection */ dwmac->eth_ref_clk_sel_reg = of_property_read_bool(np, "st,eth-ref-clk-sel"); From patchwork Fri Jun 7 09:57:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13689580 X-Patchwork-Delegate: kuba@kernel.org Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCF7915D5A5; Fri, 7 Jun 2024 10:00:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717754460; cv=none; b=CdzwsVQMgIx9aJBRyLCAYVq1tumUn7NfVzhx/CD5jccFts6yO3AJxWqRn7W03rJuOmckRBLiuOvsgVplsYNz9B+ZktEwuMe+KOdImlWWuLltvbobijIzddCg2Zl63o7DMntH7va3usFK/bd3T4/pW+I5IrTZwZBoYXGltpBo6ss= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717754460; c=relaxed/simple; bh=hvam9ZzZ3n8GYR2xcTM6bOCO+wsLEhhNJ5qt5VkFFao=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tA3iSP0PauAtOkKNWyCb3/9w/3LjrQKtWXtv/aeWc1FjGOnXzJZy0OoGaRnkDi31hduSU+qIqx/dbZuVT1WznlLiUvWQqRGzyZ19aAg+BCbQCGR/QZ5BGy6f2/vZ66EqXDN1MJ1Gr1AQc6yuAqVCKEHyg9HyTEDSRwgDXt/A9EI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=WjlAm8IC; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="WjlAm8IC" Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45791lAA009506; Fri, 7 Jun 2024 12:00:31 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= hBO/8sFCkcPpRtbOEbZweOTDMZQkjBRnKwGu29CWvBY=; b=WjlAm8ICSHmsk/8u M229+clIT1cv26522ElaPt82nbcIybYt1YXZHroCZN3Y1bYqo6IkK5HAj+1UlhdL CQb95kIKGf0yBRZR4SfM9+ZAe+d2iWlVrfnRZ6kdjkCwC4mPmSAkZ7eeXn4Mspmf pVor7pCSss+IrdHGdTWhM9rqTNmEC5JxZhbX3T70T+ZAeD4hYMR2Z36+7mA/I0UZ Ydh9I+vc8SV0zU9mVTamN2lzKHXJkXvqJco0HrVkzyV+bW6AwdLAanXLs44NbEN1 OZJaUhDrLBakN011RacvV2E8E8KAVwJV4QzhAceRbAs0x/GVfzOaezYC6+s/ijIx bWdIiw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3yfw91swjf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Jun 2024 12:00:31 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id EDA7540049; Fri, 7 Jun 2024 12:00:26 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 267D8214D11; Fri, 7 Jun 2024 11:59:16 +0200 (CEST) Received: from localhost (10.252.19.205) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 7 Jun 2024 11:59:15 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [PATCH v5 07/12] net: stmmac: dwmac-stm32: Mask support for PMCR configuration Date: Fri, 7 Jun 2024 11:57:49 +0200 Message-ID: <20240607095754.265105-8-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240607095754.265105-1-christophe.roullier@foss.st.com> References: <20240607095754.265105-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-07_04,2024-06-06_02,2024-05-17_01 X-Patchwork-Delegate: kuba@kernel.org Add possibility to have second argument in syscon property to manage mask. This mask will be used to address right BITFIELDS of PMCR register. Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 28 +++++++++++++------ 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index bed2be129b2d2..96ba7bc73e823 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -90,6 +90,7 @@ struct stm32_dwmac { int eth_ref_clk_sel_reg; int irq_pwr_wakeup; u32 mode_reg; /* MAC glue-logic mode register */ + u32 mode_mask; struct regmap *regmap; u32 speed; const struct stm32_ops *ops; @@ -102,8 +103,8 @@ struct stm32_ops { void (*resume)(struct stm32_dwmac *dwmac); int (*parse_data)(struct stm32_dwmac *dwmac, struct device *dev); - u32 syscfg_eth_mask; bool clk_rx_enable_in_suspend; + u32 syscfg_clr_off; }; static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac, bool resume) @@ -256,13 +257,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat) dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); + /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */ + val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK); + /* Need to update PMCCLRR (clear register) */ - regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, - dwmac->ops->syscfg_eth_mask); + regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off, + dwmac->mode_mask); /* Update PMCSETR (set register) */ return regmap_update_bits(dwmac->regmap, reg, - dwmac->ops->syscfg_eth_mask, val); + dwmac->mode_mask, val); } static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) @@ -303,7 +307,7 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); return regmap_update_bits(dwmac->regmap, reg, - dwmac->ops->syscfg_eth_mask, val << 23); + SYSCFG_MCU_ETH_MASK, val << 23); } static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac, bool suspend) @@ -348,8 +352,15 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac, return PTR_ERR(dwmac->regmap); err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg); - if (err) + if (err) { dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err); + return err; + } + + dwmac->mode_mask = SYSCFG_MP1_ETH_MASK; + err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask); + if (err) + pr_debug("Warning sysconfig register mask not set\n"); return err; } @@ -540,8 +551,7 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops, stm32_dwmac_suspend, stm32_dwmac_resume); static struct stm32_ops stm32mcu_dwmac_data = { - .set_mode = stm32mcu_set_mode, - .syscfg_eth_mask = SYSCFG_MCU_ETH_MASK + .set_mode = stm32mcu_set_mode }; static struct stm32_ops stm32mp1_dwmac_data = { @@ -549,7 +559,7 @@ static struct stm32_ops stm32mp1_dwmac_data = { .suspend = stm32mp1_suspend, .resume = stm32mp1_resume, .parse_data = stm32mp1_parse_data, - .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK, + .syscfg_clr_off = 0x44, .clk_rx_enable_in_suspend = true }; From patchwork Fri Jun 7 09:57:50 2024 Content-Type: text/plain; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [PATCH v5 08/12] net: stmmac: dwmac-stm32: add management of stm32mp13 for stm32 Date: Fri, 7 Jun 2024 11:57:50 +0200 Message-ID: <20240607095754.265105-9-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240607095754.265105-1-christophe.roullier@foss.st.com> References: <20240607095754.265105-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-07_04,2024-06-06_02,2024-05-17_01 X-Patchwork-Delegate: kuba@kernel.org Add Ethernet support for STM32MP13. STM32MP13 is STM32 SOC with 2 GMACs instances. GMAC IP version is SNPS 4.20. GMAC IP configure with 1 RX and 1 TX queue. DMA HW capability register supported RX Checksum Offload Engine supported TX Checksum insertion supported Wake-Up On Lan supported TSO supported Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 24 +++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index 96ba7bc73e823..064f73cbe3b45 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -104,6 +104,7 @@ struct stm32_ops { int (*parse_data)(struct stm32_dwmac *dwmac, struct device *dev); bool clk_rx_enable_in_suspend; + bool is_mp13; u32 syscfg_clr_off; }; @@ -224,11 +225,18 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat) { struct stm32_dwmac *dwmac = plat_dat->bsp_priv; u32 reg = dwmac->mode_reg; - int val; + int val = 0; switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: - val = SYSCFG_PMCR_ETH_SEL_MII; + /* + * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only. + * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and + * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx + * supports only MII, ETH_SELMII is not present. + */ + if (!dwmac->ops->is_mp13) /* Select MII mode on STM32MP15xx */ + val |= SYSCFG_PMCR_ETH_SEL_MII; break; case PHY_INTERFACE_MODE_GMII: val = SYSCFG_PMCR_ETH_SEL_GMII; @@ -560,12 +568,24 @@ static struct stm32_ops stm32mp1_dwmac_data = { .resume = stm32mp1_resume, .parse_data = stm32mp1_parse_data, .syscfg_clr_off = 0x44, + .is_mp13 = false, + .clk_rx_enable_in_suspend = true +}; + +static struct stm32_ops stm32mp13_dwmac_data = { + .set_mode = stm32mp1_set_mode, + .suspend = stm32mp1_suspend, + .resume = stm32mp1_resume, + .parse_data = stm32mp1_parse_data, + .syscfg_clr_off = 0x08, + .is_mp13 = true, .clk_rx_enable_in_suspend = true }; static const struct of_device_id stm32_dwmac_match[] = { { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data}, { .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data}, + { .compatible = "st,stm32mp13-dwmac", .data = &stm32mp13_dwmac_data}, { } }; MODULE_DEVICE_TABLE(of, stm32_dwmac_match); From patchwork Fri Jun 7 09:57:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13689578 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26D3115749A; Fri, 7 Jun 2024 10:00:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717754459; cv=none; b=k0c3z+v5//iTh8JdUMevEsE+LGGxwunqtxfn3v4JYxoCUTBuoWzVqaiMFGFKrQMlBh5ta6NSCA2Pj4a8PWmtg06LFsQ5iixfRHnA9d6u0baoSclY3OVmOb9QVxcdOo7tbotW1sKUgCyVZ958utJtIZoW7LwUwTMNuv5ilJb1QLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717754459; c=relaxed/simple; bh=LxdLgGqPLf3s+kJUNXVv8BMrS7yHp/8IVNCuj2Iw0i4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ePDcY86tBiWU6Cq9f3rPL5hYBo9eJj4UesuJ6Qbb8e/Iks7JXM3Id72iUdBvGHCKozEydvPGLqq2YUthdp4cWV4znzZG5c4uPF371QDu2yC1fRm5JddQUpni+Pv/j4b/OB/cv7oYeHZagYxBeXibaOBa4wMr1oVNK3Mm0XTLPlE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=WJ7M78dp; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="WJ7M78dp" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45791dBJ002305; Fri, 7 Jun 2024 12:00:35 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= I5eX1MiABAjtTHnD8DpDo4CymvKlEhXxzp8S24yq7DA=; b=WJ7M78dp/FboYY7x k+ktG3Zxr1+h2Rb89+cuENHIKhWeCbpsz/3fmHL2LdyyZ8dcocNOygIYhc7iB7CF 730ysypsoRx1TnDv1VCSGqS4/bWVJqeR8NI/atQjU2jayD2GIT6cdvZ+KLwetRnq 9No1oAyDbKKvQ8e5PBt19VVh0iLSQsyas2TGTUDPvEXQOBBSFuSGjxP80wXuASfk znGaKzmI8Tb0i6guNCDcMXipdsau1mcnJcv6EbdJlSAY+RLAQOH8DvIjSSYjFBVh rQ10wN9sERMXn30Bexrvgkm8V9iuu3T/ATZMhjxPmCdp2Jgdh6aDM+Fkr5ZNSKj8 pzTe1Q== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ygekj86cu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Jun 2024 12:00:35 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id F0E5140045; Fri, 7 Jun 2024 12:00:30 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 24D76214D14; Fri, 7 Jun 2024 11:59:18 +0200 (CEST) Received: from localhost (10.252.19.205) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 7 Jun 2024 11:59:17 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [PATCH v5 09/12] ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13 Date: Fri, 7 Jun 2024 11:57:51 +0200 Message-ID: <20240607095754.265105-10-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240607095754.265105-1-christophe.roullier@foss.st.com> References: <20240607095754.265105-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-07_04,2024-06-06_02,2024-05-17_01 Both instances ethernet based on GMAC SNPS IP on stm32mp13. GMAC IP version is SNPS 4.20. Signed-off-by: Christophe Roullier --- arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp133.dtsi | 31 +++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 6704ceef284d3..e1a764d269d27 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -979,6 +979,12 @@ ts_cal1: calib@5c { ts_cal2: calib@5e { reg = <0x5e 0x2>; }; + ethernet_mac1_address: mac1@e4 { + reg = <0xe4 0x6>; + }; + ethernet_mac2_address: mac2@ea { + reg = <0xea 0x6>; + }; }; etzpc: bus@5c007000 { @@ -1505,6 +1511,38 @@ sdmmc2: mmc@58007000 { status = "disabled"; }; + ethernet1: ethernet@5800a000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <&exti 68 1>; + interrupt-names = "macirq", "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH1MAC>, + <&rcc ETH1TX>, + <&rcc ETH1RX>, + <&rcc ETH1STP>, + <&rcc ETH1CK_K>; + st,syscon = <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,tso; + access-controllers = <&etzpc 48>; + status = "disabled"; + + stmmac_axi_config_1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; + usbphyc: usbphyc@5a006000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index 3e394c8e58b92..73e470019ce42 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -68,4 +68,35 @@ channel@18 { }; }; }; + + ethernet2: ethernet@5800e000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800e000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH2MAC>, + <&rcc ETH2TX>, + <&rcc ETH2RX>, + <&rcc ETH2STP>, + <&rcc ETH2CK_K>; + st,syscon = <&syscfg 0x4 0xff000000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_2>; + snps,tso; + access-controllers = <&etzpc 49>; + status = "disabled"; + + stmmac_axi_config_2: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; }; From patchwork Fri Jun 7 09:57:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13689596 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33BDC15B97B; Fri, 7 Jun 2024 10:02:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [PATCH v5 10/12] ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board Date: Fri, 7 Jun 2024 11:57:52 +0200 Message-ID: <20240607095754.265105-11-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240607095754.265105-1-christophe.roullier@foss.st.com> References: <20240607095754.265105-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-07_04,2024-06-06_02,2024-05-17_01 Those pins are used for Ethernet 1 and 2 on STM32MP13F-DK board. ethernet1: RMII with crystal. ethernet2: RMII without crystal. Add analog gpio pin configuration ("sleep") to manage power mode on stm32mp13. Signed-off-by: Christophe Roullier --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 71 +++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 32c5d8a1e06ac..7f72c62da0a64 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -13,6 +13,77 @@ pins { }; }; + eth1_rmii_pins_a: eth1-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + + }; + + eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + + eth2_rmii_pins_a: eth2-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_ETHCK */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + }; + + eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_ETHCK */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ From patchwork Fri Jun 7 09:57:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13689597 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C557415E5DD; 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Fri, 07 Jun 2024 12:01:50 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 80ECF40047; Fri, 7 Jun 2024 12:01:46 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A08C2214D12; Fri, 7 Jun 2024 12:00:32 +0200 (CEST) Received: from localhost (10.252.19.205) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 7 Jun 2024 12:00:29 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [PATCH v5 11/12] ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board Date: Fri, 7 Jun 2024 11:57:53 +0200 Message-ID: <20240607095754.265105-12-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240607095754.265105-1-christophe.roullier@foss.st.com> References: <20240607095754.265105-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-07_04,2024-06-06_02,2024-05-17_01 Ethernet1: RMII with crystal Ethernet2: RMII with no cristal, need "phy-supply" property to work, today this property was managed by Ethernet glue, but should be present and managed in PHY node. So I will push second Ethernet in next step. PHYs used are SMSC (LAN8742A) Signed-off-by: Christophe Roullier --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 567e53ad285fa..16e91b9d812d8 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -19,6 +19,7 @@ / { compatible = "st,stm32mp135f-dk", "st,stm32mp135"; aliases { + ethernet0 = ðernet1; serial0 = &uart4; serial1 = &usart1; serial2 = &uart8; @@ -141,6 +142,28 @@ &cryp { status = "okay"; }; +ðernet1 { + status = "okay"; + pinctrl-0 = <ð1_rmii_pins_a>; + pinctrl-1 = <ð1_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + phy-handle = <&phy0_eth1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0_eth1: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c131"; + reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>; + reg = <0>; + wakeup-source; + }; + }; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; From patchwork Fri Jun 7 09:57:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13689595 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B71115CD60; Fri, 7 Jun 2024 10:02:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717754530; cv=none; b=VWOazvK133xRJ6h6oY9GL1abKkvMybc6iQiCcvnJELcqxzTOYiEnc9xJ7sHs4OuE4KsNEBXvLbdIfLXL2knz8upfNdYmwnaATkCPDfJymR+tkM/0qLXUDX7DGPn3VBpi4AWBiCTrUDGIBTO8Krw51nfN3uZFU0t61FdQAGAmfNg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717754530; c=relaxed/simple; bh=PZjolXkinsbKkJg9D0xyN5Zm4GveXBTXlg8QiZ+N76E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EdsPLpXPoMvQmcijk/+KYJneUnPx9RDn4ONzF9wIwoH2FG+4qnQ+FmhmrxFsde2KHf6xh6emF2+JmcHEUg1zHJozv8SLZGl2xvqGrMjuNoTcKxx4rr9ETe1AN7CNLsA09N1nb+lnmIcQcgdLCHknGEhcJpKhOzbLYy76YpYAUKk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=JRN9cvXF; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="JRN9cvXF" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45791KNp010973; Fri, 7 Jun 2024 12:01:45 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= S/2VyWKkGuX5P0YCLDqxzItg9oxgZQDLFxM7j2pGY+s=; b=JRN9cvXFdKNaC884 F2zSuLB9I72sUNszwoJ1T9DZAhRv41y/wv/6nRYYaQXPGfilGqTBCjlGQwArcCsj 40rZzvUZJm6J5t4F28O1wmMIsHoA6bEOfD5nkob/Sww0b5bi5YSv01Nah/rjKfwy GbALkEZhuQXdb0XKK7M9Qtd43pMMscshC0vQOgvaiSi6sAfM5Lw//IW8EG+TLpQi +z986ArkPngK5Bj1d/AMFdkV2VoEVCm7IEeJNADYBX8SfR354l0MgbwJk0dWADyo Um9z0g9qzXZK1bBcs5U/fIJMIsbtToabR+fqmNda/WBVpqEbWzo6RqFa5o4AHsD1 AhsCtg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3yg7r0gxj2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Jun 2024 12:01:45 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C364F40044; Fri, 7 Jun 2024 12:01:41 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E8F61214D16; Fri, 7 Jun 2024 12:00:30 +0200 (CEST) Received: from localhost (10.252.19.205) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 7 Jun 2024 12:00:30 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [PATCH v5 12/12] ARM: multi_v7_defconfig: Add MCP23S08 pinctrl support Date: Fri, 7 Jun 2024 11:57:54 +0200 Message-ID: <20240607095754.265105-13-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240607095754.265105-1-christophe.roullier@foss.st.com> References: <20240607095754.265105-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-07_04,2024-06-06_02,2024-05-17_01 Enable MCP23S08 I/O expanders to manage Ethernet phy reset in STM32MP135F-DK board. Signed-off-by: Christophe Roullier --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 86bf057ac3663..9758f3d41ad70 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -469,6 +469,7 @@ CONFIG_SPI_XILINX=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y CONFIG_PINCTRL_AS3722=y +CONFIG_PINCTRL_MCP23S08=y CONFIG_PINCTRL_MICROCHIP_SGPIO=y CONFIG_PINCTRL_OCELOT=y CONFIG_PINCTRL_PALMAS=y