From patchwork Fri Jun 7 10:38:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiong Yining X-Patchwork-Id: 13689669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6CDFC27C53 for ; Fri, 7 Jun 2024 10:40:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sFX04-00055o-3w; Fri, 07 Jun 2024 06:39:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sFX00-00054z-Ky; Fri, 07 Jun 2024 06:39:08 -0400 Received: from sgoci-sdnproxy-4.icoremail.net ([129.150.39.64]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sFWzy-0002aW-L0; Fri, 07 Jun 2024 06:39:08 -0400 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwBHIMNB42JmK0UNAA--.5824S2; Fri, 07 Jun 2024 18:38:57 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwA34tc742JmSdwAAA--.1309S4; Fri, 07 Jun 2024 18:38:56 +0800 (CST) From: Xiong Yining To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: rad@semihalf.com, peter.maydell@linaro.org, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, Xiong Yining Subject: [PATCH v5 1/1] hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine Date: Fri, 7 Jun 2024 10:38:25 +0000 Message-Id: <20240607103825.1295328-2-xiongyining1480@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240607103825.1295328-1-xiongyining1480@phytium.com.cn> References: <20240607103825.1295328-1-xiongyining1480@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAfwA34tc742JmSdwAAA--.1309S4 X-CM-SenderInfo: x0lr0wp1lqx0bjrumio6sk53xlxphulrpou0/1tbiAQAJBmZiD2QErQAAsI Authentication-Results: hzbj-icmmx-6; spf=neutral smtp.mail=xiongyinin g1480@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvJXoWxZw13Ww1DGF43Zr45tr4UXFb_yoW5Gw1DpF 48Cr97CrWxurn0yr43W3WxuFyrJw4Fqw42kw47Gws3u3s8Jw1xWF4Ut34FkF1UWr18uFyY vF4DAr9xuFn2vrJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Received-SPF: pass client-ip=129.150.39.64; envelope-from=xiongyining1480@phytium.com.cn; helo=sgoci-sdnproxy-4.icoremail.net X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL=1.31, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Enable CPU cluster support on SbsaQemu platform, so that users can specify a 4-level CPU hierarchy sockets/clusters/cores/threads. And this topology can be passed to the firmware through /cpus/topology Device Tree. Signed-off-by: Xiong Yining tested-by: Marcin Juszkiewicz Reviewed-by: Marcin Juszkiewicz Reviewed-by: Leif Lindholm --- docs/system/arm/sbsa.rst | 4 ++++ hw/arm/sbsa-ref.c | 11 ++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst index 2bf22a1d0b..2bf3fc8d59 100644 --- a/docs/system/arm/sbsa.rst +++ b/docs/system/arm/sbsa.rst @@ -62,6 +62,7 @@ The devicetree reports: - platform version - GIC addresses - NUMA node id for CPUs and memory + - CPU topology information Platform version '''''''''''''''' @@ -88,3 +89,6 @@ Platform version changes: 0.3 The USB controller is an XHCI device, not EHCI. + +0.4 + CPU topology information is present in devicetree. diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index e884692f07..9987850fc4 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -223,7 +223,7 @@ static void create_fdt(SBSAMachineState *sms) * fw compatibility. */ qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); - qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); + qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 4); if (ms->numa_state->have_numa_distance) { int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); @@ -280,6 +280,14 @@ static void create_fdt(SBSAMachineState *sms) g_free(nodename); } + /* Add CPU topology description through fdt node topology. */ + qemu_fdt_add_subnode(sms->fdt, "/cpus/topology"); + + qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "sockets", ms->smp.sockets); + qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "clusters", ms->smp.clusters); + qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "cores", ms->smp.cores); + qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "threads", ms->smp.threads); + sbsa_fdt_add_gic_node(sms); } @@ -902,6 +910,7 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 1 * GiB; mc->default_ram_id = "sbsa-ref.ram"; mc->default_cpus = 4; + mc->smp_props.clusters_supported = true; mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id;