From patchwork Fri Jun 7 10:55:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beleswar Prasad Padhi X-Patchwork-Id: 13689684 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02EADC27C53 for ; Fri, 7 Jun 2024 10:56:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=7yMraCHzXKF6GqeWH+6zXL37FbtvBv/zG+mFCZrKhRw=; b=YrF7nIdA2ItW0D nMmJMYnGSYWnHPnATxmrcQvUqLZfY3O6JSX2/U9VosAlwJNP1kPdWQAMxqYcTXoSIl1R1Bdgfl87U qoxX0ywXz20Kq6kK7MC4juhd6g/bGdGwnnGR3MJPTgLxhW5sWXoeXRW8AofVkb/zCL3wRAbv/1EEk KjXCA3jFJM7sL1bzK7FKSh4JqntrU/OQIzMlQBu45nQVmA8AJv5Qq07gK8uL2B/7nsvdK8IXOmSLE phfcgiszusJSixp3P/VzuHG+CjLxs6uH6WQ4YvLgJheGOOs9UBnwv5x4b6vt+NyQUE8TIE9/m3Hef zF7wTxsbACThwnXwBBcg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFXGa-0000000DcD5-0Vdi; Fri, 07 Jun 2024 10:56:16 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFXGX-0000000DcC3-1Rul for linux-arm-kernel@lists.infradead.org; Fri, 07 Jun 2024 10:56:15 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 457Au3GT067900; Fri, 7 Jun 2024 05:56:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1717757763; bh=a5GAfS7C0Tj1XfUzuRZMBoPPEFIo9QtsKjJsgSeV/9k=; h=From:To:CC:Subject:Date; b=mYzvl6HARgzoK2WyuRNbgqzRjlGFvAXndX6jNlfEvwCc6uZD/YHfSfFieMJpb5ElB n5f2pSuPjJkLzWpjMPA8Ifjf8sNSYgG875YXn/7pVIMCMz3j+lbdKGDyrv9NAa1jAl 9ys2ihkjtPxDG2ctYfX6FT8RWL81eFSOGBv79ca8= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 457Au3Kq125057 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 7 Jun 2024 05:56:03 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 7 Jun 2024 05:56:03 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 7 Jun 2024 05:56:03 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [10.24.69.66]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 457AtxSV129722; Fri, 7 Jun 2024 05:56:00 -0500 From: Beleswar Padhi To: , CC: , , , , , , , , Subject: [PATCH] arm64: dts: ti: k3-j7xx: Change timer nodes status to reserved Date: Fri, 7 Jun 2024 16:25:59 +0530 Message-ID: <20240607105559.771080-1-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240607_035613_685252_8529283B X-CRM114-Status: UNSURE ( 8.75 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The remoteproc firmware like of R5F and DSPs in the MAIN voltage domain use timers. Therefore, change the status of the timer nodes to "reserved" to avoid any clash. This change is already incorporated for timer nodes in the MCU voltage domain. Fixes: 835d04422f9d ("arm64: dts: ti: k3-j721s2: Add general purpose timers") Signed-off-by: Beleswar Padhi --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 7 +++++++ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 10 ++++++++++ 4 files changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 9386bf3ef9f68..22351a4f3da6e 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -1254,6 +1254,7 @@ main_timer0: timer@2400000 { assigned-clock-parents = <&k3_clks 49 2>; power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer1: timer@2410000 { @@ -1266,6 +1267,7 @@ main_timer1: timer@2410000 { assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer2: timer@2420000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 0da785be80ff4..944bdbb98e910 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1102,6 +1102,7 @@ main_timer0: timer@2400000 { assigned-clock-parents = <&k3_clks 49 2>; power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer1: timer@2410000 { @@ -1114,6 +1115,7 @@ main_timer1: timer@2410000 { assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>; power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer2: timer@2420000 { @@ -1126,6 +1128,7 @@ main_timer2: timer@2420000 { assigned-clock-parents = <&k3_clks 51 2>; power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer3: timer@2430000 { @@ -1246,6 +1249,7 @@ main_timer12: timer@24c0000 { assigned-clock-parents = <&k3_clks 63 2>; power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer13: timer@24d0000 { @@ -1258,6 +1262,7 @@ main_timer13: timer@24d0000 { assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>; power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer14: timer@24e0000 { @@ -1270,6 +1275,7 @@ main_timer14: timer@24e0000 { assigned-clock-parents = <&k3_clks 65 2>; power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer15: timer@24f0000 { @@ -1282,6 +1288,7 @@ main_timer15: timer@24f0000 { assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>; power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer16: timer@2500000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 9ed6949b40e9d..c8e49454bd9b0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -225,6 +225,7 @@ main_timer0: timer@2400000 { assigned-clock-parents = <&k3_clks 63 2>; power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer1: timer@2410000 { @@ -237,6 +238,7 @@ main_timer1: timer@2410000 { assigned-clock-parents = <&k3_clks 64 2>; power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer2: timer@2420000 { @@ -249,6 +251,7 @@ main_timer2: timer@2420000 { assigned-clock-parents = <&k3_clks 65 2>; power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer3: timer@2430000 { @@ -261,6 +264,7 @@ main_timer3: timer@2430000 { assigned-clock-parents = <&k3_clks 66 2>; power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer4: timer@2440000 { @@ -273,6 +277,7 @@ main_timer4: timer@2440000 { assigned-clock-parents = <&k3_clks 67 2>; power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer5: timer@2450000 { @@ -285,6 +290,7 @@ main_timer5: timer@2450000 { assigned-clock-parents = <&k3_clks 68 2>; power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer6: timer@2460000 { diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 6a4554c6c9c13..d62859c52514e 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -170,6 +170,7 @@ main_timer0: timer@2400000 { assigned-clock-parents = <&k3_clks 97 3>; power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer1: timer@2410000 { @@ -182,6 +183,7 @@ main_timer1: timer@2410000 { assigned-clock-parents = <&k3_clks 98 3>; power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer2: timer@2420000 { @@ -194,6 +196,7 @@ main_timer2: timer@2420000 { assigned-clock-parents = <&k3_clks 99 3>; power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer3: timer@2430000 { @@ -206,6 +209,7 @@ main_timer3: timer@2430000 { assigned-clock-parents = <&k3_clks 100 3>; power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer4: timer@2440000 { @@ -218,6 +222,7 @@ main_timer4: timer@2440000 { assigned-clock-parents = <&k3_clks 101 3>; power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer5: timer@2450000 { @@ -230,6 +235,7 @@ main_timer5: timer@2450000 { assigned-clock-parents = <&k3_clks 102 3>; power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer6: timer@2460000 { @@ -242,6 +248,7 @@ main_timer6: timer@2460000 { assigned-clock-parents = <&k3_clks 103 3>; power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer7: timer@2470000 { @@ -254,6 +261,7 @@ main_timer7: timer@2470000 { assigned-clock-parents = <&k3_clks 104 3>; power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer8: timer@2480000 { @@ -266,6 +274,7 @@ main_timer8: timer@2480000 { assigned-clock-parents = <&k3_clks 105 3>; power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer9: timer@2490000 { @@ -278,6 +287,7 @@ main_timer9: timer@2490000 { assigned-clock-parents = <&k3_clks 106 3>; power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + status = "reserved"; }; main_timer10: timer@24a0000 {