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Fri, 7 Jun 2024 13:25:06 +0000 From: "Peng Fan (OSS)" To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com Cc: imx@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan , Ye Li , Jacky Bai Subject: [PATCH V3 01/15] clk: imx: composite-8m: Enable gate clk with mcore_booted Date: Fri, 7 Jun 2024 21:33:33 +0800 Message-Id: <20240607133347.3291040-2-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20240607133347.3291040-1-peng.fan@oss.nxp.com> References: <20240607133347.3291040-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI1PR02CA0046.apcprd02.prod.outlook.com (2603:1096:4:1f5::14) To DB7PR04MB5948.eurprd04.prod.outlook.com (2603:10a6:10:8b::21) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB5941:EE_|PAXPR04MB8944:EE_ X-MS-Office365-Filtering-Correlation-Id: f2ba165b-7886-4d9a-28ce-08dc86f53e97 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|52116005|376005|7416005|366007|38350700005; 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So if mcore_booted set with display CCM ROOT disabled by Bootloader, kernel display BLK CTRL driver imx8m_blk_ctrl_driver_init may hang the system because the BUS clk is disabled. Add back gate ops, but with disable doing nothing, then the CCM ROOT will be enabled when used. Fixes: bb7e897b002a ("clk: imx8m: check mcore_booted before register clk") Reviewed-by: Ye Li Reviewed-by: Jacky Bai Signed-off-by: Peng Fan --- drivers/clk/imx/clk-composite-8m.c | 53 +++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 11 deletions(-) diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index 8cc07d056a83..f187582ba491 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -204,6 +204,34 @@ static const struct clk_ops imx8m_clk_composite_mux_ops = { .determine_rate = imx8m_clk_composite_mux_determine_rate, }; +static int imx8m_clk_composite_gate_enable(struct clk_hw *hw) +{ + struct clk_gate *gate = to_clk_gate(hw); + unsigned long flags; + u32 val; + + spin_lock_irqsave(gate->lock, flags); + + val = readl(gate->reg); + val |= BIT(gate->bit_idx); + writel(val, gate->reg); + + spin_unlock_irqrestore(gate->lock, flags); + + return 0; +} + +static void imx8m_clk_composite_gate_disable(struct clk_hw *hw) +{ + /* composite clk requires the disable hook */ +} + +static const struct clk_ops imx8m_clk_composite_gate_ops = { + .enable = imx8m_clk_composite_gate_enable, + .disable = imx8m_clk_composite_gate_disable, + .is_enabled = clk_gate_is_enabled, +}; + struct clk_hw *__imx8m_clk_hw_composite(const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, @@ -217,6 +245,7 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, struct clk_mux *mux; const struct clk_ops *divider_ops; const struct clk_ops *mux_ops; + const struct clk_ops *gate_ops; mux = kzalloc(sizeof(*mux), GFP_KERNEL); if (!mux) @@ -257,20 +286,22 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, div->flags = CLK_DIVIDER_ROUND_CLOSEST; /* skip registering the gate ops if M4 is enabled */ - if (!mcore_booted) { - gate = kzalloc(sizeof(*gate), GFP_KERNEL); - if (!gate) - goto free_div; - - gate_hw = &gate->hw; - gate->reg = reg; - gate->bit_idx = PCG_CGC_SHIFT; - gate->lock = &imx_ccm_lock; - } + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + goto free_div; + + gate_hw = &gate->hw; + gate->reg = reg; + gate->bit_idx = PCG_CGC_SHIFT; + gate->lock = &imx_ccm_lock; + if (!mcore_booted) + gate_ops = &clk_gate_ops; + else + gate_ops = &imx8m_clk_composite_gate_ops; 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Fri, 7 Jun 2024 13:25:11 +0000 From: "Peng Fan (OSS)" To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com Cc: imx@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jacky Bai , Peng Fan , Chancel Liu Subject: [PATCH V3 02/15] clk: imx: composite-93: keep root clock on when mcore enabled Date: Fri, 7 Jun 2024 21:33:34 +0800 Message-Id: <20240607133347.3291040-3-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20240607133347.3291040-1-peng.fan@oss.nxp.com> References: <20240607133347.3291040-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI1PR02CA0046.apcprd02.prod.outlook.com (2603:1096:4:1f5::14) To DB7PR04MB5948.eurprd04.prod.outlook.com (2603:10a6:10:8b::21) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB5941:EE_|PAXPR04MB8944:EE_ X-MS-Office365-Filtering-Correlation-Id: f23d632d-46a8-4641-268f-08dc86f541e9 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|52116005|376005|7416005|366007|38350700005; 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But the bootloader may disable the clocks before jump into kernel. The gate ops should be registered rather than NULL to make sure the disabled clock can be enabled when kernel boot up. Refine the code to skip disable the clock if mcore booted. Fixes: a740d7350ff7 ("clk: imx: imx93: add mcore_booted module paratemter") Signed-off-by: Jacky Bai Reviewed-by: Peng Fan Tested-by: Chancel Liu Signed-off-by: Peng Fan --- drivers/clk/imx/clk-composite-93.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c index 81164bdcd6cc..6c6c5a30f328 100644 --- a/drivers/clk/imx/clk-composite-93.c +++ b/drivers/clk/imx/clk-composite-93.c @@ -76,6 +76,13 @@ static int imx93_clk_composite_gate_enable(struct clk_hw *hw) static void imx93_clk_composite_gate_disable(struct clk_hw *hw) { + /* + * Skip disable the root clock gate if mcore enabled. + * The root clock may be used by the mcore. + */ + if (mcore_booted) + return; + imx93_clk_composite_gate_endisable(hw, 0); } @@ -222,7 +229,7 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux_hw, &clk_mux_ro_ops, div_hw, &clk_divider_ro_ops, NULL, NULL, flags); - } else if (!mcore_booted) { + } else { gate = kzalloc(sizeof(*gate), GFP_KERNEL); if (!gate) goto fail; @@ -238,12 +245,6 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p &imx93_clk_composite_divider_ops, gate_hw, &imx93_clk_composite_gate_ops, flags | CLK_SET_RATE_NO_REPARENT); - } else { - hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, - mux_hw, &imx93_clk_composite_mux_ops, div_hw, - &imx93_clk_composite_divider_ops, NULL, - &imx93_clk_composite_gate_ops, - flags | CLK_SET_RATE_NO_REPARENT); } if (IS_ERR(hw)) From patchwork Fri Jun 7 13:33:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13689946 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2055.outbound.protection.outlook.com [40.107.21.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D93511993A9; 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Any write to this PCC will cause SError. Fixes: b40ba8065347 ("clk: imx: Update the compsite driver to support imx8ulp") Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/clk/imx/clk-composite-7ulp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c index e208ddc51133..db7f40b07d1a 100644 --- a/drivers/clk/imx/clk-composite-7ulp.c +++ b/drivers/clk/imx/clk-composite-7ulp.c @@ -14,6 +14,7 @@ #include "../clk-fractional-divider.h" #include "clk.h" +#define PCG_PR_MASK BIT(31) #define PCG_PCS_SHIFT 24 #define PCG_PCS_MASK 0x7 #define PCG_CGC_SHIFT 30 @@ -78,6 +79,12 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name, struct clk_hw *hw; u32 val; + val = readl(reg); + if (!(val & PCG_PR_MASK)) { + pr_info("PCC PR is 0 for clk:%s, bypass\n", name); + return 0; + } + if (mux_present) { mux = kzalloc(sizeof(*mux), GFP_KERNEL); if (!mux) From patchwork Fri Jun 7 13:33:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13689947 Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-ve1eur01on2052.outbound.protection.outlook.com [40.107.14.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21A18199E85; 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Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Pengfei Li Reviewed-by: Jacky Bai Signed-off-by: Peng Fan --- drivers/clk/imx/clk-fracn-gppll.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index 44462ab50e51..1becba2b62d0 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -291,6 +291,10 @@ static int clk_fracn_gppll_prepare(struct clk_hw *hw) if (val & POWERUP_MASK) return 0; + if (pll->flags & CLK_FRACN_GPPLL_FRACN) + writel_relaxed(readl_relaxed(pll->base + PLL_NUMERATOR), + pll->base + PLL_NUMERATOR); + val |= CLKMUX_BYPASS; writel_relaxed(val, pll->base + PLL_CTRL); From patchwork Fri Jun 7 13:33:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13689948 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2055.outbound.protection.outlook.com [40.107.20.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04A04199222; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: o06Keee4RH+jymJcXcwYT1+twmN5q7Ae0Fx/w5MNY5GwPx451RMUGj4swiI0ff0cw72ljw3GFJE7AjmpJ33c0eXChX8KB73Jgh7is12+xO6SgiUqpNYZMcZNMDebx2ew7unTd07P91UeR1DiqY/iC7jyzf3zfGY2hTe7KRKgY9UDcyYFRgl2TXVn416ZyPYSNWTVeYaq/11a9I0BE3mcG/KYDrif4r2fea9lbrzOFqhJOqyMBD4rIct4aC1npqEDz3R90U4gyH+2niVkiCSbByi5BfiOWCeSDmkH6ef970Cld9hlsLPHmFAGkdRaaaZVKz0oQyaLDSX/Mfjylt7rKJpZW0XL92Yfj+aP1np81BHGf0ae0EZ2k2qz1NbmDEUQHXxYH40nsxL0H7MF+JgWgvIA5bIhvCNzlBKSa1gVvZdH9Xbuf0aLIhrBKu7KH2PS+35sask043HYlCDy0cbaPJNVMd9tFYzdJxIMwKvVL+tCfOX5zl4wot4gsRiwZMwzVtkucWVegUeNqAU2hgeRGoaEfQ0Mx07IJXFNIhYPy34NOAdj7JgFW3/3J4AHvUAtpSKaiKnqTLMtbwRW88qpgUZBAS5GfTsVItKpahhAzE8AdFzXoiCzsKueCQ2/Dja1eJ1Z5Y6jYGME35wv14smBIvGj2L/An3S+hmtYqozQIaflKvRwNMLrAZPt9VuTvZYPdmA9cGq9oP0/0EJGJPDQdAKVnuQYC8oz/vtGvVf9mv/v+UMr8F1IsvP0pke9JDZ7zs96x7TAy7DmIDzCnVU3ePZ88ZYxGk1jMuu0XhoKt1Wx2xe71VNh5NKqWmcFAWV8M9hEZugx+IsB7Daw4b3m+s4gPmZ3MaOU73fqhBKPLsP4tNyEt6WITRnio5xN4QTblMUca0xonSoOnCz7g8erqBQQ3h7Vb+LrykCTVXI1J16WjaUvi9OwNbcAZVsyOD5YSUYxwAr/5RGVbe7oQi1CmQ7XYyAj4vzDRQ2pt4H0ZgyX6Pjzk/xrwIEb58MByfkvjfCbs2QyLmUDherawCijPP6ZLKftXQQe7yrqplK63/T9KM9hqOrCLvMjsoFR48gR0ISGR5gVw8F1H/h6tyTbjvPvEQZMXvbonBvzlOj092yZQNat+ZTrxzMe3gQbqU/oiymoQ3wO+YrVlRKdLX0w2ulUK9T2cpL9mBxloIdH8RFloumIoq12MaM1zyZRCy22bFlru/QQ26Ao0sWzxibYnhgEAW5AQLnA4G+Z1oiWl51WQGY0YwrLeC4pMbXSz2t80AYdmfZV2axGQJnsy6lIr63PAb/uOfou2ImqsyL5tLSccGqdah8iG4gCwqlwkb5MKo6Qt0EALhfYkub3oDxErNF2lCM2WMBvhFcotIF2loTstbWpxbQVVWeQ++q3p0SdmYyM1KovYVxIDk7dOXpuU4c4Y3fNMixzd8Oh+zK9wMNx3wBcOZb7bU1ypAu4Lsy+J2X143q4fbr9KMqB+mzvGmursb/MIPVadzkuCuq1sdSe51Cz7HAVnWGrp9YhqnaMDbhM/6w2uNlCxITtuSN/buLsqnXb6P4KY1vLFkr/5NXV4yflKvrX+LJKeucV44d X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 890edf75-0b63-41e9-6119-08dc86f54b8a X-MS-Exchange-CrossTenant-AuthSource: DB7PR04MB5948.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2024 13:25:27.7806 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: IeET6vyhCg/uNcVES5TbfnbcJ8b4BTIDyb6lmr4RUEBdKVIW1vY3ia57IhXUhpg+VrNoxZdoGVjtRnx67x35cQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR04MB9249 From: Peng Fan There is an issue: SDMA3 can't work without setting AUDIOMIX_CLKEN0[SDMA2] (bit-26) to 1 The workaround is: As the reset state of AUDIOMIX_CLKEN0[SDMA2] is enabled, we just need to keep it on as reset state, don't touch it in kernel, then every thing is same as before, if we register the clock in clk-audiomix, then kernel will try to disable it in idle. Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block control") Reviewed-by: Shengjiu Wang Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8mp-audiomix.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c index b381d6f784c8..88d8ba975b5a 100644 --- a/drivers/clk/imx/clk-imx8mp-audiomix.c +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c @@ -172,7 +172,6 @@ static struct clk_imx8mp_audiomix_sel sels[] = { CLK_GATE("ocrama", OCRAMA_IPG), CLK_GATE("aud2htx", AUD2HTX_IPG), CLK_GATE("earc_phy", EARC_PHY), - CLK_GATE("sdma2", SDMA2_ROOT), CLK_GATE("sdma3", SDMA3_ROOT), CLK_GATE("spba2", SPBA2_ROOT), CLK_GATE("dsp", DSP_ROOT), From patchwork Fri Jun 7 13:33:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13689949 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2055.outbound.protection.outlook.com [40.107.20.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F3DC19922B; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: K2JP1lr6+F1D8wIZAP1zT/Ql+ooBRN0kF71jefCt1HfZLcKTreV8pPmBGIA4u9jFmxnQEGQ8w5Xhbo1IKwQwaDfdD043GYmBdxLRdp5It04KvSq3tjY3pXcyVEMXxn+AXZYzoe0RmAX/s3ifI5vAC5qKE5AzccIWhn4GXn40EVqHvEol/XO/xN27zaDO+yJw1/mTxzqMh6+WaKRRLYcoFUAWf7EXKNJNohX7DaNwrF0O9nGPlIVxm1blvyNvUhWU1Xekd6M05v91ebqHfseDFpd1G80eXdXdjIrZg30Kc0OJyiHKQ0hSPwRZUlGzX0hnXIkwWmS/XbnykBvf1kYffAw7bKFMleVarLWobMyx/u0pCWXExYQSB39aXjWf6UbmDIHAisfPmSf6r173tM5Z6WNeIevu9VjPg2Tjp/z2Rl6S/WeovRnjYIWmFquFvV4WOEY1EdCAdI0vJOvhR3EcIugkFrPfAp6+sftpg3M/jC//UzphEPvajGgWEbIHnVg2mXbdmb9VR9CUN4Kil8qId9v5UeGP2+zehTOJnZmQmM2eYkOrpTc9EfU0mBaYswTQr+//9fUqiUuSUBp6dThmG348auM53I20AaZuc0LChTxxPlXW36Q1mFLCAwOqYh6KqzE783RTK4hSKw8FcNDWO/niaITcP8jxnB2zfATX9RRwerNw5leqaDQPCTPTBdfDarTiUV5QLL+jpJHxzdKfz5m9rkivdPrG5PEtBKj4McMWRNurEcEqRitqPqvTrAmEJF3wcuMs8HEWA1yyI0MaRWRX4SvwdqKxBKo4+NSTLo+R0dEg7551hvWPE80lSJQMIV4O83x34c9d01C6idcOHbcQHA4cThxp9Gl5elLzWQ/WtBt2GNQcEECkEE9HqqpDL49oanNFmLXOzkKRKLgEkGmhdduICV22l1TgecjUP8kwNTcBsTNjRokPE8BqlJurS+fVvyD3xjnNHeJZRNsN+o19knF1YQd8Vt7CA2Dbtl9dsnceix3W0+C1d1Ox745Hq3l4x0fAyAAP5Wa7ktslq/zxu608KYu5bg+l1MZOTd8hQgp4sIa+8ux9DRORj6ley9C8COxCZ+CHWvWuIRkuLH17K2AadWPaMup8Ko/cb0Zc9JiznEA6VKhq2GxeJA6dkW/gMSTj62foPEGfmzhE9OgFD3vkun1y5MWf66fCmjwrh8YSt1xfmZlA13MD0WsN+P9HkwDChWoKkY/QEprfHIMk118tPkYVNmEBb4JS9FXEqoi4tYNZDlCxrKpk2ofpZRgpq+VtljgDNqONCsyLp2fkNgkesmkj9vdBO2oroK/iGwlFdfFp0mGzXaFnoea+enaauGwfb6uLKnYlVaWXEPyUUxwcOeLky5y4xxc7SeKP3752u9JLmzi4wfMhGWZ5dhj6z1nH61CPeVEhnefRsl1PzD0D2wQVvx2VVdUZ8YwTDbPmUA6NgPNXujDv+hlbzPA4rc//BNLDAF8zOxcjyNuMWqpUZpzdKncxOijhENK/Av8LGCUyHpCcTE6tJH4cF01hyqBeHHI81rLV9W/Pyz5m+/msfA2oHHrpmhg8p+N524TmEnDsX3Ui5o8oovcu X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 43b80a38-8d64-44ed-6f18-08dc86f54eda X-MS-Exchange-CrossTenant-AuthSource: DB7PR04MB5948.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2024 13:25:33.2014 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: eoPtgOx7iDyeGbXXA5ZzP0uH/CxnjHW+59c8YIbcVD9oitaZSPXibli0P89YGfoIfwJj80iWoJFSeAfxoEdHxQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR04MB9249 From: Zhipeng Wang On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the SiP and then does clk_set_parent on the DDR muxes to synchronize the clock tree. since commit 936c383673b9 ("clk: imx: fix composite peripheral flags"), these TF-A managed muxes have SET_PARENT_GATE set, which results in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY: clk_set_parent(dram_apb_src, sys1_pll_40m);(busfreq-imx8mq.c) commit 926bf91248dd ("clk: imx8m: fix clock tree update of TF-A managed clocks") adds this method and enables 8mm, 8mn and 8mq. i.MX8MP also needs it. This is safe to do, because updating the Linux clock tree to reflect reality will always be glitch-free. Another reason to this patch is that powersave image BT music requires dram to be 400MTS, so clk_set_parent(dram_alt_src, sys1_pll_800m); is required. Without this patch, it will not succeed. Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags") Signed-off-by: Zhipeng Wang Reviewed-by: Ahmad Fatoum Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8mp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 670aa2bab301..e561ff7b135f 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -551,8 +551,8 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1); - hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000); - hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080); + hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000); + hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080); hws[IMX8MP_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1_sels, ccm_base + 0xa100); hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180); hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200); From patchwork Fri Jun 7 13:33:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13689950 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2063.outbound.protection.outlook.com [40.107.20.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 996A019A2A2; Fri, 7 Jun 2024 13:25:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.20.63 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717766743; cv=fail; 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Fri, 7 Jun 2024 13:25:37 +0000 From: "Peng Fan (OSS)" To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com Cc: imx@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan Subject: [PATCH V3 07/15] clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D Date: Fri, 7 Jun 2024 21:33:39 +0800 Message-Id: <20240607133347.3291040-8-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20240607133347.3291040-1-peng.fan@oss.nxp.com> References: <20240607133347.3291040-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI1PR02CA0046.apcprd02.prod.outlook.com (2603:1096:4:1f5::14) To DB7PR04MB5948.eurprd04.prod.outlook.com (2603:10a6:10:8b::21) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB5941:EE_|DU0PR04MB9249:EE_ X-MS-Office365-Filtering-Correlation-Id: 97a60e7f-f154-4cd7-5a5a-08dc86f551aa X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|52116005|7416005|366007|376005|38350700005; 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Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx7d.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 2b77d1fc7bb9..1e1296e74835 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -498,9 +498,9 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) hws[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_hw_mux2_flags("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel), CLK_SET_PARENT_GATE); hws[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_hw_mux2_flags("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel), CLK_SET_PARENT_GATE); hws[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel), CLK_SET_PARENT_GATE); - hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel)); hws[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel), CLK_SET_PARENT_GATE); - hws[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_hw_mux2("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel)); hws[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_hw_mux2_flags("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel), CLK_SET_PARENT_GATE); hws[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel), CLK_SET_PARENT_GATE); hws[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel), CLK_SET_PARENT_GATE); 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Fri, 7 Jun 2024 13:25:42 +0000 From: "Peng Fan (OSS)" To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com Cc: imx@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan Subject: [PATCH V3 08/15] clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D Date: Fri, 7 Jun 2024 21:33:40 +0800 Message-Id: <20240607133347.3291040-9-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20240607133347.3291040-1-peng.fan@oss.nxp.com> References: <20240607133347.3291040-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI1PR02CA0046.apcprd02.prod.outlook.com (2603:1096:4:1f5::14) To DB7PR04MB5948.eurprd04.prod.outlook.com (2603:10a6:10:8b::21) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB5941:EE_|DU0PR04MB9249:EE_ X-MS-Office365-Filtering-Correlation-Id: cdce25a1-6684-4320-b5ab-08dc86f55494 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|52116005|7416005|366007|376005|38350700005; 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Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx7d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 1e1296e74835..99adc55e3f5d 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -505,7 +505,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) hws[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel), CLK_SET_PARENT_GATE); hws[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel), CLK_SET_PARENT_GATE); hws[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel), CLK_SET_PARENT_GATE); - hws[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel), CLK_SET_PARENT_GATE); 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Reviewed-by: Peng Fan Signed-off-by: Adrian Alonso Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8mn.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 4bd1ed11353b..ab77e148e70c 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -583,6 +583,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_hw_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0); hws[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_hw_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0); hws[IMX8MN_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7); + hws[IMX8MN_CLK_SAI7_IPG] = imx_clk_hw_gate2_shared2("sai7_ipg_clk", "ipg_audio_root", base + 0x4650, 0, &share_count_sai7); hws[IMX8MN_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc_24m", 1, 8); From patchwork Fri Jun 7 13:33:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13689958 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2088.outbound.protection.outlook.com [40.107.20.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44B3219B3E3; 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Signed-off-by: Jacky Bai Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8mm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 075f643e3f35..342049b847b9 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -432,7 +432,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) /* BUS */ hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800); hws[IMX8MM_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mm_enet_axi_sels, base + 0x8880); - hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus_critical("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900); + hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900); hws[IMX8MM_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mm_vpu_bus_sels, base + 0x8980); hws[IMX8MM_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mm_disp_axi_sels, base + 0x8a00); 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Fri, 7 Jun 2024 13:25:58 +0000 From: "Peng Fan (OSS)" To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com Cc: imx@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan , Ranjani Vaidyanathan , "Oliver F. Brown" Subject: [PATCH V3 11/15] clk: imx: imx8qxp: Add LVDS bypass clocks Date: Fri, 7 Jun 2024 21:33:43 +0800 Message-Id: <20240607133347.3291040-12-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20240607133347.3291040-1-peng.fan@oss.nxp.com> References: <20240607133347.3291040-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI1PR02CA0046.apcprd02.prod.outlook.com (2603:1096:4:1f5::14) To DB7PR04MB5948.eurprd04.prod.outlook.com (2603:10a6:10:8b::21) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB5941:EE_|DU2PR04MB9020:EE_ X-MS-Office365-Filtering-Correlation-Id: ee3c5643-acee-48db-bb0b-08dc86f55dcf X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|52116005|7416005|376005|366007|38350700005; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /U5lKtWiI/xNRtlmavz72TysPzsHqeoPdzBIZgfbjwIG1pZ59dUwnWjXz+AFLW+x1zXy2OveI4Oy/tw2wpAi4leV2Rw98x3CLvwmb7Diz9L+GNQHZTY157cZbIYe3kErZw6iOTp3hQ1/bG4pGBGDfvkVKlKTDLohj3VE4WlcFvGlHJSGvW0Gsmq4dLw7fvAqId/VSZbwqFKtLR1fpHYUsJxTR4fiZDnIqz5uacJxEX27JUR5CXAgl7Ky+25aX6lF5yLDsSgMueVhtyl7gvcj9et9o3/NlVkg7zYT5OXJ68TU4dMlaoL9sVB+A/dy1qsUyqboBpQT441ToZ2rPtMHbijfWfp/DS3T+YMPnazH7IdGmoN0DIavLgch5mGjqjRWQvPs0QTPKM8TP16/lEhe1Vwbk2/O39MBqzpoCw+wsIVzztd+y+L/CR51QkAHy6uxmh+zTYodfv28hwGx46+vX8JKb+XsLc3T0/Qh8zek9cpZmo5bXJSscbXPcqbArRik5osWaeJyX4NeQMhvm+G7ka7NUnB+pOTtyTalW8c5sqnHfCfwOIX6cNTXCU4Ue3jxqSBtotCFm42igKyE4FRUdLt2milyjpvFBog13l9Sqr1ifB+EPiXYfGIZmivk4GFfli+ibU50OKJfZY/6ZX5lciAbtQGCnFlrISfxEW4ikMJoIRTGJedP9nfmzmyFH3NIbs4Zdwr73JZoTc4kQBTNGgVZXyuixbyMOceDkD6bh2qyPEicOvpmNVt2aNdd7O3c6NE+2uKLY7+IpaVfs1OQkOrUsNw3Twm1CCye/JD0uKIHvfHdXnKL2Kg9Xyghlss95QJ4D6lPbq7I745MNcdVHyh96DeyYgUzDkklm6N5WUIWXTbUlNiuE58kRRlV5eBphvW5I/vqZQTpCtCZp7gIq/ynGpeslriwu9zoLrIC1ZeV3aBPt34Fp5aeaqVfz9m5LEZy7Xm3ZI9KY4Lu+E9aYnWLg1phRUnBDvi64E3krv5MvaoTcOiKhNwLmmBVwjOzPv8riKYhLsdZsTbZXZKA6+xkxtKz4ErkSJXzOf86s+Q0A1aGWtbIETpy8pKzxXGOWEOa4IuXrcsK3Ilwky0mQ/Exd2zCqWumGma10Hpkh1aYD/pPLVRr2QPvSyt47BP2X7iEX8/S3ylxwsCKUqvtx6phNLOnnAhNg/xT+bu2pv64UYwGQg05zZF13ffdYjKURsX1tBLOSese0FA5SOcxtyu8ZfKr/If72bPM0C2IJ/MOPpboV6jiYcWPFgf0g0eL1uwdePqUtSbRVLcAcZLsRmoxVo7F0TzosOGHcho2v04MicG/U8R8B7g9HttK1TkrpvbGm681HlA5viLFhTkilI9V62WFoe+SrqYw+aWiSMzYuEasCEzDFSr+qsoOYp0HL2hNnMNEgHEEtVSWo3brJC3DkRsGPbIk2Vaibenvb3INFVZho1JkFeNbPSgJo6XfVjv+FdASV6ADJ5fYmWW+qEhObIbvJnIiD3PRFVp8wuJuDfhRKKrQwL4BxQzHZBMuGED7gSMrtd5VQvpIzChshucuCsvCxgWk+0eQSt1Gw9fPwch1ykz+jV6cYxgCCF8o X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ee3c5643-acee-48db-bb0b-08dc86f55dcf X-MS-Exchange-CrossTenant-AuthSource: DB7PR04MB5948.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2024 13:25:58.3369 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +YHQ5ptR6K/PqHdm5s+oNQ/0aP6m2yu9Hz3bQ76VJM2WstaDGgkaLG8n9qJH4xRZaQ4ggJmp/nv6Wa5DcULHEA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB9020 From: Peng Fan For iMX8QXP and iMX8QM, add bypass clocks and register some of the LVDS clocks with imx_clk_scu2 as the parent needs to explicitly set. In order to make sure MIPI DSI works well after suspend/resume, the LVDS pixel and phy clocks must be initialized before the MIPI tx_esacpe and rx_escape clocks. LVDS phy, LVDS pixel, tx_escape, and rx_esacpe are all on the same MSLICE. They all share the same clock parent. So, setting the parent source or rate affects all of these clocks. In the LVDS use case the MIPI tx_escape and rx_escape are not saved and restored. So, LVDS works for either clock initialization order. For MIPI case, LVDS must be initialized first. Signed-off-by: Ranjani Vaidyanathan Signed-off-by: "Oliver F. Brown" Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8qxp.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 7d8883916cac..a0654edaae83 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -71,7 +71,7 @@ static const char *const lvds0_sels[] = { "clk_dummy", "clk_dummy", "clk_dummy", - "mipi0_lvds_bypass_clk", + "lvds0_bypass_clk", }; static const char *const lvds1_sels[] = { @@ -79,7 +79,7 @@ static const char *const lvds1_sels[] = { "clk_dummy", "clk_dummy", "clk_dummy", - "mipi1_lvds_bypass_clk", + "lvds1_bypass_clk", }; static const char * const mipi_sels[] = { @@ -223,9 +223,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) /* MIPI-LVDS SS */ imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS); imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER); - imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS); - imx_clk_scu2("mipi0_lvds_pixel_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2); - imx_clk_scu2("mipi0_lvds_phy_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3); + imx_clk_scu("lvds0_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu2("lvds0_pixel_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu2("lvds0_phy_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3); imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS); imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS); imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY); @@ -235,10 +235,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS); imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER); - imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS); - imx_clk_scu2("mipi1_lvds_pixel_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2); - imx_clk_scu2("mipi1_lvds_phy_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3); - + imx_clk_scu("lvds1_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu2("lvds1_pixel_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2); + imx_clk_scu2("lvds1_phy_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3); imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS); imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS); imx_clk_scu2("mipi1_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY); From patchwork Fri Jun 7 13:33:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13689954 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2064.outbound.protection.outlook.com [40.107.22.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40E9F19AD4B; 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Brown" , Robert Chiras , Peng Fan Subject: [PATCH V3 12/15] clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks Date: Fri, 7 Jun 2024 21:33:44 +0800 Message-Id: <20240607133347.3291040-13-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20240607133347.3291040-1-peng.fan@oss.nxp.com> References: <20240607133347.3291040-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI1PR02CA0046.apcprd02.prod.outlook.com (2603:1096:4:1f5::14) To DB7PR04MB5948.eurprd04.prod.outlook.com (2603:10a6:10:8b::21) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB5941:EE_|DU2PR04MB9020:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b9cbf46-b31d-4f5e-d365-08dc86f560fa X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|52116005|7416005|376005|366007|38350700005; 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Brown" The MIPI Pixel and PHY Reference can use the bypass clock as a source. The MIPI bypass clock is the Pixel clock from the Display controller via the pixel link. Using the pixel clock for the PHY reference allows the MIPI bit clock match the pixel rate exactly. The MIPI pixel clock is currently set to be source from the bypass clock in the SCFW. This patch allows the pixel clock parent to be set by the kernel in the event that the SCFW default clock parent may change in the future. Signed-off-by: "Oliver F. Brown" Signed-off-by: Robert Chiras Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8qxp.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index a0654edaae83..fe6509be6ce9 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -90,6 +90,22 @@ static const char * const mipi_sels[] = { "clk_dummy", }; +static const char * const mipi0_phy_sels[] = { + "clk_dummy", + "clk_dummy", + "mipi_pll_div2_clk", + "clk_dummy", + "mipi0_bypass_clk", +}; + +static const char * const mipi1_phy_sels[] = { + "clk_dummy", + "clk_dummy", + "mipi_pll_div2_clk", + "clk_dummy", + "mipi1_bypass_clk", +}; + static const char * const lcd_sels[] = { "clk_dummy", "clk_dummy", @@ -222,25 +238,25 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) /* MIPI-LVDS SS */ imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS); - imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER); + imx_clk_scu2("mipi0_pixel_clk", mipi0_phy_sels, ARRAY_SIZE(mipi0_phy_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER); imx_clk_scu("lvds0_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS); imx_clk_scu2("lvds0_pixel_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2); imx_clk_scu2("lvds0_phy_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3); imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS); imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS); - imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY); + imx_clk_scu2("mipi0_dsi_phy_clk", mipi0_phy_sels, ARRAY_SIZE(mipi0_phy_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY); imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2); imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2); imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER); imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS); - imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER); + imx_clk_scu2("mipi1_pixel_clk", mipi1_phy_sels, ARRAY_SIZE(mipi1_phy_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER); imx_clk_scu("lvds1_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS); imx_clk_scu2("lvds1_pixel_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2); imx_clk_scu2("lvds1_phy_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3); imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS); imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS); - imx_clk_scu2("mipi1_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY); + imx_clk_scu2("mipi1_dsi_phy_clk", mipi1_phy_sels, ARRAY_SIZE(mipi1_phy_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY); imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2); 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Fri, 7 Jun 2024 13:26:08 +0000 From: "Peng Fan (OSS)" To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com Cc: imx@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan Subject: [PATCH V3 13/15] clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk Date: Fri, 7 Jun 2024 21:33:45 +0800 Message-Id: <20240607133347.3291040-14-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20240607133347.3291040-1-peng.fan@oss.nxp.com> References: <20240607133347.3291040-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI1PR02CA0046.apcprd02.prod.outlook.com (2603:1096:4:1f5::14) To DB7PR04MB5948.eurprd04.prod.outlook.com (2603:10a6:10:8b::21) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB5941:EE_|DU2PR04MB9020:EE_ X-MS-Office365-Filtering-Correlation-Id: 0d28e056-4d1c-4805-b2eb-08dc86f563d3 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|52116005|7416005|376005|366007|38350700005; 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If there are no other effects, the earlier the initialization, the earlier the resume. During SCU clock resume, the clock rate is restored. As SCFW guidelines, configure the parent clock rate before configuring the child rate. Fixes: 91e916771de0 ("clk: imx: scu: remove legacy scu clock binding support") Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8qxp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index fe6509be6ce9..47f4ceab1179 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -222,11 +222,11 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC); /* Display controller SS */ - imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0); - imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1); imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL); imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL); imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1); imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS); imx_clk_scu2("dc1_disp0_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0); From patchwork Fri Jun 7 13:33:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13689956 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2048.outbound.protection.outlook.com [40.107.22.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60D1019AD9D; Fri, 7 Jun 2024 13:26:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.22.48 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717766778; cv=fail; b=euWvP+x9z5IQ0a+eqEh21hrO7af3Ggi8DttpDf3QySb4c6BAwivvo/WI0tjxXaS5dx+/usxxePCLZJ8LbdyIhB7MYM4M49yvXMQGz8AiCT3nLWr1P7lyOR9Ly/+bxXDc/ngu16uF21cF8OB5qb2YckAta2HeyFYA6nCmTv+qKEU= ARC-Message-Signature: i=2; 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Fri, 7 Jun 2024 13:26:13 +0000 From: "Peng Fan (OSS)" To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com Cc: imx@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan Subject: [PATCH V3 14/15] clk: imx: imx8qxp: Parent should be initialized earlier than the clock Date: Fri, 7 Jun 2024 21:33:46 +0800 Message-Id: <20240607133347.3291040-15-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20240607133347.3291040-1-peng.fan@oss.nxp.com> References: <20240607133347.3291040-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI1PR02CA0046.apcprd02.prod.outlook.com (2603:1096:4:1f5::14) To DB7PR04MB5948.eurprd04.prod.outlook.com (2603:10a6:10:8b::21) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB5941:EE_|DU2PR04MB9020:EE_ X-MS-Office365-Filtering-Correlation-Id: 796d14fe-104d-44e7-3e4f-08dc86f5669b X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|52116005|7416005|376005|366007|38350700005; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Vn/nL8yUr+s8oTpflzI/vYI8MSCdhLe7D5Dc5V9fV6sscRigW73V0/Uh8yNiRPuMzYbN8r1DOXWUsrAbqRd8baldocucbbR7P5SmKFvF/ivkBk7ulMIecjx3thxLrh/hE1YZvd80kkvIXnj+FNcBPJX6Fc3vLsdSbDvgbzLvDXlcNLkUjykFzBaCcU+QMACZivo1AHGPtGGiD6lH7bIE0FsZI7SNCuTeyKepp+hIqcsK4A48vdyIWTQgtmtqFgpOrFbJIS0rzL3hqZPM7YkQ5ACvEkbw/zMJvirRCZzdmVwd9IujPNsk/I3vyuYzGWZC/Ke/InV4q/4imFGcaCbeyeU7MXX+7hW5knPXvsAV0WW15sr079UZma/54QWcrelPWmRnwhNChd8hpx3UTi2QRfQOSqxnqK7G9oSoktBxV7c8xk0xyZ9Eqp+MHAtO4abBew13NqHMLwxK4h6iSDFONHgJMwFmODY1R7gssnGbkvZXvVjl7swEwywasVF5PIb3CslIdhPzr1dI5yS9CjYTjYhxDHBEk5R1MTZ9zErI/eOwtAvQlLb3kxPVeubdLyXLtEdG0Odz7IlI0T8/7KkYoZkRQyrXj6cOlHcJGZDx5g3LjYljVMmo7ZswGevhqzjVjgZuXhOV8C0FrX8nsX6RS7/rQeBjlGzefIk5He21XUVYEkUFhpg+pdXgzGobmHhdh3Tyk7L5Qj1T0+ar7GeieYCfKa825ErUIqHokmIf8bsqd05J4VgxE7AQ1o2Pr5iqecKauej2xs+L+E+fg+HdLeMbfInS8ph1Djbfjqd7f+m9SJ4DcpMv5NlJBF+l37EQz2hzyZumMXhp3j5FAy/rUK1VrEyX27mgOLFNld168jOiE2XSp9ntD21MssCylWulaMMMMQAzUv7M5hN71KHdbvM4IW7cDeR2qE88lkAL8xJEDrpS08GBqdCFVWIAZnMDJshHGysuNmqQcKA+HR9iwsgqRBaCosT/52g93uceExu5wIjMoTnP+KgTZD9jfmaT0K65g66gzUVq54U7BDrtzh7Z0vZtkH5pO47Jj869GYVCnqcsu3LkULvMKKPhVlKlzJfFKrgB917LYg7htvbp08CWBsxUU1qdXpN3U1Snta+q5Z2KBTMA1HDgk94WUGjJPCVIypZBeyAMUNcS5S6EVYfFJQpIMt5YCalouYkTnzWuai2Plx6uiz3fZpGurO9mpK2iiJRfaFXkp4mULsMd+exBBKgnexsC0N3ZX9wzA2y7ye1pXCWaMr9d/06AQz906/mRLZsMu0TfYgZXazJxAmydx+gHYgPc5MDsJKjcO/O/uZh3UWfnFre91XZxGQX92+ifA7BQ6pjnv1B3ZntROMB2N/YtWGXoiRuUTLkKtc9TrAaHGzn1CbcgiKwEhh6+sajpLJZ0bbMFhcPgLNsFKHQp2vhmxB3wdVe6LZh61GpPo2bVSDosY4jnQQSKS7RZmwpvzXVSTofTkxlP1PC+T7+PW2jnEuUWBy4iLoMi3Jq+v+A4E2Y0YoYC+F3ko6ObCHXcB/zsIZojxluRKikWMzAuH+KGIcs2JFngQG5c+JM6QfTmIysOwJOdxiqca1Eb X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 796d14fe-104d-44e7-3e4f-08dc86f5669b X-MS-Exchange-CrossTenant-AuthSource: DB7PR04MB5948.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2024 13:26:13.2920 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +qZzpX0CzHxL9LW4rT5Y2vnlQ8WxqdTb7OGgrokQy4Xsaa0x8CAjlaeYrch3J16+er18pQNmtqkEhpKEQqLiHQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB9020 From: Peng Fan The initialization order of SCU clocks affects the sequence of SCU clock resume. If there are no other effects, the earlier the initialization, the earlier the resume. During SCU clock resume, the clock rate is restored. As SCFW guidelines, configure the parent clock rate before configuring the child rate. Fixes: babfaa9556d7 ("clk: imx: scu: add more scu clocks") Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8qxp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 47f4ceab1179..3ae162625bb1 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -186,8 +186,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER); imx_clk_scu("elcdif_pll", IMX_SC_R_ELCDIF_PLL, IMX_SC_PM_CLK_PLL); imx_clk_scu2("lcd_clk", lcd_sels, ARRAY_SIZE(lcd_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER); - imx_clk_scu2("lcd_pxl_clk", lcd_pxl_sels, ARRAY_SIZE(lcd_pxl_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_MISC0); imx_clk_scu("lcd_pxl_bypass_div_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu2("lcd_pxl_clk", lcd_pxl_sels, ARRAY_SIZE(lcd_pxl_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_MISC0); /* Audio SS */ imx_clk_scu("audio_pll0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_PLL); @@ -229,11 +229,11 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1); imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS); - imx_clk_scu2("dc1_disp0_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0); - imx_clk_scu2("dc1_disp1_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC1); imx_clk_scu("dc1_pll0_clk", IMX_SC_R_DC_1_PLL_0, IMX_SC_PM_CLK_PLL); imx_clk_scu("dc1_pll1_clk", IMX_SC_R_DC_1_PLL_1, IMX_SC_PM_CLK_PLL); imx_clk_scu("dc1_bypass0_clk", IMX_SC_R_DC_1_VIDEO0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu2("dc1_disp0_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0); + imx_clk_scu2("dc1_disp1_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC1); imx_clk_scu("dc1_bypass1_clk", IMX_SC_R_DC_1_VIDEO1, IMX_SC_PM_CLK_BYPASS); /* MIPI-LVDS SS */ From patchwork Fri Jun 7 13:33:47 2024 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: J8+CmM/rwt6aVLWVchwwfPINCzydELCb1nqTFj1NNiMpKXax5nFN86Q2xtcgmEFQvV7q5kmiA11Xwn8rklcw9MrsFJly5gbrP3m6rJAUGfLMHA2t5O3mFwHa9UtzddLG14n8liLGd3zHtzEV3Dc7r+SafWpMeP2J1QV4bD6RGKjptZ8PNw0tNY/T+jJJ3Zc7y5C9VtVTdfBb5e99Ty+IZLBcm2pAQnB3JgE7vus7oB63DLL7A+Rdx5p3TnXK5edMra5t8l9b86PI9Dbwsus0f++1yw1I3Qn+JqaY/9ha1HfNrx4tH6+3MUY60lSYBTfVRYdjMtgtkomxpNcUyxZKReCrKx04Nfg4rDxsuwbl6ZEunspKttxBRZHkq2gN9y+L0KRSTFoBg6UzX4g1rdHACOkWr2wm/d815iWZ/0/AnN5cZdI/10sN8JLVw3KmDpM+TkIo/pq7RijpS1a5LpNE+SK1c2PVle+ifqtxjV2Akh98q4toJIb8aTij696JgU/THI+KdlAqNAJYBEevd0bDZ3Us0nJdFV15ad7+VBoU7anHhq9Pdr3sT3cD/VZT6H14cJ/wM0QwYp593uAh6FTHVMeKMiIU0zlRbJC04m9mZUYPf57AfUraXzPIMVwsrNGggCnjIC4aY8yob1CUY3+pFUVckVoFbsPJx8m69rKfmM+p/hWN8tMmuG+S9uVxe99IB4jrscFU1DIGZLYDc3zhbyioZ2tWNMaproKDUrw/PwxwmmnU/lSdyt8j222Y4g/YFtkWmbs5I0R69ihohMeW5XhpEAkT0Iwf1xn57PuCTpkP2XgkHS434Nauw9i/p61mQciMq2HF3Jipmofjt2xtxypEmBmSEQXDNr2HCoHmZj1QOMjAI7EOiwqE5+JxqZ6S+DkDQ/9UZ0esVkHZH/+j9w9zRyFFdEb4MM76JkkEjMBExkCedYa4tInsGUOE44KUrTjNXqu2Lc+FA7I5wPo7zMlwpgDcYy2Nr8h08eIgYGbZbXu70TjWs8iKpulZiNfZaOaQdlPjuhaw75iryfRwHourBdAfmUX2Sg/nBlDPfB+dB/7vRcfH0hhswFJ0LxMZhn51IlGAyoPHfID8fdyu4uP98q9rLNPREGCCO+1Zqr8VxB3XQm2lMr3bKP9+0T/W+7+M7V/UdvaTQkl3hvIRh9cvxf2Ja0HNnspamonB97VD3C6DPxAGlqE47U5Lnpv59vY5kR8JCDEGxllrAHuuZhac1h7MSuRpQZqZBp6Z17dddJaH21oOt54coyUCulUuGlxERaKs/DDluCm0JHHcpAfqNu35ZEA7iaJtDXFj/AM9dYY0fq70RxR1qMDAYo4mW0lFt5dhwQ5+LBxOiDpWq6yf6LSxy/5PYtADPLVxICPQdPjI2fTcCj5pV//qwbVXCPHOA20PRmngtVnlhfWNlmUgQZdT770TOwk781N9zWBXio88LP9iCc9lIu0vxTFOYvYOElC4FuvpHbdmPdShzh89ahxh/lsp7vWdsEUhEgo5ZqclAZXE0XbwaKYH0Fkudyx1A0RjBoFoQtd24e0v6HGtp7/NVwzcF3bSYagpcy5ZtSwjHIIb1Zh48etrDR/W X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: dc879646-acb0-45ec-2458-08dc86f569b6 X-MS-Exchange-CrossTenant-AuthSource: DB7PR04MB5948.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2024 13:26:18.3036 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: arc0hHvTLiifFgfEYKAKZtmBEJdYwwBZkzf3ODDADXvRplay2rKOif7Hg7Yrp5V74CjdkhAUWpDmBCpTgd3NBg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB9020 From: Peng Fan - Add 1039.5MHz clock for video PLL to fulfill the LVDS display 148.5MHz * 7 requirement - Add 800MHz clock for ARM PLL Signed-off-by: Jacky Bai Signed-off-by: Peng Fan --- drivers/clk/imx/clk-fracn-gppll.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index 1becba2b62d0..591e0364ee5c 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -78,6 +78,7 @@ struct clk_fracn_gppll { * The Fvco should be in range 2.5Ghz to 5Ghz */ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { + PLL_FRACN_GP(1039500000U, 173, 25, 100, 1, 4), PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6), PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8), PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6), @@ -106,6 +107,7 @@ static const struct imx_fracn_gppll_rate_table int_tbl[] = { PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2), PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3), PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4), + PLL_FRACN_GP_INTEGER(800000000U, 200, 1, 6), }; struct imx_fracn_gppll_clk imx_fracn_gppll_integer = {