From patchwork Thu Feb 28 13:52:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gareth Williams X-Patchwork-Id: 10833147 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 189EB1390 for ; Thu, 28 Feb 2019 14:01:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 058272EF6A for ; Thu, 28 Feb 2019 14:01:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 034952EF70; Thu, 28 Feb 2019 14:00:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 707DA2EF6F for ; Thu, 28 Feb 2019 14:00:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732208AbfB1OA7 (ORCPT ); Thu, 28 Feb 2019 09:00:59 -0500 Received: from relmlor2.renesas.com ([210.160.252.172]:30665 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731305AbfB1OA6 (ORCPT ); Thu, 28 Feb 2019 09:00:58 -0500 X-IronPort-AV: E=Sophos;i="5.58,423,1544454000"; d="scan'208";a="8917305" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 28 Feb 2019 23:00:56 +0900 Received: from renesas-VirtualBox.ree.adwin.renesas.com (unknown [10.226.37.56]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 75590446C473; Thu, 28 Feb 2019 23:00:54 +0900 (JST) From: Gareth Williams To: Rob Herring , Mark Rutland , Alexandre Belloni , Wolfram Sang Cc: Phil Edworthy , devicetree@vger.kernel.org, linux-i2c@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Gareth Williams Subject: [PATCH v5 1/2] dt: snps,designware-i2c: Add clock bindings documentation Date: Thu, 28 Feb 2019 13:52:09 +0000 Message-Id: <1551361930-24434-2-git-send-email-gareth.williams.jx@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551361930-24434-1-git-send-email-gareth.williams.jx@renesas.com> References: <1551361930-24434-1-git-send-email-gareth.williams.jx@renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Phil Edworthy The driver requires an undocumented clock property, so detail it. Add documentation for a separate, optional, interface clock. Signed-off-by: Phil Edworthy Signed-off-by: Gareth Williams Acked-by: Wolfram Sang Reviewed-by: Rob Herring Reviewed-by: Jarkko Nikula --- v5: - Changed clocks and clock-names sections to use term "interface clock" instead of "peripheral clock". - Updated commit message to reference "interface clock" instead of "peripheral clock". v4: - Updated commit message to reference "peripheral clock" instead of "bus clock". v3: - Changed clocks and clock-names sections to use term "peripheral clock" (pclk) instead of "bus clock" (busclk). v2: - No changes. v1: - Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/i2c/i2c-designware.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-designware.txt b/Documentation/devicetree/bindings/i2c/i2c-designware.txt index 3e4bcc2..aa2c106 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-designware.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-designware.txt @@ -6,12 +6,21 @@ Required properties : or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback - reg : Offset and length of the register set for the device - interrupts : where IRQ is the interrupt number. + - clocks : phandles for the clocks, see the description of clock-names below. + The phandle for the "ic_clk" clock is required. The phandle for the "pclk" + clock is optional. If a single clock is specified but no clock-name, it is + the "ic_clk" clock. If both clocks are listed, the "ic_clk" must be first. Recommended properties : - clock-frequency : desired I2C bus clock frequency in Hz. Optional properties : + + - clock-names : Contains the names of the clocks: + "ic_clk", for the core clock used to generate the external I2C clock. + "pclk", the interface clock, required for register access. + - reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold time, named ICPU_CFG:TWI_DELAY in the datasheet. From patchwork Thu Feb 28 13:52:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gareth Williams X-Patchwork-Id: 10833153 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7490A15AC for ; Thu, 28 Feb 2019 14:01:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 646372EF1C for ; Thu, 28 Feb 2019 14:01:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5844C2EF32; Thu, 28 Feb 2019 14:01:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E5D072EF51 for ; Thu, 28 Feb 2019 14:01:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731198AbfB1OBV (ORCPT ); Thu, 28 Feb 2019 09:01:21 -0500 Received: from relmlor2.renesas.com ([210.160.252.172]:54989 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730687AbfB1OBV (ORCPT ); Thu, 28 Feb 2019 09:01:21 -0500 X-IronPort-AV: E=Sophos;i="5.58,423,1544454000"; d="scan'208";a="8917342" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 28 Feb 2019 23:01:19 +0900 Received: from renesas-VirtualBox.ree.adwin.renesas.com (unknown [10.226.37.56]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 11F11446E12D; Thu, 28 Feb 2019 23:01:16 +0900 (JST) From: Gareth Williams To: Jarkko Nikula , Andy Shevchenko , Mika Westerberg , linux-i2c@vger.kernel.org Cc: Phil Edworthy , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Gareth Williams Subject: [PATCH v5 2/2] i2c: designware: Add support for an interface clock Date: Thu, 28 Feb 2019 13:52:10 +0000 Message-Id: <1551361930-24434-3-git-send-email-gareth.williams.jx@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551361930-24434-1-git-send-email-gareth.williams.jx@renesas.com> References: <1551361930-24434-1-git-send-email-gareth.williams.jx@renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Phil Edworthy The Synopsys I2C Controller has an interface clock, but most SoCs hide this away. However, on some SoCs you need to explicitly enable the interface clock in order to access the registers. Therefore, add support for an optional interface clock. Signed-off-by: Phil Edworthy Signed-off-by: Gareth Williams Acked-by: Wolfram Sang Acked-by: Jarkko Nikula Tested-by: Jarkko Nikula --- v5: - Updated comments to reference "interface clock" instead of "peripheral clock". - Corrected spelling in commit message, changing "explicity" to "explicitly". v4: - Updated comments to reference "peripheral clock" instead of "bus clock". - Added Wolfram's Acked-by v3: - busclk renamed to pclk. - Added comment with dw_i2c_dev struct definition describing pclk. - Added enable rollback of first clock if second fails to enable. v2: - Use new devm_clk_get_optional() function as it simplifies handling when the optional clock is not present. --- drivers/i2c/busses/i2c-designware-common.c | 18 ++++++++++++++++-- drivers/i2c/busses/i2c-designware-core.h | 2 ++ drivers/i2c/busses/i2c-designware-platdrv.c | 5 +++++ 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c index a473011..2de7452 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -251,13 +251,27 @@ unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev) int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare) { + int ret; + if (IS_ERR(dev->clk)) return PTR_ERR(dev->clk); - if (prepare) - return clk_prepare_enable(dev->clk); + if (prepare) { + /* Optional interface clock */ + ret = clk_prepare_enable(dev->pclk); + if (ret) + return ret; + + ret = clk_prepare_enable(dev->clk); + if (ret) + clk_disable_unprepare(dev->pclk); + + return ret; + } clk_disable_unprepare(dev->clk); + clk_disable_unprepare(dev->pclk); + return 0; } EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk); diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h index b4a0b2b..e88c711 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -177,6 +177,7 @@ * @base: IO registers pointer * @cmd_complete: tx completion indicator * @clk: input reference clock + * @pclk: clock required to access the registers * @slave: represent an I2C slave device * @cmd_err: run time hadware error code * @msgs: points to an array of messages currently being transferred @@ -226,6 +227,7 @@ struct dw_i2c_dev { void __iomem *ext; struct completion cmd_complete; struct clk *clk; + struct clk *pclk; struct reset_control *rst; struct i2c_client *slave; u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev); diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c index 9eaac3b..97129f5 100644 --- a/drivers/i2c/busses/i2c-designware-platdrv.c +++ b/drivers/i2c/busses/i2c-designware-platdrv.c @@ -346,6 +346,11 @@ static int dw_i2c_plat_probe(struct platform_device *pdev) else i2c_dw_configure_master(dev); + /* Optional interface clock */ + dev->pclk = devm_clk_get_optional(&pdev->dev, "pclk"); + if (IS_ERR(dev->pclk)) + return PTR_ERR(dev->pclk); + dev->clk = devm_clk_get(&pdev->dev, NULL); if (!i2c_dw_prepare_clk(dev, true)) { u64 clk_khz;