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Wed, 12 Jun 2024 04:54:33 -0400 (EDT) From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:54:28 +0100 Subject: [PATCH v2 1/7] MIPS: csrc-r4k: Refine rating computation Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240612-mips-clks-v2-1-a57e6f49f3db@flygoat.com> References: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> In-Reply-To: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> To: Thomas Bogendoerfer , Serge Semin , Daniel Lezcano , Thomas Gleixner Cc: "Maciej W. Rozycki" , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1085; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=HlsMz4irpGQHhXBogt5PnjuY/xW84KRG9P+0pPj829g=; b=kA0DAAoWQ3EMfdd3KcMByyZiAGZpYkegzN7T0kZ1f0Umu6LlQMQvmIIND+o50wHSC/vA89Zbj Ih1BAAWCgAdFiEEVBAijrCB0aDX4Gr8Q3EMfdd3KcMFAmZpYkcACgkQQ3EMfdd3KcMEBAEAzrsw dG+lT1qiTlr3PUPDNYjvF/4Qz8Nal696U78Mo7MA/2KExIY0xLGEFEH85f3RTQasM9C34eS/46Y 7pAk9UZIC X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Increase frequency addend dividend to 10000000 (10MHz) to reasonably accommodate multi GHz level mips_hpt_frequency. Cap rating of csrc-r4k into 299 to ensure it doesn't go into "Desired" range, given all the drama we have with CP0 count registers (SMP sync, behaviour on wait etc). Signed-off-by: Jiaxun Yang --- v2: Fix up number of zeros for 10 MHz (Maciej) --- arch/mips/kernel/csrc-r4k.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index edc4afc080fa..f02ae333f4f9 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -111,7 +111,8 @@ int __init init_r4k_clocksource(void) return -ENXIO; /* Calculate a somewhat reasonable rating value */ - clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; + clocksource_mips.rating = 200; + clocksource_mips.rating += clamp(mips_hpt_frequency / 10000000, 0, 99); /* * R2 onwards makes the count accessible to user mode so it can be used From patchwork Wed Jun 12 08:54:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13694654 Received: from fout5-smtp.messagingengine.com (fout5-smtp.messagingengine.com [103.168.172.148]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B81F816DEAE; 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Wed, 12 Jun 2024 04:54:34 -0400 (EDT) From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:54:29 +0100 Subject: [PATCH v2 2/7] MIPS: csrc-r4k: Apply verification clocksource flags Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240612-mips-clks-v2-2-a57e6f49f3db@flygoat.com> References: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> In-Reply-To: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> To: Thomas Bogendoerfer , Serge Semin , Daniel Lezcano , Thomas Gleixner Cc: "Maciej W. Rozycki" , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=920; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=1l2iw9HXUPl+0KsXVVzTlbq6pkrETw2qb2aFtEiqaXk=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrTMJPcDkbs4Jj35dGebfstlaykn8Wv/olI0M87deFIy+ XBN/seZHaUsDGJcDLJiiiwhAkp9GxovLrj+IOsPzBxWJpAhDFycAjCRzIcM/zOerOPZ8/QxQ1Bd W0Hupz3PlZpfb5/LtznY/vJ5kd36D5kZGeYwNk194Fg/91bgZtEdDr7amSkesxdekms79cLhwvJ JvEwA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 CP0 counter suffers from various problems like SMP sync, behaviour on wait. Set CLOCK_SOURCE_MUST_VERIFY and CLOCK_SOURCE_VERIFY_PERCPU, as what x86 did to TSC, to let kernel test it before use. Signed-off-by: Jiaxun Yang --- arch/mips/kernel/csrc-r4k.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index f02ae333f4f9..055747a7417d 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -21,7 +21,9 @@ static struct clocksource clocksource_mips = { .name = "MIPS", .read = c0_hpt_read, .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .flags = CLOCK_SOURCE_IS_CONTINUOUS | + CLOCK_SOURCE_MUST_VERIFY | + CLOCK_SOURCE_VERIFY_PERCPU, }; static u64 __maybe_unused notrace r4k_read_sched_clock(void) From patchwork Wed Jun 12 08:54:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13694655 Received: from fhigh3-smtp.messagingengine.com (fhigh3-smtp.messagingengine.com [103.168.172.154]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21E0416DEC7; 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Wed, 12 Jun 2024 04:54:35 -0400 (EDT) From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:54:30 +0100 Subject: [PATCH v2 3/7] MIPS: csrc-r4k: Select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240612-mips-clks-v2-3-a57e6f49f3db@flygoat.com> References: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> In-Reply-To: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> To: Thomas Bogendoerfer , Serge Semin , Daniel Lezcano , Thomas Gleixner Cc: "Maciej W. Rozycki" , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=723; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=/1HBI8X5gA92dWi6gRt06ZHjuNwe7f7CMITzKjoFsHY=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrTMJPfQo4IxfadkbvfcyxQ1OWl01tm1vmmCi4nUdoVCW aHbWy91lLIwiHExyIopsoQIKPVtaLy44PqDrD8wc1iZQIYwcHEKwESyKhn+p7NGbLB9sfVH1fP5 8bzl31W89Fs8r21qtWa6HsMlYqkyn+F/6N058VPq/pw+fNh5y50H0fMTKrurX8+9vy9o1sygPZf bmAE= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 csrc-r4k suffers from SMP synchronization overhead. Select HAVE_UNSTABLE_SCHED_CLOCK to workaround drift between the CPUs on the system. HAVE_UNSTABLE_SCHED_CLOCK requires cmpxchg64, so enable it for 64 bits only. Signed-off-by: Jiaxun Yang --- v2: Depends on SMP as well --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f1aa1bf11166..656df5d4097d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1083,6 +1083,7 @@ config CSRC_IOASIC config CSRC_R4K select CLOCKSOURCE_WATCHDOG if CPU_FREQ + select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT bool config CSRC_SB1250 From patchwork Wed Jun 12 08:54:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13694656 Received: from fhigh3-smtp.messagingengine.com (fhigh3-smtp.messagingengine.com [103.168.172.154]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A7A816DED6; Wed, 12 Jun 2024 08:54:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.168.172.154 ARC-Seal: i=1; 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Wed, 12 Jun 2024 04:54:37 -0400 (EDT) From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:54:31 +0100 Subject: [PATCH v2 4/7] MIPS: csrc-r4k: Don't register as sched_clock if unfit Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240612-mips-clks-v2-4-a57e6f49f3db@flygoat.com> References: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> In-Reply-To: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> To: Thomas Bogendoerfer , Serge Semin , Daniel Lezcano , Thomas Gleixner Cc: "Maciej W. Rozycki" , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1593; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=ck/0wmFfxcf8nADSXP1DJNBzmOLr1sy9OsInITDxgf4=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrTMJHdBa7sNZxQzuWbv/H6td+PF/EvrzQPtdb5eTlu72 jxxQ96tjlIWBjEuBlkxRZYQAaW+DY0XF1x/kPUHZg4rE8gQBi5OAZiI4kuG/87V4v+/Rf3dX3fY Ii/qhb3dP6mPGSl3Dq5+mvzTIJBrWQIjw6M8/YstsVbf1hwW+rY/odpE2eHxKhnlJavPS4TrLhX WYgYA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 When we have more than one CPU in system, counter synchronisation overhead can lead to a scenario that sched_clock goes backward when being read from different CPUs. This is accommodated by CONFIG_HAVE_UNSTABLE_SCHED_CLOCK, but it's unavailable on 32bit kernel. We don't want to risk sched_clock correctness, so if we have multiple CPU in system and CONFIG_HAVE_UNSTABLE_SCHED_CLOCK is not set, we just don't use counter as sched_clock source. Signed-off-by: Jiaxun Yang --- arch/mips/kernel/csrc-r4k.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index 055747a7417d..bdb1fa8931f4 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -68,6 +68,18 @@ static bool rdhwr_count_usable(void) return false; } +static inline __init bool count_can_be_sched_clock(void) +{ + if (IS_ENABLED(CONFIG_CPU_FREQ)) + return false; + + if (num_possible_cpus() > 1 && + !IS_ENABLED(CONFIG_HAVE_UNSTABLE_SCHED_CLOCK)) + return false; + + return true; +} + #ifdef CONFIG_CPU_FREQ static bool __read_mostly r4k_clock_unstable; @@ -125,9 +137,8 @@ int __init init_r4k_clocksource(void) clocksource_register_hz(&clocksource_mips, mips_hpt_frequency); -#ifndef CONFIG_CPU_FREQ - sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency); -#endif + if (count_can_be_sched_clock()) + sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency); 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Wed, 12 Jun 2024 04:54:38 -0400 (EDT) From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:54:32 +0100 Subject: [PATCH v2 5/7] MIPS: sync-r4k: Rework based on x86 tsc_sync Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240612-mips-clks-v2-5-a57e6f49f3db@flygoat.com> References: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> In-Reply-To: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> To: Thomas Bogendoerfer , Serge Semin , Daniel Lezcano , Thomas Gleixner Cc: "Maciej W. Rozycki" , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=11164; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=xwM8tZQLa2dHgBxiqH/Qjcx2XSrzcAWUBGhUvTuKohc=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrTMJPe8w66HfnIzPv9f5Pgy/5zC4XrrKqufV4wLY7Ju/ hLfvfp+RykLgxgXg6yYIkuIgFLfhsaLC64/yPoDM4eVCWQIAxenAEzE4TvDf9+NLn9t0uNvPc0/ oJpypudO492anfclWhMOV8z911Zh+Ynhf9HrFQ+m7Kw+xm08c0/CvHd3QuZNavRO0f1W9vBaR/W sj4wA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 The original sync-r4k did a good job on reducing jitter by determine the "next time value", but it has a limitation that when synchronization being performed too many times due to high core count or CPU hotplug, the timewrap on CPU0 will become unaccpetable. Rework the mechanism based on latest x86 tsc_sync. (It seems like the original implementation is based on tsc_sync at that time, so it's just a refresh.) To improve overall performance. Tesed on Loongson64, Boston, QEMU. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/r4k-timer.h | 5 - arch/mips/kernel/smp.c | 2 - arch/mips/kernel/sync-r4k.c | 281 +++++++++++++++++++++++++++----------- 3 files changed, 202 insertions(+), 86 deletions(-) diff --git a/arch/mips/include/asm/r4k-timer.h b/arch/mips/include/asm/r4k-timer.h index 6e7361629348..432e61dd5204 100644 --- a/arch/mips/include/asm/r4k-timer.h +++ b/arch/mips/include/asm/r4k-timer.h @@ -12,15 +12,10 @@ #ifdef CONFIG_SYNC_R4K -extern void synchronise_count_master(int cpu); extern void synchronise_count_slave(int cpu); #else -static inline void synchronise_count_master(int cpu) -{ -} - static inline void synchronise_count_slave(int cpu) { } diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 0b53d35a116e..0362fc5df7b0 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -462,8 +462,6 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle) return -EIO; } - synchronise_count_master(cpu); - /* Wait for CPU to finish startup & mark itself online before return */ wait_for_completion(&cpu_running); return 0; diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c index abdd7aaa3311..39156592582e 100644 --- a/arch/mips/kernel/sync-r4k.c +++ b/arch/mips/kernel/sync-r4k.c @@ -2,121 +2,244 @@ /* * Count register synchronisation. * - * All CPUs will have their count registers synchronised to the CPU0 next time - * value. This can cause a small timewarp for CPU0. All other CPU's should - * not have done anything significant (but they may have had interrupts - * enabled briefly - prom_smp_finish() should not be responsible for enabling - * interrupts...) + * Derived from arch/x86/kernel/tsc_sync.c + * Copyright (C) 2006, Red Hat, Inc., Ingo Molnar */ #include #include #include +#include +#include +#include +#include #include -#include -#include #include +#include -static unsigned int initcount = 0; -static atomic_t count_count_start = ATOMIC_INIT(0); -static atomic_t count_count_stop = ATOMIC_INIT(0); - -#define COUNTON 100 -#define NR_LOOPS 3 - -void synchronise_count_master(int cpu) -{ - int i; - unsigned long flags; - - pr_info("Synchronize counters for CPU %u: ", cpu); +#define COUNTON 100 +#define NR_LOOPS 3 +#define LOOP_TIMEOUT 20 - local_irq_save(flags); +/* + * Entry/exit counters that make sure that both CPUs + * run the measurement code at once: + */ +static atomic_t start_count; +static atomic_t stop_count; +static atomic_t test_runs; - /* - * We loop a few times to get a primed instruction cache, - * then the last pass is more or less synchronised and - * the master and slaves each set their cycle counters to a known - * value all at once. This reduces the chance of having random offsets - * between the processors, and guarantees that the maximum - * delay between the cycle counters is never bigger than - * the latency of information-passing (cachelines) between - * two CPUs. - */ +/* + * We use a raw spinlock in this exceptional case, because + * we want to have the fastest, inlined, non-debug version + * of a critical section, to be able to prove counter time-warps: + */ +static arch_spinlock_t sync_lock = __ARCH_SPIN_LOCK_UNLOCKED; - for (i = 0; i < NR_LOOPS; i++) { - /* slaves loop on '!= 2' */ - while (atomic_read(&count_count_start) != 1) - mb(); - atomic_set(&count_count_stop, 0); - smp_wmb(); +static uint32_t last_counter; +static uint32_t max_warp; +static int nr_warps; +static int random_warps; - /* Let the slave writes its count register */ - atomic_inc(&count_count_start); +/* + * Counter warp measurement loop running on both CPUs. + */ +static uint32_t check_counter_warp(void) +{ + uint32_t start, now, prev, end, cur_max_warp = 0; + int i, cur_warps = 0; - /* Count will be initialised to current timer */ - if (i == 1) - initcount = read_c0_count(); + start = read_c0_count(); + end = start + (uint32_t) mips_hpt_frequency / 1000 * LOOP_TIMEOUT; + for (i = 0; ; i++) { /* - * Everyone initialises count in the last loop: + * We take the global lock, measure counter, save the + * previous counter that was measured (possibly on + * another CPU) and update the previous counter timestamp. */ - if (i == NR_LOOPS-1) - write_c0_count(initcount); + arch_spin_lock(&sync_lock); + prev = last_counter; + now = read_c0_count(); + last_counter = now; + arch_spin_unlock(&sync_lock); /* - * Wait for slave to leave the synchronization point: + * Be nice every now and then (and also check whether + * measurement is done [we also insert a 10 million + * loops safety exit, so we dont lock up in case the + * counter is totally broken]): */ - while (atomic_read(&count_count_stop) != 1) - mb(); - atomic_set(&count_count_start, 0); - smp_wmb(); - atomic_inc(&count_count_stop); + if (unlikely(!(i & 7))) { + if (now > end || i > 10000000) + break; + cpu_relax(); + touch_nmi_watchdog(); + } + /* + * Outside the critical section we can now see whether + * we saw a time-warp of the counter going backwards: + */ + if (unlikely(prev > now)) { + arch_spin_lock(&sync_lock); + max_warp = max(max_warp, prev - now); + cur_max_warp = max_warp; + /* + * Check whether this bounces back and forth. Only + * one CPU should observe time going backwards. + */ + if (cur_warps != nr_warps) + random_warps++; + nr_warps++; + cur_warps = nr_warps; + arch_spin_unlock(&sync_lock); + } + } + WARN(!(now-start), + "Warning: zero counter calibration delta: %d [max: %d]\n", + now-start, end-start); + return cur_max_warp; +} + +/* + * The freshly booted CPU initiates this via an async SMP function call. + */ +static void check_counter_sync_source(void *__cpu) +{ + unsigned int cpu = (unsigned long)__cpu; + int cpus = 2; + + atomic_set(&test_runs, NR_LOOPS); +retry: + /* Wait for the target to start. */ + while (atomic_read(&start_count) != cpus - 1) + cpu_relax(); + + /* + * Trigger the target to continue into the measurement too: + */ + atomic_inc(&start_count); + + check_counter_warp(); + + while (atomic_read(&stop_count) != cpus-1) + cpu_relax(); + + /* + * If the test was successful set the number of runs to zero and + * stop. If not, decrement the number of runs an check if we can + * retry. In case of random warps no retry is attempted. + */ + if (!nr_warps) { + atomic_set(&test_runs, 0); + + pr_info("Counter synchronization [CPU#%d -> CPU#%u]: passed\n", + smp_processor_id(), cpu); + } else if (atomic_dec_and_test(&test_runs) || random_warps) { + /* Force it to 0 if random warps brought us here */ + atomic_set(&test_runs, 0); + + pr_info("Counter synchronization [CPU#%d -> CPU#%u]:\n", + smp_processor_id(), cpu); + pr_info("Measured %d cycles counter warp between CPUs", max_warp); + if (random_warps) + pr_warn("Counter warped randomly between CPUs\n"); } - /* Arrange for an interrupt in a short while */ - write_c0_compare(read_c0_count() + COUNTON); - local_irq_restore(flags); + /* + * Reset it - just in case we boot another CPU later: + */ + atomic_set(&start_count, 0); + random_warps = 0; + nr_warps = 0; + max_warp = 0; + last_counter = 0; + + /* + * Let the target continue with the bootup: + */ + atomic_inc(&stop_count); /* - * i386 code reported the skew here, but the - * count registers were almost certainly out of sync - * so no point in alarming people + * Retry, if there is a chance to do so. */ - pr_cont("done.\n"); + if (atomic_read(&test_runs) > 0) + goto retry; } +/* + * Freshly booted CPUs call into this: + */ void synchronise_count_slave(int cpu) { - int i; - unsigned long flags; + uint32_t cur_max_warp, gbl_max_warp, count; + int cpus = 2; - local_irq_save(flags); + if (!cpu_has_counter || !mips_hpt_frequency) + return; + /* Kick the control CPU into the counter synchronization function */ + smp_call_function_single(cpumask_first(cpu_online_mask), + check_counter_sync_source, + (unsigned long *)(unsigned long)cpu, 0); +retry: /* - * Not every cpu is online at the time this gets called, - * so we first wait for the master to say everyone is ready + * Register this CPU's participation and wait for the + * source CPU to start the measurement: */ + atomic_inc(&start_count); + while (atomic_read(&start_count) != cpus) + cpu_relax(); - for (i = 0; i < NR_LOOPS; i++) { - atomic_inc(&count_count_start); - while (atomic_read(&count_count_start) != 2) - mb(); + cur_max_warp = check_counter_warp(); - /* - * Everyone initialises count in the last loop: - */ - if (i == NR_LOOPS-1) - write_c0_count(initcount); + /* + * Store the maximum observed warp value for a potential retry: + */ + gbl_max_warp = max_warp; + + /* + * Ok, we are done: + */ + atomic_inc(&stop_count); + + /* + * Wait for the source CPU to print stuff: + */ + while (atomic_read(&stop_count) != cpus) + cpu_relax(); - atomic_inc(&count_count_stop); - while (atomic_read(&count_count_stop) != 2) - mb(); + /* + * Reset it for the next sync test: + */ + atomic_set(&stop_count, 0); + + /* + * Check the number of remaining test runs. If not zero, the test + * failed and a retry with adjusted counter is possible. If zero the + * test was either successful or failed terminally. + */ + if (!atomic_read(&test_runs)) { + /* Arrange for an interrupt in a short while */ + write_c0_compare(read_c0_count() + COUNTON); + return; } - /* Arrange for an interrupt in a short while */ - write_c0_compare(read_c0_count() + COUNTON); - local_irq_restore(flags); + /* + * If the warp value of this CPU is 0, then the other CPU + * observed time going backwards so this counter was ahead and + * needs to move backwards. + */ + if (!cur_max_warp) + cur_max_warp = -gbl_max_warp; + + count = read_c0_count(); + count += cur_max_warp; + write_c0_count(count); + + pr_debug("Counter compensate: CPU%u observed %d warp\n", cpu, cur_max_warp); + + goto retry; + } -#undef NR_LOOPS From patchwork Wed Jun 12 08:54:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13694658 Received: from fout5-smtp.messagingengine.com (fout5-smtp.messagingengine.com [103.168.172.148]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4381716E89B; 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Wed, 12 Jun 2024 04:54:40 -0400 (EDT) From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:54:33 +0100 Subject: [PATCH v2 6/7] clocksource: mips-gic-timer: Refine rating computation Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240612-mips-clks-v2-6-a57e6f49f3db@flygoat.com> References: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> In-Reply-To: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> To: Thomas Bogendoerfer , Serge Semin , Daniel Lezcano , Thomas Gleixner Cc: "Maciej W. Rozycki" , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1357; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=ubnQb338iKShZTU1iTrw7BeDTT6ctPCLmk5scTR/g2M=; b=kA0DAAoWQ3EMfdd3KcMByyZiAGZpYkej99mdg8cccBjdsvZE17rDTvcux0h6SSDNZtOc24FAb 4h1BAAWCgAdFiEEVBAijrCB0aDX4Gr8Q3EMfdd3KcMFAmZpYkcACgkQQ3EMfdd3KcMtxwD5Aez6 5355Bn0G0hxyZCy0m/EYO7G5FSQCNetKlyO7ZSUBAM2slUf95REmTxEDq3wILWXN3ShI7x1R8Zc /K3XCOI0M X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 It is a good clocksource which usually go as fast as CPU core and have a low access latency, so raise the base of rating from Good to desired when we know that it has a stable frequency. Increase frequency addend dividend to 10000000 (10MHz) to reasonably accommodate multi GHz level clock, also cap rating within current level. Signed-off-by: Jiaxun Yang --- v2: Fix number of zeros for 10 MHz --- drivers/clocksource/mips-gic-timer.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index b3ae38f36720..7a03d94c028a 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -197,7 +197,11 @@ static int __init __gic_clocksource_init(void) gic_clocksource.mask = CLOCKSOURCE_MASK(count_width); /* Calculate a somewhat reasonable rating value. */ - gic_clocksource.rating = 200 + gic_frequency / 10000000; + if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) + gic_clocksource.rating = 300; /* Good when frequecy is stable */ + else + gic_clocksource.rating = 200; + gic_clocksource.rating += clamp(gic_frequency / 10000000, 0, 99); ret = clocksource_register_hz(&gic_clocksource, gic_frequency); if (ret < 0) From patchwork Wed Jun 12 08:54:34 2024 Content-Type: text/plain; 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Wed, 12 Jun 2024 04:54:41 -0400 (EDT) From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:54:34 +0100 Subject: [PATCH v2 7/7] clocksource: mips-gic-timer: Correct sched_clock width Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240612-mips-clks-v2-7-a57e6f49f3db@flygoat.com> References: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> In-Reply-To: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> To: Thomas Bogendoerfer , Serge Semin , Daniel Lezcano , Thomas Gleixner Cc: "Maciej W. Rozycki" , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2015; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=mjI/mjh69onU/yGH22kAjkQ4UV9AJXLhATGHNzoYz3Q=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrTMJPefrdFGosqqyTq+R9SWHJijwn3e7veB48fOnxNs+ +KxR2xyRykLgxgXg6yYIkuIgFLfhsaLC64/yPoDM4eVCWQIAxenAExk8lpGhgtHoj8qX/Yx95V4 r1MxS8ZzOfdJoRUHt0w96Sv/oFHZey7D/woXc0nFyxpcsiqbt5870uj+aw+7yE33z/yXtP4scEk 25QMA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Counter width of GIC is configurable and can be read from a register. Use width value from the register for sched_clock. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jiaxun Yang --- drivers/clocksource/mips-gic-timer.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index 7a03d94c028a..110347707ff9 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -19,6 +19,7 @@ static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device); static int gic_timer_irq; static unsigned int gic_frequency; +static unsigned int gic_count_width; static bool __read_mostly gic_clock_unstable; static void gic_clocksource_unstable(char *reason); @@ -186,15 +187,14 @@ static void gic_clocksource_unstable(char *reason) static int __init __gic_clocksource_init(void) { - unsigned int count_width; int ret; /* Set clocksource mask. */ - count_width = read_gic_config() & GIC_CONFIG_COUNTBITS; - count_width >>= __ffs(GIC_CONFIG_COUNTBITS); - count_width *= 4; - count_width += 32; - gic_clocksource.mask = CLOCKSOURCE_MASK(count_width); + gic_count_width = read_gic_config() & GIC_CONFIG_COUNTBITS; + gic_count_width >>= __ffs(GIC_CONFIG_COUNTBITS); + gic_count_width *= 4; + gic_count_width += 32; + gic_clocksource.mask = CLOCKSOURCE_MASK(gic_count_width); /* Calculate a somewhat reasonable rating value. */ if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) @@ -264,7 +264,7 @@ static int __init gic_clocksource_of_init(struct device_node *node) if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) { sched_clock_register(mips_cm_is64 ? gic_read_count_64 : gic_read_count_2x32, - 64, gic_frequency); + gic_count_width, gic_frequency); } return 0;