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([178.233.24.52]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286fe7670sm38110205e9.6.2024.06.12.13.12.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jun 2024 13:12:19 -0700 (PDT) From: Alper Nebi Yasak To: AngeloGioacchino Del Regno , linux-mediatek@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Stephen Boyd , Rob Herring , devicetree@vger.kernel.org, Michael Turquette , =?utf-8?q?Uwe_Kleine-K=C3=B6ni?= =?utf-8?q?g?= , Conor Dooley , linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Krzysztof Kozlowski , Matthias Brugger , linux-clk@vger.kernel.org, Alper Nebi Yasak Subject: [PATCH RESEND v2 1/2] clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module Date: Wed, 12 Jun 2024 23:11:00 +0300 Message-ID: <20240612201211.91683-1-alpernebiyasak@gmail.com> X-Mailer: git-send-email 2.45.1 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The MT8173 infracfg clock driver does initialization in two steps, via a CLK_OF_DECLARE_DRIVER declaration. However its early init function doesn't get to run when it's built as a module, presumably since it's not loaded by the time it would have been called by of_clk_init(). This causes its second-step probe() to return -ENOMEM when trying to register clocks, as the necessary clock_data struct isn't initialized by the first step. MT2701 and MT6797 clock drivers also use this mechanism, but they try to allocate the necessary clock_data structure if missing in the second step. Mimic that for the MT8173 infracfg clock as well to make it work as a module. Signed-off-by: Alper Nebi Yasak Reviewed-by: AngeloGioacchino Del Regno --- Changes in v2: - Rewrite patch subject for consistency v1: https://lore.kernel.org/lkml/20231108213734.140707-1-alpernebiyasak@gmail.com/ drivers/clk/mediatek/clk-mt8173-infracfg.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) base-commit: 03d44168cbd7fc57d5de56a3730427db758fc7f6 diff --git a/drivers/clk/mediatek/clk-mt8173-infracfg.c b/drivers/clk/mediatek/clk-mt8173-infracfg.c index 2f2f074e231a..ecc8b0063ea5 100644 --- a/drivers/clk/mediatek/clk-mt8173-infracfg.c +++ b/drivers/clk/mediatek/clk-mt8173-infracfg.c @@ -98,7 +98,17 @@ CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg", static int clk_mt8173_infracfg_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; - int r; + int r, i; + + if (!infra_clk_data) { + infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + if (!infra_clk_data) + return -ENOMEM; + } else { + for (i = 0; i < CLK_INFRA_NR_CLK; i++) + if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER)) + infra_clk_data->hws[i] = ERR_PTR(-ENOENT); + } r = mtk_clk_register_gates(&pdev->dev, node, infra_gates, ARRAY_SIZE(infra_gates), infra_clk_data); From patchwork Wed Jun 12 20:11:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alper Nebi Yasak X-Patchwork-Id: 13695532 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25D0B84E00; Wed, 12 Jun 2024 20:12:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718223145; cv=none; b=da5e9h+oXrkqllK3jTZcsUxqSknUFdJ0tkskEXXePZ5v2L0PO0FXp9IN9cgLUU1vr1mgwRTeGjE5P40YlUj8ixzjPo0xVi7bFB4S+HwOwFT50j3jTL9yiYEcpyWv7MNnd4zo7eHnLjsN5h67U+9mod2l3nwpXrB0tGkW+wsTf+I= ARC-Message-Signature: i=1; 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([178.233.24.52]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286fe7670sm38110205e9.6.2024.06.12.13.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jun 2024 13:12:21 -0700 (PDT) From: Alper Nebi Yasak To: AngeloGioacchino Del Regno , linux-mediatek@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Stephen Boyd , Rob Herring , devicetree@vger.kernel.org, Michael Turquette , =?utf-8?q?Uwe_Kleine-K=C3=B6ni?= =?utf-8?q?g?= , Conor Dooley , linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Krzysztof Kozlowski , Matthias Brugger , linux-clk@vger.kernel.org, Alper Nebi Yasak Subject: [PATCH RESEND v2 2/2] arm64: dts: mediatek: mt8173: Fix timer 13 MHz clock description Date: Wed, 12 Jun 2024 23:11:01 +0300 Message-ID: <20240612201211.91683-2-alpernebiyasak@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240612201211.91683-1-alpernebiyasak@gmail.com> References: <20240612201211.91683-1-alpernebiyasak@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 A previous patch fixes an issue with the mt8173-infracfg clock driver when working as a module, but has the side effect of skipping set up of CLK_INFRA_CLK_13M in that case. This clock is used by the timer device. Similar to the MT8183, MT8192, MT8195 and MT8186 cases [1], change the input clock of the timer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Also remove the RTC clock from the timer node while we're here. According to commit 59311b19d7f63 ("clocksource/drivers/timer-mediatek: Add system timer bindings") it is no longer used. [1] https://lore.kernel.org/all/20221201084229.3464449-1-wenst@chromium.org/ Signed-off-by: Alper Nebi Yasak --- Tested on a MT8173 Chromebook. But I'm not sure I understand all of this, so review with a pinch of salt. Changes in v2: - Add this patch arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 3458be7f7f61..809b379b6818 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -244,6 +244,15 @@ psci { cpu_on = <0x84000003>; }; + clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "clk13m"; + }; + clk26m: oscillator0 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -530,8 +539,7 @@ timer: timer@10008000 { "mediatek,mt6577-timer"; reg = <0 0x10008000 0 0x1000>; interrupts = ; - clocks = <&infracfg CLK_INFRA_CLK_13M>, - <&topckgen CLK_TOP_RTC_SEL>; + clocks = <&clk13m>; }; pwrap: pwrap@1000d000 {