From patchwork Wed Jun 12 20:47:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13695556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 71F16C27C77 for ; Wed, 12 Jun 2024 20:47:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 440C410E904; Wed, 12 Jun 2024 20:47:24 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="K79d5KB+"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 939AD10E8FE; Wed, 12 Jun 2024 20:47:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718225240; x=1749761240; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UZUx4h1r6+vfK/fPYm8VAxGEhUEdEwNVT7c2kSLzjO4=; b=K79d5KB+OroG8MIoGXXeq0ZzA/oNYERsO4qMZcnk0mEn2ArXCD8PslHz N3u9BfDj0tOiwVhFo2/HruOB2lMhrLsiqDtQiJYys8GrB3NpHkaRz5/I7 KnUiO8D6ChpvBT6yBZIpq6OocxGxTFYw7tRnixwWXsToW9qLhL/aJOYX/ fQbrauznJFUjzi6jsAXB2TwocHxNzalq7HzveZNkdq4mc31GA4bQeMHjE Si7uGKWt8ir/dE9v7RHPHongAtYas1i5Wctm1Y76xZLeq0Hg854wgxaUi LBoK8JIqF6ST6NDfs6WvrYmIwhlWojWf3zyM2ArhRewpM3i2IxaXrzEHA g==; X-CSE-ConnectionGUID: VU7ImM0DTX2x7++vZwTLoA== X-CSE-MsgGUID: 21RJA3oOSC6HD0Lf/NyGRg== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="14976517" X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="14976517" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 13:47:19 -0700 X-CSE-ConnectionGUID: DkV7Km2zS8qoS9toM9uiGw== X-CSE-MsgGUID: BzbWwi9WTYiUX04+HIWvGA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="39863945" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 12 Jun 2024 13:47:16 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Jun 2024 23:47:15 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 1/9] drm: Rename drm_plane_check_pixel_format() to drm_plane_has_format() Date: Wed, 12 Jun 2024 23:47:04 +0300 Message-ID: <20240612204712.31404-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240612204712.31404-1-ville.syrjala@linux.intel.com> References: <20240612204712.31404-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Rename drm_plane_check_pixel_format() to drm_plane_has_format() and change the return type accordingly. Allows one to write more natural code. Also matches drm_any_plane_has_format() better. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/drm_atomic.c | 7 ++----- drivers/gpu/drm/drm_crtc.c | 6 ++---- drivers/gpu/drm/drm_crtc_internal.h | 4 ++-- drivers/gpu/drm/drm_plane.c | 22 ++++++++++------------ 4 files changed, 16 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 07b4b394e3bf..6e516c39a372 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -608,7 +608,6 @@ static int drm_atomic_plane_check(const struct drm_plane_state *old_plane_state, unsigned int fb_width, fb_height; struct drm_mode_rect *clips; uint32_t num_clips; - int ret; /* either *both* CRTC and FB must be set, or neither */ if (crtc && !fb) { @@ -635,14 +634,12 @@ static int drm_atomic_plane_check(const struct drm_plane_state *old_plane_state, } /* Check whether this plane supports the fb pixel format. */ - ret = drm_plane_check_pixel_format(plane, fb->format->format, - fb->modifier); - if (ret) { + if (!drm_plane_has_format(plane, fb->format->format, fb->modifier)) { drm_dbg_atomic(plane->dev, "[PLANE:%d:%s] invalid pixel format %p4cc, modifier 0x%llx\n", plane->base.id, plane->name, &fb->format->format, fb->modifier); - return ret; + return -EINVAL; } /* Give drivers some help against integer overflows */ diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 483969b84a30..3488ff067c69 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -789,12 +789,10 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, * case. */ if (!plane->format_default) { - ret = drm_plane_check_pixel_format(plane, - fb->format->format, - fb->modifier); - if (ret) { + if (!drm_plane_has_format(plane, fb->format->format, fb->modifier)) { drm_dbg_kms(dev, "Invalid pixel format %p4cc, modifier 0x%llx\n", &fb->format->format, fb->modifier); + ret = -EINVAL; goto out; } } diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h index 20e9d7b206a2..cdd60f2a4052 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -272,8 +272,8 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, /* drm_plane.c */ int drm_plane_register_all(struct drm_device *dev); void drm_plane_unregister_all(struct drm_device *dev); -int drm_plane_check_pixel_format(struct drm_plane *plane, - u32 format, u64 modifier); +bool drm_plane_has_format(struct drm_plane *plane, + u32 format, u64 modifier); struct drm_mode_rect * __drm_plane_get_damage_clips(const struct drm_plane_state *state); diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index 57662a1fd345..268aa2299df5 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -877,8 +877,8 @@ int drm_mode_getplane(struct drm_device *dev, void *data, return 0; } -int drm_plane_check_pixel_format(struct drm_plane *plane, - u32 format, u64 modifier) +bool drm_plane_has_format(struct drm_plane *plane, + u32 format, u64 modifier) { unsigned int i; @@ -887,24 +887,24 @@ int drm_plane_check_pixel_format(struct drm_plane *plane, break; } if (i == plane->format_count) - return -EINVAL; + return false; if (plane->funcs->format_mod_supported) { if (!plane->funcs->format_mod_supported(plane, format, modifier)) - return -EINVAL; + return false; } else { if (!plane->modifier_count) - return 0; + return true; for (i = 0; i < plane->modifier_count; i++) { if (modifier == plane->modifiers[i]) break; } if (i == plane->modifier_count) - return -EINVAL; + return false; } - return 0; + return true; } static int __setplane_check(struct drm_plane *plane, @@ -924,12 +924,10 @@ static int __setplane_check(struct drm_plane *plane, } /* Check whether this plane supports the fb pixel format. */ - ret = drm_plane_check_pixel_format(plane, fb->format->format, - fb->modifier); - if (ret) { + if (!drm_plane_has_format(plane, fb->format->format, fb->modifier)) { DRM_DEBUG_KMS("Invalid pixel format %p4cc, modifier 0x%llx\n", &fb->format->format, fb->modifier); - return ret; + return -EINVAL; } /* Give drivers some help against integer overflows */ @@ -964,7 +962,7 @@ bool drm_any_plane_has_format(struct drm_device *dev, struct drm_plane *plane; drm_for_each_plane(plane, dev) { - if (drm_plane_check_pixel_format(plane, format, modifier) == 0) + if (drm_plane_has_format(plane, format, modifier)) return true; } From patchwork Wed Jun 12 20:47:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13695555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E94BAC27C75 for ; Wed, 12 Jun 2024 20:47:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E731710E8FF; Wed, 12 Jun 2024 20:47:23 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bzzqFfWb"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5398010E8FE; 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12 Jun 2024 13:47:22 -0700 X-CSE-ConnectionGUID: 38+MusxoQQSLg0EJ6+kftw== X-CSE-MsgGUID: NZAoSL+hRe69TjKeNl49HA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="39863948" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 12 Jun 2024 13:47:19 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Jun 2024 23:47:18 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 2/9] drm: Export drm_plane_has_format() Date: Wed, 12 Jun 2024 23:47:05 +0300 Message-ID: <20240612204712.31404-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240612204712.31404-1-ville.syrjala@linux.intel.com> References: <20240612204712.31404-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Export drm_plane_has_format() so that drivers can use it. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Reviewed-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc_internal.h | 2 -- drivers/gpu/drm/drm_plane.c | 1 + include/drm/drm_plane.h | 2 ++ 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h index cdd60f2a4052..1f73b8d6d750 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -272,8 +272,6 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, /* drm_plane.c */ int drm_plane_register_all(struct drm_device *dev); void drm_plane_unregister_all(struct drm_device *dev); -bool drm_plane_has_format(struct drm_plane *plane, - u32 format, u64 modifier); struct drm_mode_rect * __drm_plane_get_damage_clips(const struct drm_plane_state *state); diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index 268aa2299df5..a51d4dd3f7de 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -906,6 +906,7 @@ bool drm_plane_has_format(struct drm_plane *plane, return true; } +EXPORT_SYMBOL(drm_plane_has_format); static int __setplane_check(struct drm_plane *plane, struct drm_crtc *crtc, diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 9507542121fa..dd718c62ac31 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -972,6 +972,8 @@ static inline struct drm_plane *drm_plane_find(struct drm_device *dev, #define drm_for_each_plane(plane, dev) \ list_for_each_entry(plane, &(dev)->mode_config.plane_list, head) +bool drm_plane_has_format(struct drm_plane *plane, + u32 format, u64 modifier); bool drm_any_plane_has_format(struct drm_device *dev, u32 format, u64 modifier); From patchwork Wed Jun 12 20:47:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13695557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83D9CC27C75 for ; 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X-CSE-ConnectionGUID: ItLU6aLnTOG+817PlViJ9g== X-CSE-MsgGUID: NF6sQvrQSviAcG9Q537hhA== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="14976553" X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="14976553" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 13:47:25 -0700 X-CSE-ConnectionGUID: kEjFkq6gT2mqRlwJ4EwUtQ== X-CSE-MsgGUID: F1GH2jSsTlarPv8Ie71Hew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="39863951" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 12 Jun 2024 13:47:22 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Jun 2024 23:47:22 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Imre Deak Subject: [PATCH v2 3/9] drm/i915: Introduce the plane->min_alignment() vfunc Date: Wed, 12 Jun 2024 23:47:06 +0300 Message-ID: <20240612204712.31404-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240612204712.31404-1-ville.syrjala@linux.intel.com> References: <20240612204712.31404-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Different hardware generations have different scanout alignment requirements. Introduce a new vfunc that will allow us to make that distinction without horrible if-ladders. For now we directly plug in the existing intel_surf_alignment() and intel_cursor_alignment() functions. For fbdev we (temporarily) introduce intel_fbdev_min_alignment() that simply queries the alignment from the primary plane of the first crtc. TODO: someone will need to fix xe's alignment handling Reviewed-by: Imre Deak Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 8 ++-- drivers/gpu/drm/i915/display/intel_cursor.c | 2 + .../drm/i915/display/intel_display_types.h | 3 ++ drivers/gpu/drm/i915/display/intel_fb.c | 22 +++++----- drivers/gpu/drm/i915/display/intel_fb.h | 7 +++- drivers/gpu/drm/i915/display/intel_fb_pin.c | 40 ++++++++++++++----- drivers/gpu/drm/i915/display/intel_fb_pin.h | 3 +- drivers/gpu/drm/i915/display/intel_fbdev.c | 21 +++++++++- drivers/gpu/drm/i915/display/intel_sprite.c | 2 + .../drm/i915/display/skl_universal_plane.c | 11 +++-- drivers/gpu/drm/xe/display/xe_fb_pin.c | 3 +- drivers/gpu/drm/xe/display/xe_plane_initial.c | 4 +- 12 files changed, 89 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 864d94406894..53b18efaa88c 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -225,8 +225,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, int i9xx_check_plane_surface(struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; int src_x, src_y, src_w; u32 offset; @@ -267,7 +267,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) * despite them not using the linear offset anymore. */ if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { - unsigned int alignment = intel_surf_alignment(fb, 0); + unsigned int alignment = plane->min_alignment(plane, fb, 0); int cpp = fb->format->cpp[0]; while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) { @@ -869,6 +869,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) plane->max_stride = ilk_primary_max_stride; } + plane->min_alignment = intel_surf_alignment; + if (IS_I830(dev_priv) || IS_I845G(dev_priv)) { plane->update_arm = i830_plane_update_arm; } else { diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 7f7fc710350c..5f8c23296b61 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -954,6 +954,8 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, cursor->check_plane = i9xx_check_cursor; } + cursor->min_alignment = intel_cursor_alignment; + cursor->cursor.base = ~0; cursor->cursor.cntl = ~0; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4fa785fd664e..0c165572fbd0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1560,6 +1560,9 @@ struct intel_plane { int (*max_height)(const struct drm_framebuffer *fb, int color_plane, unsigned int rotation); + unsigned int (*min_alignment)(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane); unsigned int (*max_stride)(struct intel_plane *plane, u32 pixel_format, u64 modifier, unsigned int rotation); diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 8069abf91c5e..b3a48754a417 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -776,8 +776,12 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier); } -unsigned int intel_cursor_alignment(const struct drm_i915_private *i915) +unsigned int intel_cursor_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) { + struct drm_i915_private *i915 = to_i915(plane->base.dev); + if (IS_I830(i915)) return 16 * 1024; else if (IS_I85X(i915)) @@ -801,10 +805,11 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr return 0; } -unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, +unsigned int intel_surf_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *dev_priv = to_i915(fb->dev); + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); if (intel_fb_uses_dpt(fb)) { /* AUX_DIST needs only 4K alignment */ @@ -1099,17 +1104,12 @@ u32 intel_plane_compute_aligned_offset(int *x, int *y, const struct intel_plane_state *state, int color_plane) { - struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane); - struct drm_i915_private *i915 = to_i915(intel_plane->base.dev); + struct intel_plane *plane = to_intel_plane(state->uapi.plane); + struct drm_i915_private *i915 = to_i915(plane->base.dev); const struct drm_framebuffer *fb = state->hw.fb; unsigned int rotation = state->hw.rotation; unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; - unsigned int alignment; - - if (intel_plane->id == PLANE_CURSOR) - alignment = intel_cursor_alignment(i915); - else - alignment = intel_surf_alignment(fb, color_plane); + unsigned int alignment = plane->min_alignment(plane, fb, color_plane); return intel_compute_aligned_offset(i915, x, y, fb, color_plane, pitch, rotation, alignment); diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 23db6628f53e..86c01a3ce81e 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -60,8 +60,11 @@ unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane); unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, int color_plane, unsigned int height); -unsigned int intel_cursor_alignment(const struct drm_i915_private *i915); -unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, +unsigned int intel_cursor_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane); +unsigned int intel_surf_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, int color_plane); void intel_fb_plane_get_subsampling(int *hsub, int *vsub, diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index 1acc11fa19f4..9b0f1ea41b70 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -103,8 +103,9 @@ intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, struct i915_vma * intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, - bool phys_cursor, const struct i915_gtt_view *view, + unsigned int alignment, + unsigned int phys_alignment, bool uses_fence, unsigned long *out_flags) { @@ -113,7 +114,6 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, struct drm_i915_gem_object *obj = intel_fb_obj(fb); intel_wakeref_t wakeref; struct i915_gem_ww_ctx ww; - unsigned int alignment; struct i915_vma *vma; unsigned int pinctl; int ret; @@ -121,10 +121,6 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))) return ERR_PTR(-EINVAL); - if (phys_cursor) - alignment = intel_cursor_alignment(dev_priv); - else - alignment = intel_surf_alignment(fb, 0); if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) return ERR_PTR(-EINVAL); @@ -162,8 +158,8 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, i915_gem_ww_ctx_init(&ww, true); retry: ret = i915_gem_object_lock(obj, &ww); - if (!ret && phys_cursor) - ret = i915_gem_object_attach_phys(obj, alignment); + if (!ret && phys_alignment) + ret = i915_gem_object_attach_phys(obj, phys_alignment); else if (!ret && HAS_LMEM(dev_priv)) ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0); if (!ret) @@ -234,6 +230,27 @@ void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags) i915_vma_put(vma); } +static unsigned int +intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state) +{ + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); + const struct drm_framebuffer *fb = plane_state->hw.fb; + + return plane->min_alignment(plane, fb, 0); +} + +static unsigned int +intel_plane_fb_min_phys_alignment(const struct intel_plane_state *plane_state) +{ + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); + const struct drm_framebuffer *fb = plane_state->hw.fb; + + if (!intel_plane_needs_physical(plane)) + return 0; + + return plane->min_alignment(plane, fb, 0); +} + int intel_plane_pin_fb(struct intel_plane_state *plane_state) { struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); @@ -242,8 +259,9 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state) struct i915_vma *vma; if (!intel_fb_uses_dpt(&fb->base)) { - vma = intel_fb_pin_to_ggtt(&fb->base, intel_plane_needs_physical(plane), - &plane_state->view.gtt, + vma = intel_fb_pin_to_ggtt(&fb->base, &plane_state->view.gtt, + intel_plane_fb_min_alignment(plane_state), + intel_plane_fb_min_phys_alignment(plane_state), intel_plane_uses_fence(plane_state), &plane_state->flags); if (IS_ERR(vma)) @@ -261,7 +279,7 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state) plane_state->phys_dma_addr = i915_gem_object_get_dma_address(intel_fb_obj(&fb->base), 0); } else { - unsigned int alignment = intel_surf_alignment(&fb->base, 0); + unsigned int alignment = intel_plane_fb_min_alignment(plane_state); vma = intel_dpt_pin_to_ggtt(fb->dpt_vm, alignment / 512); if (IS_ERR(vma)) diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h b/drivers/gpu/drm/i915/display/intel_fb_pin.h index 3f8245edcd15..ac0319b53af0 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.h +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h @@ -15,8 +15,9 @@ struct i915_gtt_view; struct i915_vma * intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, - bool phys_cursor, const struct i915_gtt_view *view, + unsigned int alignment, + unsigned int phys_alignment, bool uses_fence, unsigned long *out_flags); diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 37ae176bfeb0..6e5f88f20482 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -47,6 +47,7 @@ #include "gem/i915_gem_object.h" #include "i915_drv.h" +#include "intel_crtc.h" #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_pin.h" @@ -172,6 +173,21 @@ static const struct fb_ops intelfb_ops = { __diag_pop(); +static unsigned int intel_fbdev_min_alignment(const struct drm_framebuffer *fb) +{ + struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_plane *plane; + struct intel_crtc *crtc; + + crtc = intel_first_crtc(i915); + if (!crtc) + return 0; + + plane = to_intel_plane(crtc->base.primary); + + return plane->min_alignment(plane, fb, 0); +} + static int intelfb_create(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes) { @@ -228,8 +244,9 @@ static int intelfb_create(struct drm_fb_helper *helper, * This also validates that any existing fb inherited from the * BIOS is suitable for own access. */ - vma = intel_fb_pin_to_ggtt(&fb->base, false, - &view, false, &flags); + vma = intel_fb_pin_to_ggtt(&fb->base, &view, + intel_fbdev_min_alignment(&fb->base), 0, + false, &flags); if (IS_ERR(vma)) { ret = PTR_ERR(vma); goto out_unlock; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index e1c907f601da..6f9ae83b095c 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -1622,6 +1622,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, } } + plane->min_alignment = intel_surf_alignment; + if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 8a66b1002a74..7e4417459c41 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1680,11 +1680,12 @@ skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, int main_x, int main_y, u32 main_offset, int ccs_plane) { + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct drm_framebuffer *fb = plane_state->hw.fb; int aux_x = plane_state->view.color_plane[ccs_plane].x; int aux_y = plane_state->view.color_plane[ccs_plane].y; u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; - unsigned int alignment = intel_surf_alignment(fb, ccs_plane); + unsigned int alignment = plane->min_alignment(plane, fb, ccs_plane); int hsub; int vsub; @@ -1728,7 +1729,7 @@ int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, const struct drm_framebuffer *fb = plane_state->hw.fb; int aux_plane = skl_main_to_aux_plane(fb, 0); u32 aux_offset = plane_state->view.color_plane[aux_plane].offset; - unsigned int alignment = intel_surf_alignment(fb, 0); + unsigned int alignment = plane->min_alignment(plane, fb, 0); int w = drm_rect_width(&plane_state->uapi.src) >> 16; intel_add_fb_offsets(x, y, plane_state, 0); @@ -1784,7 +1785,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) int min_width = intel_plane_min_width(plane, fb, 0, rotation); int max_width = intel_plane_max_width(plane, fb, 0, rotation); int max_height = intel_plane_max_height(plane, fb, 0, rotation); - unsigned int alignment = intel_surf_alignment(fb, 0); + unsigned int alignment = plane->min_alignment(plane, fb, 0); int aux_plane = skl_main_to_aux_plane(fb, 0); u32 offset; int ret; @@ -1873,7 +1874,7 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) if (ccs_plane) { u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; - unsigned int alignment = intel_surf_alignment(fb, uv_plane); + unsigned int alignment = plane->min_alignment(plane, fb, uv_plane); if (offset > aux_offset) offset = intel_plane_adjust_aligned_offset(&x, &y, @@ -2430,6 +2431,8 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane->max_stride = skl_plane_max_stride; + plane->min_alignment = intel_surf_alignment; + if (DISPLAY_VER(dev_priv) >= 11) { plane->update_noarm = icl_plane_update_noarm; plane->update_arm = icl_plane_update_arm; diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index a2f417209124..a807f869d39f 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -334,8 +334,9 @@ static void __xe_unpin_fb_vma(struct i915_vma *vma) struct i915_vma * intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, - bool phys_cursor, const struct i915_gtt_view *view, + unsigned int alignment, + unsigned int phys_alignment, bool uses_fence, unsigned long *out_flags) { diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c index e135b20962d9..5eccd6abb3ef 100644 --- a/drivers/gpu/drm/xe/display/xe_plane_initial.c +++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c @@ -210,8 +210,8 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc, intel_fb_fill_view(to_intel_framebuffer(fb), plane_state->uapi.rotation, &plane_state->view); - vma = intel_fb_pin_to_ggtt(fb, false, &plane_state->view.gtt, - false, &plane_state->flags); + vma = intel_fb_pin_to_ggtt(fb, &plane_state->view.gtt, + 0, 0, false, &plane_state->flags); if (IS_ERR(vma)) goto nofb; From patchwork Wed Jun 12 20:47:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13695558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B78BC27C53 for ; Wed, 12 Jun 2024 20:47:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9045D10E909; Wed, 12 Jun 2024 20:47:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="14976573" X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="14976573" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 13:47:28 -0700 X-CSE-ConnectionGUID: JQwnsXGbT+udSn4ktHZc5Q== X-CSE-MsgGUID: /Gk+yPFsS8q1+OeUwS6r2Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="39863954" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 12 Jun 2024 13:47:25 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Jun 2024 23:47:25 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Imre Deak Subject: [PATCH v2 4/9] drm/i915: Introduce fb->min_alignment Date: Wed, 12 Jun 2024 23:47:07 +0300 Message-ID: <20240612204712.31404-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240612204712.31404-1-ville.syrjala@linux.intel.com> References: <20240612204712.31404-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Different planes could have different alignment requirements even for the same format/modifier. Collect the alignment requirements across all planes capable of scanning out the fb such that the alignment is satisfactory to all those planes. So far this was sort of handle by making sure intel_surf_alignment() declares the superset of all planes' alignment requirements, but maintaining that manually is annoying. So we're going to move towards each plane declaring only its own requirements, and thus we need code to generate the superset. v2: Drop the borked per-plane vma optimization (Imre) Assert that the plane's declared alignment is POT (Imre) Cc: Imre Deak Signed-off-by: Ville Syrjälä Reviewed-by: Imre Deak --- .../drm/i915/display/intel_display_types.h | 2 ++ drivers/gpu/drm/i915/display/intel_fb.c | 29 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_fb_pin.c | 5 ++-- drivers/gpu/drm/i915/display/intel_fbdev.c | 18 +----------- 4 files changed, 34 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 0c165572fbd0..af7cc3d6c82b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -146,6 +146,8 @@ struct intel_framebuffer { }; struct i915_address_space *dpt_vm; + + unsigned int min_alignment; }; enum intel_hotplug_state { diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index b3a48754a417..0abb80972885 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -11,6 +11,7 @@ #include "gem/i915_gem_object.h" #include "i915_drv.h" +#include "intel_atomic_plane.h" #include "intel_display.h" #include "intel_display_types.h" #include "intel_dpt.h" @@ -1617,6 +1618,32 @@ bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb) fb->base.modifier == I915_FORMAT_MOD_Yf_TILED; } +static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb) +{ + struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_plane *plane; + unsigned int min_alignment = 0; + + for_each_intel_plane(&i915->drm, plane) { + unsigned int plane_min_alignment; + + if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier)) + continue; + + plane_min_alignment = plane->min_alignment(plane, fb, 0); + + drm_WARN_ON(&i915->drm, plane_min_alignment && + !is_power_of_2(plane_min_alignment)); + + if (intel_plane_needs_physical(plane)) + continue; + + min_alignment = max(min_alignment, plane_min_alignment); + } + + return min_alignment; +} + int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb) { struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base); @@ -1699,6 +1726,8 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer * return -EINVAL; } + fb->min_alignment = intel_fb_min_alignment(&fb->base); + return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index 9b0f1ea41b70..575b271e012b 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -233,10 +233,9 @@ void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags) static unsigned int intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state) { - struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - const struct drm_framebuffer *fb = plane_state->hw.fb; + const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); - return plane->min_alignment(plane, fb, 0); + return fb->min_alignment; } static unsigned int diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 6e5f88f20482..49a1ac4f5491 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -47,7 +47,6 @@ #include "gem/i915_gem_object.h" #include "i915_drv.h" -#include "intel_crtc.h" #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_pin.h" @@ -173,21 +172,6 @@ static const struct fb_ops intelfb_ops = { __diag_pop(); -static unsigned int intel_fbdev_min_alignment(const struct drm_framebuffer *fb) -{ - struct drm_i915_private *i915 = to_i915(fb->dev); - struct intel_plane *plane; - struct intel_crtc *crtc; - - crtc = intel_first_crtc(i915); - if (!crtc) - return 0; - - plane = to_intel_plane(crtc->base.primary); - - return plane->min_alignment(plane, fb, 0); -} - static int intelfb_create(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes) { @@ -245,7 +229,7 @@ static int intelfb_create(struct drm_fb_helper *helper, * BIOS is suitable for own access. */ vma = intel_fb_pin_to_ggtt(&fb->base, &view, - intel_fbdev_min_alignment(&fb->base), 0, + fb->min_alignment, 0, false, &flags); if (IS_ERR(vma)) { ret = PTR_ERR(vma); From patchwork Wed Jun 12 20:47:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13695559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BBFC2C27C75 for ; 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X-CSE-ConnectionGUID: E3LbhvPjRZaA4IYBhubK2w== X-CSE-MsgGUID: Ge/dhxfKSyGzrAIruzaU0A== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="14976592" X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="14976592" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 13:47:31 -0700 X-CSE-ConnectionGUID: +hbMZBZxQ82CpbmnbdxbhA== X-CSE-MsgGUID: lc2OjtS1STe1+mN/jeZktQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="39863957" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 12 Jun 2024 13:47:28 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Jun 2024 23:47:28 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Imre Deak Subject: [PATCH v2 5/9] drm/i915: Split cursor alignment to per-platform vfuncs Date: Wed, 12 Jun 2024 23:47:08 +0300 Message-ID: <20240612204712.31404-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240612204712.31404-1-ville.syrjala@linux.intel.com> References: <20240612204712.31404-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Split intel_cursor_alignment() into per-platform variants. Reviewed-by: Imre Deak Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_cursor.c | 40 +++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_fb.c | 16 --------- drivers/gpu/drm/i915/display/intel_fb.h | 3 -- 3 files changed, 38 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 5f8c23296b61..8e95ed0beeb9 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -194,6 +194,13 @@ i845_cursor_max_stride(struct intel_plane *plane, return 2048; } +static unsigned int i845_cursor_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + return 32; +} + static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) { u32 cntl = 0; @@ -344,6 +351,28 @@ i9xx_cursor_max_stride(struct intel_plane *plane, return plane->base.dev->mode_config.cursor_width * 4; } +static unsigned int i830_cursor_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + /* "AlmadorM Errata – Requires 32-bpp cursor data to be 16KB aligned." */ + return 16 * 1024; /* physical */ +} + +static unsigned int i85x_cursor_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + return 256; /* physical */ +} + +static unsigned int i9xx_cursor_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + return 4 * 1024; /* physical for i915/i945 */ +} + static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -942,20 +971,27 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { cursor->max_stride = i845_cursor_max_stride; + cursor->min_alignment = i845_cursor_min_alignment; cursor->update_arm = i845_cursor_update_arm; cursor->disable_arm = i845_cursor_disable_arm; cursor->get_hw_state = i845_cursor_get_hw_state; cursor->check_plane = i845_check_cursor; } else { cursor->max_stride = i9xx_cursor_max_stride; + + if (IS_I830(dev_priv)) + cursor->min_alignment = i830_cursor_min_alignment; + else if (IS_I85X(dev_priv)) + cursor->min_alignment = i85x_cursor_min_alignment; + else + cursor->min_alignment = i9xx_cursor_min_alignment; + cursor->update_arm = i9xx_cursor_update_arm; cursor->disable_arm = i9xx_cursor_disable_arm; cursor->get_hw_state = i9xx_cursor_get_hw_state; cursor->check_plane = i9xx_check_cursor; } - cursor->min_alignment = intel_cursor_alignment; - cursor->cursor.base = ~0; cursor->cursor.cntl = ~0; diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 0abb80972885..b5d31ccf013a 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -777,22 +777,6 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier); } -unsigned int intel_cursor_alignment(struct intel_plane *plane, - const struct drm_framebuffer *fb, - int color_plane) -{ - struct drm_i915_private *i915 = to_i915(plane->base.dev); - - if (IS_I830(i915)) - return 16 * 1024; - else if (IS_I85X(i915)) - return 256; - else if (IS_I845G(i915) || IS_I865G(i915)) - return 32; - else - return 4 * 1024; -} - static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) { if (DISPLAY_VER(dev_priv) >= 9) diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 86c01a3ce81e..16ebb573643f 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -60,9 +60,6 @@ unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane); unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, int color_plane, unsigned int height); -unsigned int intel_cursor_alignment(struct intel_plane *plane, - const struct drm_framebuffer *fb, - int color_plane); unsigned int intel_surf_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane); From patchwork Wed Jun 12 20:47:09 2024 Content-Type: text/plain; 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12 Jun 2024 13:47:34 -0700 X-CSE-ConnectionGUID: FXUtVTK7SY68qZzNkTKV9A== X-CSE-MsgGUID: wAaXwUnhRdKayY0qeTfXGA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="39863960" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 12 Jun 2024 13:47:31 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Jun 2024 23:47:31 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Imre Deak Subject: [PATCH v2 6/9] drm/i915: Split pre-skl platforms out from intel_surf_alignment() Date: Wed, 12 Jun 2024 23:47:09 +0300 Message-ID: <20240612204712.31404-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240612204712.31404-1-ville.syrjala@linux.intel.com> References: <20240612204712.31404-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Extract the necessary chunks from intel_surf_alignment() into per-platform variants for all pre-skl primary/sprite planes. Reviewed-by: Imre Deak Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 69 ++++++++++++++++++++- drivers/gpu/drm/i915/display/intel_fb.c | 17 +---- drivers/gpu/drm/i915/display/intel_sprite.c | 28 ++++++++- 3 files changed, 96 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 53b18efaa88c..9447f7229b60 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -764,6 +764,66 @@ i8xx_plane_max_stride(struct intel_plane *plane, return 8 * 1024; } +static unsigned int vlv_primary_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + + switch (fb->modifier) { + case I915_FORMAT_MOD_X_TILED: + if (HAS_ASYNC_FLIPS(i915)) + return 256 * 1024; + return 4 * 1024; + case DRM_FORMAT_MOD_LINEAR: + return 128 * 1024; + default: + MISSING_CASE(fb->modifier); + return 0; + } +} + +static unsigned int g4x_primary_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + + switch (fb->modifier) { + case I915_FORMAT_MOD_X_TILED: + if (HAS_ASYNC_FLIPS(i915)) + return 256 * 1024; + return 4 * 1024; + case DRM_FORMAT_MOD_LINEAR: + return 4 * 1024; + default: + MISSING_CASE(fb->modifier); + return 0; + } +} + +static unsigned int i965_plane_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + switch (fb->modifier) { + case I915_FORMAT_MOD_X_TILED: + return 4 * 1024; + case DRM_FORMAT_MOD_LINEAR: + return 128 * 1024; + default: + MISSING_CASE(fb->modifier); + return 0; + } +} + +static unsigned int i9xx_plane_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + return 0; +} + static const struct drm_plane_funcs i965_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, @@ -869,7 +929,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) plane->max_stride = ilk_primary_max_stride; } - plane->min_alignment = intel_surf_alignment; + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + plane->min_alignment = vlv_primary_min_alignment; + else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) + plane->min_alignment = g4x_primary_min_alignment; + else if (DISPLAY_VER(dev_priv) == 4) + plane->min_alignment = i965_plane_min_alignment; + else + plane->min_alignment = i9xx_plane_min_alignment; if (IS_I830(dev_priv) || IS_I845G(dev_priv)) { plane->update_arm = i830_plane_update_arm; diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index b5d31ccf013a..7f6a3de07cad 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -777,19 +777,6 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier); } -static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) -{ - if (DISPLAY_VER(dev_priv) >= 9) - return 256 * 1024; - else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || - IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - return 128 * 1024; - else if (DISPLAY_VER(dev_priv) >= 4) - return 4 * 1024; - else - return 0; -} - unsigned int intel_surf_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) @@ -825,7 +812,7 @@ unsigned int intel_surf_alignment(struct intel_plane *plane, */ if (DISPLAY_VER(dev_priv) >= 12) { if (fb->modifier == DRM_FORMAT_MOD_LINEAR) - return intel_linear_alignment(dev_priv); + return 256 * 1024; return intel_tile_row_size(fb, color_plane); } @@ -837,7 +824,7 @@ unsigned int intel_surf_alignment(struct intel_plane *plane, switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: - return intel_linear_alignment(dev_priv); + return 256 * 1024; case I915_FORMAT_MOD_X_TILED: if (HAS_ASYNC_FLIPS(dev_priv)) return 256 * 1024; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 6f9ae83b095c..f8cceb3e5d8e 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -253,6 +253,21 @@ int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state, return DIV_ROUND_UP(pixel_rate * num, den); } +static unsigned int vlv_sprite_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + switch (fb->modifier) { + case I915_FORMAT_MOD_X_TILED: + return 4 * 1024; + case DRM_FORMAT_MOD_LINEAR: + return 128 * 1024; + default: + MISSING_CASE(fb->modifier); + return 0; + } +} + static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) { u32 sprctl = 0; @@ -964,6 +979,13 @@ hsw_sprite_max_stride(struct intel_plane *plane, return min(8192 * cpp, 16 * 1024); } +static unsigned int g4x_sprite_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + return 4 * 1024; +} + static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) { u32 dvscntr = 0; @@ -1570,6 +1592,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->get_hw_state = vlv_sprite_get_hw_state; plane->check_plane = vlv_sprite_check; plane->max_stride = i965_plane_max_stride; + plane->min_alignment = vlv_sprite_min_alignment; plane->min_cdclk = vlv_plane_min_cdclk; if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { @@ -1596,6 +1619,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->min_cdclk = ivb_sprite_min_cdclk; } + plane->min_alignment = g4x_sprite_min_alignment; + formats = snb_sprite_formats; num_formats = ARRAY_SIZE(snb_sprite_formats); @@ -1607,6 +1632,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->get_hw_state = g4x_sprite_get_hw_state; plane->check_plane = g4x_sprite_check; plane->max_stride = g4x_sprite_max_stride; + plane->min_alignment = g4x_sprite_min_alignment; plane->min_cdclk = g4x_sprite_min_cdclk; if (IS_SANDYBRIDGE(dev_priv)) { @@ -1622,8 +1648,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, } } - plane->min_alignment = intel_surf_alignment; - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | From patchwork Wed Jun 12 20:47:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13695561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F66DC41513 for ; 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X-CSE-ConnectionGUID: LHBMmYJ0RxGZZvAdmE3YSg== X-CSE-MsgGUID: Bj6qkX7zQE2KuvPEfTsevg== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="14976627" X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="14976627" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 13:47:37 -0700 X-CSE-ConnectionGUID: CeC3RZfjRFe2Bj1iJdWpJQ== X-CSE-MsgGUID: ZFyrwhJnRXi9lPAZ/2TP4A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="39863963" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 12 Jun 2024 13:47:35 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Jun 2024 23:47:34 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Imre Deak Subject: [PATCH v2 7/9] drm/i915: Move intel_surf_alignment() into skl_univerals_plane.c Date: Wed, 12 Jun 2024 23:47:10 +0300 Message-ID: <20240612204712.31404-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240612204712.31404-1-ville.syrjala@linux.intel.com> References: <20240612204712.31404-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Now that all pre-skl platforms have their own .min_alignment() functions the remainder of intel_surf_alignment() can be hoisted into skl_univerals_plane.c (and renamed appropriately). Reviewed-by: Imre Deak Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fb.c | 77 +------------------ drivers/gpu/drm/i915/display/intel_fb.h | 4 +- .../drm/i915/display/skl_universal_plane.c | 77 ++++++++++++++++++- 3 files changed, 78 insertions(+), 80 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 7f6a3de07cad..a11c1cf6f548 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -585,7 +585,7 @@ static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_pl return intel_fb_rc_ccs_cc_plane(fb) == color_plane; } -static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane) +bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane) { return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && color_plane == 1; @@ -777,81 +777,6 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier); } -unsigned int intel_surf_alignment(struct intel_plane *plane, - const struct drm_framebuffer *fb, - int color_plane) -{ - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); - - if (intel_fb_uses_dpt(fb)) { - /* AUX_DIST needs only 4K alignment */ - if (intel_fb_is_ccs_aux_plane(fb, color_plane)) - return 512 * 4096; - - /* - * FIXME ADL sees GGTT/DMAR faults with async - * flips unless we align to 16k at least. - * Figure out what's going on here... - */ - if (IS_ALDERLAKE_P(dev_priv) && - !intel_fb_is_ccs_modifier(fb->modifier) && - HAS_ASYNC_FLIPS(dev_priv)) - return 512 * 16 * 1024; - - return 512 * 4096; - } - - /* AUX_DIST needs only 4K alignment */ - if (intel_fb_is_ccs_aux_plane(fb, color_plane)) - return 4096; - - if (is_semiplanar_uv_plane(fb, color_plane)) { - /* - * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes - * alignment for linear UV planes on all platforms. - */ - if (DISPLAY_VER(dev_priv) >= 12) { - if (fb->modifier == DRM_FORMAT_MOD_LINEAR) - return 256 * 1024; - - return intel_tile_row_size(fb, color_plane); - } - - return 4096; - } - - drm_WARN_ON(&dev_priv->drm, color_plane != 0); - - switch (fb->modifier) { - case DRM_FORMAT_MOD_LINEAR: - return 256 * 1024; - case I915_FORMAT_MOD_X_TILED: - if (HAS_ASYNC_FLIPS(dev_priv)) - return 256 * 1024; - return 0; - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: - case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: - case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: - case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: - return 16 * 1024; - case I915_FORMAT_MOD_Y_TILED_CCS: - case I915_FORMAT_MOD_Yf_TILED_CCS: - case I915_FORMAT_MOD_Y_TILED: - case I915_FORMAT_MOD_4_TILED: - case I915_FORMAT_MOD_Yf_TILED: - return 1 * 1024 * 1024; - case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: - case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: - case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: - return 16 * 1024; - default: - MISSING_CASE(fb->modifier); - return 0; - } -} - void intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane) diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 16ebb573643f..1b1fef2dc39a 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -34,6 +34,7 @@ bool intel_fb_is_ccs_modifier(u64 modifier); bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier); bool intel_fb_is_mc_ccs_modifier(u64 modifier); +bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane); bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane); int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb); @@ -60,9 +61,6 @@ unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane); unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, int color_plane, unsigned int height); -unsigned int intel_surf_alignment(struct intel_plane *plane, - const struct drm_framebuffer *fb, - int color_plane); void intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 7e4417459c41..d4c1db3fb9e3 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -503,6 +503,81 @@ skl_plane_max_stride(struct intel_plane *plane, max_pixels, max_bytes); } +static unsigned int skl_plane_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + + if (intel_fb_uses_dpt(fb)) { + /* AUX_DIST needs only 4K alignment */ + if (intel_fb_is_ccs_aux_plane(fb, color_plane)) + return 512 * 4096; + + /* + * FIXME ADL sees GGTT/DMAR faults with async + * flips unless we align to 16k at least. + * Figure out what's going on here... + */ + if (IS_ALDERLAKE_P(dev_priv) && + !intel_fb_is_ccs_modifier(fb->modifier) && + HAS_ASYNC_FLIPS(dev_priv)) + return 512 * 16 * 1024; + + return 512 * 4096; + } + + /* AUX_DIST needs only 4K alignment */ + if (intel_fb_is_ccs_aux_plane(fb, color_plane)) + return 4096; + + if (is_semiplanar_uv_plane(fb, color_plane)) { + /* + * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes + * alignment for linear UV planes on all platforms. + */ + if (DISPLAY_VER(dev_priv) >= 12) { + if (fb->modifier == DRM_FORMAT_MOD_LINEAR) + return 256 * 1024; + + return intel_tile_row_size(fb, color_plane); + } + + return 4096; + } + + drm_WARN_ON(&dev_priv->drm, color_plane != 0); + + switch (fb->modifier) { + case DRM_FORMAT_MOD_LINEAR: + return 256 * 1024; + case I915_FORMAT_MOD_X_TILED: + if (HAS_ASYNC_FLIPS(dev_priv)) + return 256 * 1024; + return 0; + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: + return 16 * 1024; + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_4_TILED: + case I915_FORMAT_MOD_Yf_TILED: + return 1 * 1024 * 1024; + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: + return 16 * 1024; + default: + MISSING_CASE(fb->modifier); + return 0; + } +} + /* Preoffset values for YUV to RGB Conversion */ #define PREOFF_YUV_TO_RGB_HI 0x1800 #define PREOFF_YUV_TO_RGB_ME 0x0000 @@ -2431,7 +2506,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane->max_stride = skl_plane_max_stride; - plane->min_alignment = intel_surf_alignment; + plane->min_alignment = skl_plane_min_alignment; if (DISPLAY_VER(dev_priv) >= 11) { plane->update_noarm = icl_plane_update_noarm; From patchwork Wed Jun 12 20:47:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13695562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B6B5C27C53 for ; Wed, 12 Jun 2024 20:48:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 398E510E917; Wed, 12 Jun 2024 20:48:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="14976642" X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="14976642" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 13:47:40 -0700 X-CSE-ConnectionGUID: zFStCzkRQCOqpPYJ1YPc6w== X-CSE-MsgGUID: XbbbyieQQ26PKR8vPonyUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="39863966" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 12 Jun 2024 13:47:38 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Jun 2024 23:47:37 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Imre Deak Subject: [PATCH v2 8/9] drm/i915: Update plane alignment requirements for TGL+ Date: Wed, 12 Jun 2024 23:47:11 +0300 Message-ID: <20240612204712.31404-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240612204712.31404-1-ville.syrjala@linux.intel.com> References: <20240612204712.31404-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Currently we still use the SKL+ PLANE_SURF alignment even for TGL+ even though the hardware no longer needs it. Introduce a separate tgl_plane_min_alignment() and update it to more accurately reflect the hardware requirements. v2: Don't screw up DPT+semiplanar 2MiB alignment Reviewed-by: Imre Deak Signed-off-by: Ville Syrjälä --- .../drm/i915/display/skl_universal_plane.c | 109 ++++++++++-------- 1 file changed, 61 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index d4c1db3fb9e3..a1c4778cf656 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -503,75 +503,85 @@ skl_plane_max_stride(struct intel_plane *plane, max_pixels, max_bytes); } -static unsigned int skl_plane_min_alignment(struct intel_plane *plane, - const struct drm_framebuffer *fb, - int color_plane) +static u32 tgl_plane_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); - - if (intel_fb_uses_dpt(fb)) { - /* AUX_DIST needs only 4K alignment */ - if (intel_fb_is_ccs_aux_plane(fb, color_plane)) - return 512 * 4096; - - /* - * FIXME ADL sees GGTT/DMAR faults with async - * flips unless we align to 16k at least. - * Figure out what's going on here... - */ - if (IS_ALDERLAKE_P(dev_priv) && - !intel_fb_is_ccs_modifier(fb->modifier) && - HAS_ASYNC_FLIPS(dev_priv)) - return 512 * 16 * 1024; - - return 512 * 4096; - } + struct drm_i915_private *i915 = to_i915(plane->base.dev); + /* PLANE_SURF GGTT -> DPT alignment */ + int mult = intel_fb_uses_dpt(fb) ? 512 : 1; /* AUX_DIST needs only 4K alignment */ if (intel_fb_is_ccs_aux_plane(fb, color_plane)) - return 4096; + return mult * 4 * 1024; if (is_semiplanar_uv_plane(fb, color_plane)) { + if (intel_fb_uses_dpt(fb)) + return 512 * 4 * 1024; + /* * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes * alignment for linear UV planes on all platforms. */ - if (DISPLAY_VER(dev_priv) >= 12) { - if (fb->modifier == DRM_FORMAT_MOD_LINEAR) - return 256 * 1024; - - return intel_tile_row_size(fb, color_plane); - } - - return 4096; - } - - drm_WARN_ON(&dev_priv->drm, color_plane != 0); - - switch (fb->modifier) { - case DRM_FORMAT_MOD_LINEAR: - return 256 * 1024; - case I915_FORMAT_MOD_X_TILED: - if (HAS_ASYNC_FLIPS(dev_priv)) + if (fb->modifier == DRM_FORMAT_MOD_LINEAR) return 256 * 1024; - return 0; + + return intel_tile_row_size(fb, color_plane); + } + + switch (fb->modifier) { + case DRM_FORMAT_MOD_LINEAR: + case I915_FORMAT_MOD_X_TILED: + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_4_TILED: + /* + * FIXME ADL sees GGTT/DMAR faults with async + * flips unless we align to 16k at least. + * Figure out what's going on here... + */ + if (IS_ALDERLAKE_P(i915) && HAS_ASYNC_FLIPS(i915)) + return mult * 16 * 1024; + return mult * 4 * 1024; case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: - return 16 * 1024; + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: + /* + * Align to at least 4x1 main surface + * tiles (16K) to match 64B of AUX. + */ + return max(mult * 4 * 1024, 16 * 1024); + default: + MISSING_CASE(fb->modifier); + return 0; + } +} + +static u32 skl_plane_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + /* + * AUX_DIST needs only 4K alignment, + * as does ICL UV PLANE_SURF. + */ + if (color_plane != 0) + return 4 * 1024; + + switch (fb->modifier) { + case DRM_FORMAT_MOD_LINEAR: + case I915_FORMAT_MOD_X_TILED: + return 256 * 1024; case I915_FORMAT_MOD_Y_TILED_CCS: case I915_FORMAT_MOD_Yf_TILED_CCS: case I915_FORMAT_MOD_Y_TILED: - case I915_FORMAT_MOD_4_TILED: case I915_FORMAT_MOD_Yf_TILED: return 1 * 1024 * 1024; - case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: - case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: - case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: - return 16 * 1024; default: MISSING_CASE(fb->modifier); return 0; @@ -2506,7 +2516,10 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane->max_stride = skl_plane_max_stride; - plane->min_alignment = skl_plane_min_alignment; + if (DISPLAY_VER(dev_priv) >= 12) + plane->min_alignment = tgl_plane_min_alignment; + else + plane->min_alignment = skl_plane_min_alignment; if (DISPLAY_VER(dev_priv) >= 11) { plane->update_noarm = icl_plane_update_noarm; From patchwork Wed Jun 12 20:47:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13695563 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E055AC27C77 for ; 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X-CSE-ConnectionGUID: HTqiihS1Rd2Ma1+w7wRhvQ== X-CSE-MsgGUID: rQlokhHGQlutfCcFC7o1cg== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="14976660" X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="14976660" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 13:47:44 -0700 X-CSE-ConnectionGUID: 27Y3ydLaS2qX5RVBwgBJyQ== X-CSE-MsgGUID: CoriZQcaQouXiqHJqbIT6A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="39863973" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 12 Jun 2024 13:47:41 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Jun 2024 23:47:40 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Imre Deak Subject: [PATCH v2 9/9] drm/i915: Nuke the TGL+ chroma plane tile row alignment stuff Date: Wed, 12 Jun 2024 23:47:12 +0300 Message-ID: <20240612204712.31404-10-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240612204712.31404-1-ville.syrjala@linux.intel.com> References: <20240612204712.31404-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä I don't think the display hardware really has such chroma plane tile row alignment requirements as outlined in commit d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned") Bspec had the same exact thing to say about earlier hardware as well, but we never cared and things work just fine. The one thing mentioned in that commit that is definitely true however is the fence alignment issue. But we don't deal with that on earlier hardware either. We do have code to deal with that issue for the first color plane, but not the chroma planes. So I think if we did want to check this more extensively we should do it in the same places where we already check the first color plane (namely convert_plane_offset_to_xy() and intel_fb_bo_framebuffer_init()). Reviewed-by: Imre Deak Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fb.c | 12 +----------- drivers/gpu/drm/i915/display/intel_fb.h | 1 - drivers/gpu/drm/i915/display/skl_universal_plane.c | 14 -------------- 3 files changed, 1 insertion(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index a11c1cf6f548..f23547a88b1f 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -585,12 +585,6 @@ static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_pl return intel_fb_rc_ccs_cc_plane(fb) == color_plane; } -bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane) -{ - return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && - color_plane == 1; -} - bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) { return fb->modifier == DRM_FORMAT_MOD_LINEAR || @@ -1020,11 +1014,7 @@ static int intel_fb_offset_to_xy(int *x, int *y, struct drm_i915_private *i915 = to_i915(fb->dev); unsigned int height, alignment, unused; - if (DISPLAY_VER(i915) >= 12 && - !intel_fb_needs_pot_stride_remap(to_intel_framebuffer(fb)) && - is_semiplanar_uv_plane(fb, color_plane)) - alignment = intel_tile_row_size(fb, color_plane); - else if (fb->modifier != DRM_FORMAT_MOD_LINEAR) + if (fb->modifier != DRM_FORMAT_MOD_LINEAR) alignment = intel_tile_size(i915); else alignment = 0; diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 1b1fef2dc39a..6dee0c8b7f22 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -34,7 +34,6 @@ bool intel_fb_is_ccs_modifier(u64 modifier); bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier); bool intel_fb_is_mc_ccs_modifier(u64 modifier); -bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane); bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane); int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index a1c4778cf656..ba5a628b4757 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -515,20 +515,6 @@ static u32 tgl_plane_min_alignment(struct intel_plane *plane, if (intel_fb_is_ccs_aux_plane(fb, color_plane)) return mult * 4 * 1024; - if (is_semiplanar_uv_plane(fb, color_plane)) { - if (intel_fb_uses_dpt(fb)) - return 512 * 4 * 1024; - - /* - * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes - * alignment for linear UV planes on all platforms. - */ - if (fb->modifier == DRM_FORMAT_MOD_LINEAR) - return 256 * 1024; - - return intel_tile_row_size(fb, color_plane); - } - switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: case I915_FORMAT_MOD_X_TILED: