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([5.2.194.157]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57cbb05b465sm308861a12.18.2024.06.13.04.40.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jun 2024 04:40:21 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Alexandru Tachici , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Subject: [PATCH v4 1/5] iio: adc: ad7192: Clean up dev Date: Thu, 13 Jun 2024 14:39:57 +0300 Message-Id: <20240613114001.270233-2-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240613114001.270233-1-alisa.roman@analog.com> References: <20240613114001.270233-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Clean up by using a local variable struct device *dev. Also use dev_err_probe where possible. Signed-off-by: Alisa-Dariana Roman --- drivers/iio/adc/ad7192.c | 65 +++++++++++++++++++--------------------- 1 file changed, 30 insertions(+), 35 deletions(-) diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index 0789121236d6..c7fb51a90e87 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -1196,17 +1196,16 @@ static void ad7192_reg_disable(void *reg) static int ad7192_probe(struct spi_device *spi) { + struct device *dev = &spi->dev; struct ad7192_state *st; struct iio_dev *indio_dev; struct regulator *aincom; int ret; - if (!spi->irq) { - dev_err(&spi->dev, "no IRQ?\n"); - return -ENODEV; - } + if (!spi->irq) + return dev_err_probe(dev, -ENODEV, "Failed to get IRQ\n"); - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); if (!indio_dev) return -ENOMEM; @@ -1219,71 +1218,69 @@ static int ad7192_probe(struct spi_device *spi) * Newer firmware should provide a zero volt fixed supply if wired to * ground. */ - aincom = devm_regulator_get_optional(&spi->dev, "aincom"); + aincom = devm_regulator_get_optional(dev, "aincom"); if (IS_ERR(aincom)) { if (PTR_ERR(aincom) != -ENODEV) - return dev_err_probe(&spi->dev, PTR_ERR(aincom), + return dev_err_probe(dev, PTR_ERR(aincom), "Failed to get AINCOM supply\n"); st->aincom_mv = 0; } else { ret = regulator_enable(aincom); if (ret) - return dev_err_probe(&spi->dev, ret, + return dev_err_probe(dev, ret, "Failed to enable specified AINCOM supply\n"); - ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, aincom); + ret = devm_add_action_or_reset(dev, ad7192_reg_disable, aincom); if (ret) return ret; ret = regulator_get_voltage(aincom); if (ret < 0) - return dev_err_probe(&spi->dev, ret, + return dev_err_probe(dev, ret, "Device tree error, AINCOM voltage undefined\n"); st->aincom_mv = ret / MILLI; } - st->avdd = devm_regulator_get(&spi->dev, "avdd"); + st->avdd = devm_regulator_get(dev, "avdd"); if (IS_ERR(st->avdd)) return PTR_ERR(st->avdd); ret = regulator_enable(st->avdd); - if (ret) { - dev_err(&spi->dev, "Failed to enable specified AVdd supply\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable specified AVdd supply\n"); - ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd); + ret = devm_add_action_or_reset(dev, ad7192_reg_disable, st->avdd); if (ret) return ret; - ret = devm_regulator_get_enable(&spi->dev, "dvdd"); + ret = devm_regulator_get_enable(dev, "dvdd"); if (ret) - return dev_err_probe(&spi->dev, ret, "Failed to enable specified DVdd supply\n"); + return dev_err_probe(dev, ret, "Failed to enable specified DVdd supply\n"); - st->vref = devm_regulator_get_optional(&spi->dev, "vref"); + st->vref = devm_regulator_get_optional(dev, "vref"); if (IS_ERR(st->vref)) { if (PTR_ERR(st->vref) != -ENODEV) return PTR_ERR(st->vref); ret = regulator_get_voltage(st->avdd); if (ret < 0) - return dev_err_probe(&spi->dev, ret, + return dev_err_probe(dev, ret, "Device tree error, AVdd voltage undefined\n"); } else { ret = regulator_enable(st->vref); - if (ret) { - dev_err(&spi->dev, "Failed to enable specified Vref supply\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable specified Vref supply\n"); - ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->vref); + ret = devm_add_action_or_reset(dev, ad7192_reg_disable, st->vref); if (ret) return ret; ret = regulator_get_voltage(st->vref); if (ret < 0) - return dev_err_probe(&spi->dev, ret, + return dev_err_probe(dev, ret, "Device tree error, Vref voltage undefined\n"); } st->int_vref_mv = ret / 1000; @@ -1305,13 +1302,13 @@ static int ad7192_probe(struct spi_device *spi) if (ret) return ret; - ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev); + ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev); if (ret) return ret; st->fclk = AD7192_INT_FREQ_MHZ; - st->mclk = devm_clk_get_optional_enabled(&spi->dev, "mclk"); + st->mclk = devm_clk_get_optional_enabled(dev, "mclk"); if (IS_ERR(st->mclk)) return PTR_ERR(st->mclk); @@ -1320,18 +1317,16 @@ static int ad7192_probe(struct spi_device *spi) if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 || st->clock_sel == AD7192_CLK_EXT_MCLK2) { st->fclk = clk_get_rate(st->mclk); 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([5.2.194.157]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57cbb05b465sm308861a12.18.2024.06.13.04.40.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jun 2024 04:40:26 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Alexandru Tachici , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Subject: [PATCH v4 2/5] dt-bindings: iio: adc: ad7192: Update clock config Date: Thu, 13 Jun 2024 14:39:58 +0300 Message-Id: <20240613114001.270233-3-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240613114001.270233-1-alisa.roman@analog.com> References: <20240613114001.270233-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 There are actually 4 configuration modes of clock source for AD719X devices. Either a crystal can be attached externally between MCLK1 and MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 pin. The other 2 modes make use of the 4.92MHz internal clock. Add clock name xtal alongside mclk. When an external crystal is attached, xtal should be chosen. When an external clock is used, mclk should be chosen. The presence of an external clock source is optional, not required. When absent, internal clock is used. Modify required property accordingly and modify second example to showcase this. Signed-off-by: Alisa-Dariana Roman --- .../devicetree/bindings/iio/adc/adi,ad7192.yaml | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml index a03da9489ed9..3ae2f860d24c 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml @@ -39,11 +39,15 @@ properties: clocks: maxItems: 1 - description: phandle to the master clock (mclk) + description: | + Optionally, either a crystal can be attached externally between MCLK1 and + MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 + pin. If absent, internal 4.92MHz clock is used. clock-names: - items: - - const: mclk + enum: + - xtal + - mclk interrupts: maxItems: 1 @@ -135,8 +139,6 @@ patternProperties: required: - compatible - reg - - clocks - - clock-names - interrupts - dvdd-supply - avdd-supply @@ -202,8 +204,6 @@ examples: spi-max-frequency = <1000000>; spi-cpol; spi-cpha; - clocks = <&ad7192_mclk>; - clock-names = "mclk"; interrupts = <25 0x2>; interrupt-parent = <&gpio>; aincom-supply = <&aincom>; From patchwork Thu Jun 13 11:39:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13696659 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87A521442EF; Thu, 13 Jun 2024 11:40:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718278832; cv=none; b=L7KIi5HyDHC8GZ+n7OKKDEevS2Jnz5TqeVWT0dugrxRalj28RD1Utdal8ZvDA8i4c+giFcA+6I5SlJiANbGmchoNwwN7A+VC7BQ38bkGtDNQkIf0MikPgWmjkaxHjPVmqcgqJgLH39QautDGc5xrdc0ZOhOBFlip0g4KEQZMx6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718278832; c=relaxed/simple; bh=UNJKY1APu8hC8tnXQbVXTO0anEd3Q+DEYeYTK/oq3lg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=C/eToNVbcnnKiINolEQQw+6nSo7QvsBCyFU8rXZ31Bl4o4+q8IIcBU7fne1VdDYbICzLwNgkePSTEVDYBhYtp35w1Z7/ALcDKRvgn+Ef8wY3TAT0VQszS7dlQvkvVillLyYT4JzOIw2w8+Lu7i77CIWhDAb1QnQ1kcLSAg1Oieg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NKpuVYd8; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NKpuVYd8" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-57a1fe63947so963479a12.1; Thu, 13 Jun 2024 04:40:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1718278829; x=1718883629; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HHdK21MQAj7eMH+wey85S101XtvAaeCIG2tAjvFarww=; b=NKpuVYd84SQSwTjbxS4x2IT6gbxgPxE4UEisBOvQcEHJzQUghuhlM/xakUBEqekvyi iWslaYX1/rfZ89kDlAEskaq/qMkbRbA2lFkVfj5ILOXVjaKmklwanbpGhXCAgIIImTyA c3pLeFSCyVt45J8yCUk2MNzCRjzA7BTDNR1xS1bNEO44RYS7/h+R9UcfkXI0PPxBhUOb ksAip2JCduSvDccekv8OskjZG8tr684VcKI9fSMAxjWvrsyeklmETQPh97yslJv/llWN hbv5JvngjMVc2q6tfM2LXV02FcDWSVoyuoroNzKo1+RrzXWSbzIm7f/KLcgx/mu3Tu5+ m6WA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718278829; x=1718883629; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HHdK21MQAj7eMH+wey85S101XtvAaeCIG2tAjvFarww=; b=jBnchF5nqKkYetvZqxsECFqLylkUtWazIn0mMLVM1RvWo46GZIeXkI1K7GXnBO632f O5sHps9j4LoollfoCg8a2nUfMmCmZcVXQNGS1qVLmi/fCgKj9D5onAYjSQDUwpO8q3Tr GcBMPIFe/D7ygXpaUrvsWxI4KJAOaH8eHu3VhFHz0wXO2lndvlIiU33GcYkFcT+d0n+g S2sB2ulYxQzG2r7XyMFIMZG3I/3L49CgnQTdkAdppjRDc+IOypM1Tt2IZdbeaXAh8NPg x/tPNuPTvfTjf7JUz3fzY1xRa5+wGs18SVUcsshwSj2gQeqytpqsajkv9AMK8Iw0sfCS i1PA== X-Forwarded-Encrypted: i=1; AJvYcCUNO5JnLQH9a7BY/Cfe+iLW3IEcNqlJ2mszaQNvyTtkqPSdCLCgzovpM5qKfhMDVFHusBEKlhSQW6Nu5gxDITBl5R51y7DDEeBJ+o5uJoBAjnQvnToEyFd1oPB+72Lg93re1vjgRaWcTEqZKNfmJKAtZXuaajaZBEAs5gs8yGtXqvBROg== X-Gm-Message-State: AOJu0Ywdxpns4ynSLYIw3ve4d1C+6pMqJuU0W7xNx5KmGg7vzGop4EIT i0i44+sf3ackRUhYAY3D6C92o4oyTXVbtE0BtdlzzbdeAB5WOc2a X-Google-Smtp-Source: AGHT+IG/+WcR4oE/o6/dLioL19QyAaoUKov0Fp6szt5bO/Klws3koFzKmvlCQ+7RQXVNH4zlOqvkzw== X-Received: by 2002:a50:9f6a:0:b0:57a:2327:d2d2 with SMTP id 4fb4d7f45d1cf-57caaacbb4emr3120531a12.29.1718278828531; Thu, 13 Jun 2024 04:40:28 -0700 (PDT) Received: from spiri.. ([5.2.194.157]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57cbb05b465sm308861a12.18.2024.06.13.04.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jun 2024 04:40:28 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Alexandru Tachici , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Subject: [PATCH v4 3/5] iio: adc: ad7192: Update clock config Date: Thu, 13 Jun 2024 14:39:59 +0300 Message-Id: <20240613114001.270233-4-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240613114001.270233-1-alisa.roman@analog.com> References: <20240613114001.270233-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 There are actually 4 configuration modes of clock source for AD719X devices. Either a crystal can be attached externally between MCLK1 and MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 pin. The other 2 modes make use of the 4.92MHz internal clock. Removed properties adi,int-clock-output-enable and adi,clock-xtal were undocumented. Use cleaner alternative of configuring external clock by using clock names mclk and xtal. Removed functionality of AD7192_CLK_INT_CO restored in complementary patch. Signed-off-by: Alisa-Dariana Roman --- drivers/iio/adc/ad7192.c | 56 ++++++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index c7fb51a90e87..c30ffe47cd70 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -398,25 +398,37 @@ static inline bool ad7192_valid_external_frequency(u32 freq) freq <= AD7192_EXT_FREQ_MHZ_MAX); } -static int ad7192_clock_select(struct ad7192_state *st) +static const char *const ad7192_clock_names[] = { + "xtal", + "mclk" +}; + +static int ad7192_clock_setup(struct ad7192_state *st) { struct device *dev = &st->sd.spi->dev; - unsigned int clock_sel; - - clock_sel = AD7192_CLK_INT; + int ret; - /* use internal clock */ - if (!st->mclk) { - if (device_property_read_bool(dev, "adi,int-clock-output-enable")) - clock_sel = AD7192_CLK_INT_CO; + ret = device_property_match_property_string(dev, "clock-names", + ad7192_clock_names, + ARRAY_SIZE(ad7192_clock_names)); + if (ret < 0) { + st->clock_sel = AD7192_CLK_INT; + st->fclk = AD7192_INT_FREQ_MHZ; } else { - if (device_property_read_bool(dev, "adi,clock-xtal")) - clock_sel = AD7192_CLK_EXT_MCLK1_2; - else - clock_sel = AD7192_CLK_EXT_MCLK2; + st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret; + + st->mclk = devm_clk_get_enabled(dev, ad7192_clock_names[ret]); + if (IS_ERR(st->mclk)) + return dev_err_probe(dev, PTR_ERR(st->mclk), + "Failed to get mclk\n"); + + st->fclk = clk_get_rate(st->mclk); + if (!ad7192_valid_external_frequency(st->fclk)) + return dev_err_probe(dev, -EINVAL, + "External clock frequency out of bounds\n"); } - return clock_sel; + return 0; } static int ad7192_setup(struct iio_dev *indio_dev, struct device *dev) @@ -1306,21 +1318,9 @@ static int ad7192_probe(struct spi_device *spi) if (ret) return ret; - st->fclk = AD7192_INT_FREQ_MHZ; - - st->mclk = devm_clk_get_optional_enabled(dev, "mclk"); - if (IS_ERR(st->mclk)) - return PTR_ERR(st->mclk); - - st->clock_sel = ad7192_clock_select(st); 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([5.2.194.157]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57cbb05b465sm308861a12.18.2024.06.13.04.40.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jun 2024 04:40:30 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Alexandru Tachici , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Subject: [PATCH v4 4/5] dt-bindings: iio: adc: ad7192: Add clock provider Date: Thu, 13 Jun 2024 14:40:00 +0300 Message-Id: <20240613114001.270233-5-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240613114001.270233-1-alisa.roman@analog.com> References: <20240613114001.270233-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Internal clock of AD719X devices can be made available on MCLK2 pin. Add clock provider to support this functionality. Signed-off-by: Alisa-Dariana Roman --- .../devicetree/bindings/iio/adc/adi,ad7192.yaml | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml index 3ae2f860d24c..1434d89c2880 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml @@ -42,13 +42,20 @@ properties: description: | Optionally, either a crystal can be attached externally between MCLK1 and MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 - pin. If absent, internal 4.92MHz clock is used. + pin. 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([5.2.194.157]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57cbb05b465sm308861a12.18.2024.06.13.04.40.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jun 2024 04:40:32 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Alexandru Tachici , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Subject: [PATCH v4 5/5] iio: adc: ad7192: Add clock provider Date: Thu, 13 Jun 2024 14:40:01 +0300 Message-Id: <20240613114001.270233-6-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240613114001.270233-1-alisa.roman@analog.com> References: <20240613114001.270233-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Internal clock of AD719X devices can be made available on MCLK2 pin. Add clock provider to support this functionality. Signed-off-by: Alisa-Dariana Roman --- drivers/iio/adc/ad7192.c | 90 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index c30ffe47cd70..36e3fe50c455 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -203,6 +204,7 @@ struct ad7192_state { struct regulator *avdd; struct regulator *vref; struct clk *mclk; + struct clk_hw int_clk_hw; u16 int_vref_mv; u32 aincom_mv; u32 fclk; @@ -403,6 +405,90 @@ static const char *const ad7192_clock_names[] = { "mclk" }; +static struct ad7192_state *clk_hw_to_ad7192(struct clk_hw *hw) +{ + return container_of(hw, struct ad7192_state, int_clk_hw); +} + +static unsigned long ad7192_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return AD7192_INT_FREQ_MHZ; +} + +static int ad7192_clk_output_is_enabled(struct clk_hw *hw) +{ + struct ad7192_state *st = clk_hw_to_ad7192(hw); + + return st->clock_sel == AD7192_CLK_INT_CO; +} + +static int ad7192_clk_prepare(struct clk_hw *hw) +{ + struct ad7192_state *st = clk_hw_to_ad7192(hw); + int ret; + + st->mode &= ~AD7192_MODE_CLKSRC_MASK; + st->mode |= AD7192_CLK_INT_CO; + + ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); + if (ret) + return ret; + + st->clock_sel = AD7192_CLK_INT_CO; + + return 0; +} + +static void ad7192_clk_unprepare(struct clk_hw *hw) +{ + struct ad7192_state *st = clk_hw_to_ad7192(hw); + int ret; + + st->mode &= ~AD7192_MODE_CLKSRC_MASK; + st->mode |= AD7192_CLK_INT; + + ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); + if (ret) + return; + + st->clock_sel = AD7192_CLK_INT; +} + +static const struct clk_ops ad7192_int_clk_ops = { + .recalc_rate = ad7192_clk_recalc_rate, + .is_enabled = ad7192_clk_output_is_enabled, + .prepare = ad7192_clk_prepare, + .unprepare = ad7192_clk_unprepare, +}; + +static int ad7192_register_clk_provider(struct ad7192_state *st) +{ + struct device *dev = &st->sd.spi->dev; + struct clk_init_data init = {}; + const char *clk_name; + int ret; + + if (!IS_ENABLED(CONFIG_COMMON_CLK)) + return 0; + + ret = device_property_read_string(dev, "clock-output-names", &clk_name); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get clock-output-names\n"); + + init.name = clk_name; + init.ops = &ad7192_int_clk_ops; + + st->int_clk_hw.init = &init; + ret = devm_clk_hw_register(dev, &st->int_clk_hw); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &st->int_clk_hw); +} + static int ad7192_clock_setup(struct ad7192_state *st) { struct device *dev = &st->sd.spi->dev; @@ -414,6 +500,10 @@ static int ad7192_clock_setup(struct ad7192_state *st) if (ret < 0) { st->clock_sel = AD7192_CLK_INT; st->fclk = AD7192_INT_FREQ_MHZ; + + ret = ad7192_register_clk_provider(st); + if (ret) + return ret; } else { st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret;