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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286eef9eesm87272555e9.9.2024.06.14.00.19.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 00:19:50 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 01/12] clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP Date: Fri, 14 Jun 2024 10:19:21 +0300 Message-Id: <20240614071932.1014067-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> References: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240614_001954_737929_A8891B8F X-CRM114-Status: GOOD ( 10.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB) that generates the RTC clock. Add clock, reset and power domain support for it. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a08g045-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index b068733b145f..2ae97c29c377 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -215,6 +215,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9), DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), + DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), }; static const struct rzg2l_reset r9a08g045_resets[] = { @@ -231,6 +232,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), + DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0), }; static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { @@ -238,6 +240,7 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A08G045_IA55_PCLK, MOD_CLK_BASE + R9A08G045_IA55_CLK, MOD_CLK_BASE + R9A08G045_DMAC_ACLK, + MOD_CLK_BASE + R9A08G045_VBAT_BCLK, }; static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { @@ -275,6 +278,9 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { DEF_PD("scif0", R9A08G045_PD_SCIF0, DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), RZG2L_PD_F_NONE), + DEF_PD("vbat", R9A08G045_PD_VBAT, + DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), + RZG2L_PD_F_ALWAYS_ON), }; const struct rzg2l_cpg_info r9a08g045_cpg_info = { From patchwork Fri Jun 14 07:19:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13697969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83C03C27C6E for ; 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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286eef9eesm87272555e9.9.2024.06.14.00.19.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 00:19:52 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 02/12] dt-bindings: clock: renesas,rzg3s-vbattb-clk: Document the VBATTB clock driver Date: Fri, 14 Jun 2024 10:19:22 +0300 Message-Id: <20240614071932.1014067-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> References: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240614_001954_488261_774B3F07 X-CRM114-Status: GOOD ( 14.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that feeds the RTC and the tamper detector. Add documentation for the VBATTB clock driver. Signed-off-by: Claudiu Beznea --- .../clock/renesas,rzg3s-vbattb-clk.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml new file mode 100644 index 000000000000..ef52a0c0f874 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,rzg3s-vbattb-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas VBATTB clock + +maintainers: + - Claudiu Beznea + +description: + Renesas VBATTB module is an always on powered module (backed by battery) which + generates a clock (VBATTCLK). This clocks feeds the RTC and the tamper detector + modules. + +properties: + compatible: + const: renesas,rzg3s-vbattb-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: VBATTB module clock + - description: VBATTB input xtal + + clock-names: + items: + - const: bclk + - const: vbattb_xtal + + '#clock-cells': + const: 0 + + power-domains: + maxItems: 1 + + renesas,vbattb-load-nanofarads: + description: load capacitance of the on board xtal + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 4000, 7000, 9000, 12500 ] + + renesas,vbattb-osc-bypass: + description: set when external clock is connected to RTXOUT pin + type: boolean + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - '#clock-cells' + - renesas,vbattb-load-nanofarads + +additionalProperties: false + +examples: + - | + #include + #include + + vbattb: vbattb@1005c000 { + compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd"; + reg = <0x1005c000 0x1000>; + ranges = <0 0 0x1005c000 0 0x1000>; + interrupts = ; + interrupt-names = "tampdi"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>; + clock-names = "bclk"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + vbattclk: clock-controller@1c { + compatible = "renesas,rzg3s-vbattb-clk"; + reg = <0 0x1c 0 0x10>; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "vbattb_xtal"; + #clock-cells = <0>; + power-domains = <&cpg>; + status = "disabled"; + }; + }; + +... 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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286eef9eesm87272555e9.9.2024.06.14.00.19.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 00:19:53 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 03/12] dt-bindings: mfd: renesas,rzg3s-vbattb: Document VBATTB Date: Fri, 14 Jun 2024 10:19:23 +0300 Message-Id: <20240614071932.1014067-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> References: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240614_001956_404158_62D42E2E X-CRM114-Status: GOOD ( 13.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small general usage memory of 128B. Add documentation for it. Signed-off-by: Claudiu Beznea --- .../bindings/mfd/renesas,rzg3s-vbattb.yaml | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rzg3s-vbattb.yaml diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg3s-vbattb.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg3s-vbattb.yaml new file mode 100644 index 000000000000..c0259e557dc5 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg3s-vbattb.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/renesas,rzg3s-vbattb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Battery Backup Function (VBATTB) + +description: + Renesas VBATTB is a module which controls the RTC clock (VBATTCLK), tamper + detection logic and a small general usage memory (128B). + +maintainers: + - Claudiu Beznea + +properties: + compatible: + items: + - const: renesas,rzg3s-vbattb + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + ranges: true + + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + +patternProperties: + "^clock-controller@[0-9a-f]+$": + $ref: /schemas/clock/renesas,rzg3s-vbattb-clk.yaml# + description: VBATTCLK clock + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + + vbattb: vbattb@1005c000 { + compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd"; + reg = <0x1005c000 0x1000>; + ranges = <0 0 0x1005c000 0 0x1000>; + interrupts = ; + interrupt-names = "tampdi"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>; + clock-names = "bclk"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + vbattclk: clock-controller@1c { + compatible = "renesas,rzg3s-vbattb-clk"; + reg = <0 0x1c 0 0x10>; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "vbattb_xtal"; + #clock-cells = <0>; + power-domains = <&cpg>; + status = "disabled"; + }; + }; + +... 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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286eef9eesm87272555e9.9.2024.06.14.00.19.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 00:19:55 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 04/12] clk: renesas: clk-vbattb: Add VBATTB clock driver Date: Fri, 14 Jun 2024 10:19:24 +0300 Message-Id: <20240614071932.1014067-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> References: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240614_001958_222726_DFA10C4D X-CRM114-Status: GOOD ( 23.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used by the RTC. The input to the VBATTB could be a 32KHz crystal connected to both the RTXIN and RTXOUT pins or an external clock connected to RTXOUT pin. In case an external clock is connected to the RTXOUT pin the renesas,vbattb-osc-bypass DT property need to be used when describing the node. The load capacitance of the on-board oscillator need to be configured with renesas,vbattb-load-nanofarads DT property. Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/Kconfig | 4 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-vbattb.c | 202 +++++++++++++++++++++++++++++++ 3 files changed, 207 insertions(+) create mode 100644 drivers/clk/renesas/clk-vbattb.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index d252150402e8..1dc38e3a8326 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -228,6 +228,10 @@ config CLK_RZG2L bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER +config CLK_VBATTB + bool "Renesas VBATTB clock controller" + select RESET_CONTROLLER + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index f7e18679c3b8..e9e487f53577 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o obj-$(CONFIG_CLK_RENESAS_DIV6) += clk-div6.o +obj-$(CONFIG_CLK_VBATTB) += clk-vbattb.o diff --git a/drivers/clk/renesas/clk-vbattb.c b/drivers/clk/renesas/clk-vbattb.c new file mode 100644 index 000000000000..0a5cc886e89c --- /dev/null +++ b/drivers/clk/renesas/clk-vbattb.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * VBATTB clock driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define VBATTB_BKSCCR 0x1c +#define VBATTB_BKSCCR_SOSEL BIT(6) +#define VBATTB_SOSCCR2 0x24 +#define VBATTB_SOSCCR2_SOSTP2 BIT(0) +#define VBATTB_XOSCCR 0x30 +#define VBATTB_XOSCCR_OUTEN BIT(16) +#define VBATTB_XOSCCR_XSEL GENMASK(1, 0) +#define VBATTB_XOSCCR_XSEL_4_PF 0x0 +#define VBATTB_XOSCCR_XSEL_7_PF 0x1 +#define VBATTB_XOSCCR_XSEL_9_PF 0x2 +#define VBATTB_XOSCCR_XSEL_12_5_PF 0x3 + +/** + * struct vbattb_clk - VBATTB clock data structure + * @regmap: regmap + * @hw: clk hw + * @lock: device lock + * @load_capacitance: load capacitance + */ +struct vbattb_clk { + struct regmap *regmap; + struct clk_hw hw; + spinlock_t lock; + u8 load_capacitance; +}; + +#define to_vbattb_clk(_hw) container_of(_hw, struct vbattb_clk, hw) + +static int vbattb_clk_enable(struct clk_hw *hw) +{ + struct vbattb_clk *vbclk = to_vbattb_clk(hw); + struct regmap *regmap = vbclk->regmap; + + spin_lock(&vbclk->lock); + regmap_update_bits(regmap, VBATTB_SOSCCR2, VBATTB_SOSCCR2_SOSTP2, 0); + regmap_update_bits(regmap, VBATTB_XOSCCR, VBATTB_XOSCCR_OUTEN | VBATTB_XOSCCR_XSEL, + VBATTB_XOSCCR_OUTEN | vbclk->load_capacitance); + spin_unlock(&vbclk->lock); + + return 0; +} + +static void vbattb_clk_disable(struct clk_hw *hw) +{ + struct vbattb_clk *vbclk = to_vbattb_clk(hw); + struct regmap *regmap = vbclk->regmap; + + spin_lock(&vbclk->lock); + regmap_update_bits(regmap, VBATTB_XOSCCR, VBATTB_XOSCCR_OUTEN, 0); + regmap_update_bits(regmap, VBATTB_SOSCCR2, VBATTB_SOSCCR2_SOSTP2, VBATTB_SOSCCR2_SOSTP2); + spin_unlock(&vbclk->lock); +} + +static int vbattb_clk_is_enabled(struct clk_hw *hw) +{ + struct vbattb_clk *vbclk = to_vbattb_clk(hw); + struct regmap *regmap = vbclk->regmap; + unsigned int xosccr, sosccr2; + int ret; + + spin_lock(&vbclk->lock); + ret = regmap_read(regmap, VBATTB_XOSCCR, &xosccr); + if (ret) + goto unlock; + + ret = regmap_read(regmap, VBATTB_SOSCCR2, &sosccr2); +unlock: + spin_unlock(&vbclk->lock); + + if (ret) + return 0; + + return ((xosccr & VBATTB_XOSCCR_OUTEN) && !(sosccr2 & VBATTB_SOSCCR2_SOSTP2)); +} + +static const struct clk_ops vbattb_clk_ops = { + .enable = vbattb_clk_enable, + .disable = vbattb_clk_disable, + .is_enabled = vbattb_clk_is_enabled, +}; + +static int vbattb_clk_validate_load_capacitance(struct vbattb_clk *vbclk, u32 load_capacitance) +{ + switch (load_capacitance) { + case 4000: + vbclk->load_capacitance = VBATTB_XOSCCR_XSEL_4_PF; + break; + case 7000: + vbclk->load_capacitance = VBATTB_XOSCCR_XSEL_7_PF; + break; + case 9000: + vbclk->load_capacitance = VBATTB_XOSCCR_XSEL_9_PF; + break; + case 12500: + vbclk->load_capacitance = VBATTB_XOSCCR_XSEL_12_5_PF; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int vbattb_clk_probe(struct platform_device *pdev) +{ + struct clk_parent_data parent_data = { .fw_name = "vbattb_xtal" }; + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct clk_init_data init = {}; + struct vbattb_clk *vbclk; + u32 load_capacitance; + struct clk_hw *hw; + bool bypass; + int ret; + + vbclk = devm_kzalloc(dev, GFP_KERNEL, sizeof(*vbclk)); + if (!vbclk) + return -ENOMEM; + + vbclk->regmap = syscon_node_to_regmap(np->parent); + if (IS_ERR(vbclk->regmap)) + return PTR_ERR(vbclk->regmap); + + bypass = of_property_read_bool(np, "renesas,vbattb-osc-bypass"); + ret = of_property_read_u32(np, "renesas,vbattb-load-nanofarads", &load_capacitance); + if (ret) + return ret; + + ret = vbattb_clk_validate_load_capacitance(vbclk, load_capacitance); + if (ret) + return ret; + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + regmap_update_bits(vbclk->regmap, VBATTB_BKSCCR, VBATTB_BKSCCR_SOSEL, + bypass ? VBATTB_BKSCCR_SOSEL : 0); + + init.name = "vbattclk"; + init.ops = &vbattb_clk_ops; + init.parent_data = &parent_data; + init.num_parents = 1; + init.flags = 0; + + vbclk->hw.init = &init; + hw = &vbclk->hw; + + spin_lock_init(&vbclk->lock); + + ret = devm_clk_hw_register(dev, hw); + if (ret) + goto rpm_put; + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); + if (ret) + goto rpm_put; + + return 0; + +rpm_put: + pm_runtime_put(dev); + return ret; +} + +static const struct of_device_id vbattb_clk_match[] = { + { .compatible = "renesas,rzg3s-vbattb-clk" }, + { /* sentinel */ } +}; + +static struct platform_driver vbattb_clk_driver = { + .driver = { + .name = "vbattb-clk", + .of_match_table = vbattb_clk_match, + }, + .probe = vbattb_clk_probe, +}; +module_platform_driver(vbattb_clk_driver); + +MODULE_DESCRIPTION("Renesas VBATTB Clock Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); From patchwork Fri Jun 14 07:19:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13697972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CAFBC27C77 for ; Fri, 14 Jun 2024 07:20:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=r7siOFVYUaSSVi4rSlfod3aMeNU0h2Ys5AF3R/iRB18=; b=jK0zCorssa+41SMKRMapU21k6A OZwFrHM33vHbzlZHGP0tn2n+1waWmN2UvX28MoA9rV44v6jtOs6zLu9KA2E9o1Rbd20KSVL67UfnH 82DS7wAxsN7vrN1ZWwo2LFMh7rx2rFVGmmQ2M5GyHqlzE4QEfMS26ZkIyD5u8yqhQRnlesC7sfyZr R6Y+ZRCajz/FIXpXLcrYkYjXsmSAoLgDQQRwQVPmA7e1SOwKaY1V7iHcH/k6KMqN11DwiYRFyoeBn RaKCFeB+sMknFVurr3oG4w0KPLrhutoXFp4tA+j05tCiIY0zI+84H1nuDo6zizYUZI4EPHKhwi+pC gKVPX0mw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sI1ED-00000001jVN-3V24; Fri, 14 Jun 2024 07:20:05 +0000 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sI1E7-00000001jQa-2to8 for linux-arm-kernel@lists.infradead.org; Fri, 14 Jun 2024 07:20:01 +0000 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4218314a6c7so17283225e9.0 for ; Fri, 14 Jun 2024 00:19:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1718349598; x=1718954398; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r7siOFVYUaSSVi4rSlfod3aMeNU0h2Ys5AF3R/iRB18=; b=P9mu5MQKqMNdszkC+OJDRde2sdSKSnJ922DyB8YFU01J/TuiGw8nJQZo77ryeVzmdI 8QAvohoDNqLZk7kuZLS4qBa4hdinEpX0evQ4Qg5YvAaKrOWdd0GvY8XCZIT29azx/Ttk 3ZCpAlHB0bsfCKmGOH9VJHurt+AfTtWHfzK3e/SZgVzN/AAzRYw+fTaTYb6DnDAYf3FX BxXuvF857MZWmCIOrIbf4AMgyuMW6/QC9RCSaj35x/fa3JHufPJKmMDUFU4qFYZT9YqJ vbx5irfNVBcwh4FuFfXdb1GCjzPwQLnGr8JzgY6z8FInaUCq60th1hW/TN28QhJ1RUsN kg1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718349598; x=1718954398; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r7siOFVYUaSSVi4rSlfod3aMeNU0h2Ys5AF3R/iRB18=; b=B4eTCZ7ePhLX20+qTqAFbvGxqEbLbxagUS8pRe2tPUr0qBst1oxpku1bgfdP0GeQLw b7WV+5uCtCwIryCTvuPEt1cmKVxudvNUrL56TPPLK9ZbJjXvO08HOibOLaHznnzdVEJU 6dDR9ldM5ZQmYVOmfFtD9QtG3QeA2PfwdcXhO+MaWVfyRCpI8jV63aurKeBrrexKVqgW /F+2KG8Pao7woTNcbRZ/Xm424mmZGsf22J+RQf1r+5SoHqokShdNVxTXjHAYFq02qeTA D9wxfO/1A+PbFTMPkPOAr0mxr5Ru5VOt1rTbeSEkB8yht/oS+W2IdyF10XXXS0K2wZZ3 YZlA== X-Forwarded-Encrypted: i=1; AJvYcCXmrtokU/e8sj2laJre5GdD4imaW4nRr16TY4U47UcxVig/34Dvnfy+L4qSzu+bplwsJKPrAZ3+9oKyRqyPN9my4qbX5HO/ux+FQOsE7rufbR6ePT8= X-Gm-Message-State: AOJu0Yy4D+7vv5iRtdLeJPZKA3S/DGgramqMenAJhfIVmLOrH1ShNUeN MG2lxJX34Qi6eUbuqhXqVNzo21GQbjAaLEyFb1v6GienmBSfW6d8DiNQUAo7A3s= X-Google-Smtp-Source: AGHT+IHvJbe0MPxxmAy0Jaa+i29h6XRm4HO3GS+nYni4SEUr1oyYsazmbKlbSli1ZCLA+9ThckA7xQ== X-Received: by 2002:a05:600c:a43:b0:421:ad:f104 with SMTP id 5b1f17b1804b1-42304827c4emr19665955e9.10.1718349598308; Fri, 14 Jun 2024 00:19:58 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286eef9eesm87272555e9.9.2024.06.14.00.19.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 00:19:57 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC Date: Fri, 14 Jun 2024 10:19:25 +0300 Message-Id: <20240614071932.1014067-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> References: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240614_001959_754917_20BFF97F X-CRM114-Status: GOOD ( 12.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- .../bindings/rtc/renesas,rzg3s-rtc.yaml | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml new file mode 100644 index 000000000000..0e17f8a36155 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,rzg3s-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Real Time Clock for Renesas RZ/G3S SoC + +maintainers: + - Claudiu Beznea + +properties: + compatible: + const: renesas,rzg3s-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: alarm + - const: period + - const: carry + + clocks: + maxItems: 1 + description: RTC counter clock + + clock-names: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + rtc: rtc@1004ec00 { + compatible = "renesas,rzg3s-rtc"; + reg = <0x1004ec00 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&vbattclk>; + clock-names = "counter"; + status = "disabled"; + }; From patchwork Fri Jun 14 07:19:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13697977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5D64C41513 for ; Fri, 14 Jun 2024 07:20:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286eef9eesm87272555e9.9.2024.06.14.00.19.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 00:19:59 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 06/12] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC Date: Fri, 14 Jun 2024 10:19:26 +0300 Message-Id: <20240614071932.1014067-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> References: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240614_002004_992632_09010701 X-CRM114-Status: GOOD ( 28.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea The RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC has calendar count mode and binary count mode (selectable though RCR2.CNTMD) capabilities, alarm capabilities, clock error correction capabilities. It can generate alarm, period, carry interrupts. Add a driver for RTCA-3 IP. The driver implements calendar count mode (as the conversion b/w RTC and system time is simpler, done with bcd2bin(), bin2bcd()), read and set time, read and set alarm, read and set an offset. Signed-off-by: Claudiu Beznea --- MAINTAINERS | 8 + drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-renesas-rtca3.c | 891 ++++++++++++++++++++++++++++++++ 4 files changed, 910 insertions(+) create mode 100644 drivers/rtc/rtc-renesas-rtca3.c diff --git a/MAINTAINERS b/MAINTAINERS index 670b8201973b..0b4bf350c416 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19173,6 +19173,14 @@ S: Supported F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml F: drivers/counter/rz-mtu3-cnt.c +RENESAS RZ/G3S RTC DRIVER +M: Claudiu Beznea +L: linux-rtc@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml +F: drivers/rtc/rtc-renesas-rtca3.c + RENESAS RZ/N1 A5PSW SWITCH DRIVER M: Clément Léger L: linux-renesas-soc@vger.kernel.org diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 2a95b05982ad..3b29b35e48e0 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1978,6 +1978,16 @@ config RTC_DRV_MA35D1 This driver can also be built as a module, if so, the module will be called "rtc-ma35d1". +config RTC_DRV_RENESAS_RTCA3 + tristate "Renesas RTCA-3 RTC" + depends on ARCH_RENESAS + help + If you say yes here you get support for the Renesas RTCA-3 RTC + available on the Renesas RZ/G3S SoC. + + This driver can also be built as a module, if so, the module + will be called "rtc-rtca3". + comment "HID Sensor RTC drivers" config RTC_DRV_HID_SENSOR_TIME diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 3004e372f25f..52844f13b247 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -157,6 +157,7 @@ obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o obj-$(CONFIG_RTC_DRV_RX8111) += rtc-rx8111.o obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o +obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c new file mode 100644 index 000000000000..e2edf12d0c54 --- /dev/null +++ b/drivers/rtc/rtc-renesas-rtca3.c @@ -0,0 +1,891 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * On-Chip RTC Support available on RZ/G3S SoC + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Counter registers. */ +#define RTCA3_RSECCNT 0x2 +#define RTCA3_RSECCNT_SEC GENMASK(6, 0) +#define RTCA3_RMINCNT 0x4 +#define RTCA3_RMINCNT_MIN GENMASK(6, 0) +#define RTCA3_RHRCNT 0x6 +#define RTCA3_RHRCNT_HR GENMASK(5, 0) +#define RTCA3_RHRCNT_PM BIT(6) +#define RTCA3_RWKCNT 0x8 +#define RTCA3_RWKCNT_WK GENMASK(2, 0) +#define RTCA3_RDAYCNT 0xa +#define RTCA3_RDAYCNT_DAY GENMASK(5, 0) +#define RTCA3_RMONCNT 0xc +#define RTCA3_RMONCNT_MONTH GENMASK(4, 0) +#define RTCA3_RYRCNT 0xe +#define RTCA3_RYRCNT_YEAR GENMASK(7, 0) + +/* Alarm registers. */ +#define RTCA3_RSECAR 0x10 +#define RTCA3_RSECAR_SEC GENMASK(6, 0) +#define RTCA3_RMINAR 0x12 +#define RTCA3_RMINAR_MIN GENMASK(6, 0) +#define RTCA3_RHRAR 0x14 +#define RTCA3_RHRAR_HR GENMASK(5, 0) +#define RTCA3_RHRAR_PM BIT(6) +#define RTCA3_RWKAR 0x16 +#define RTCA3_RWKAR_DAYW GENMASK(2, 0) +#define RTCA3_RDAYAR 0x18 +#define RTCA3_RDAYAR_DATE GENMASK(5, 0) +#define RTCA3_RMONAR 0x1a +#define RTCA3_RMONAR_MON GENMASK(4, 0) +#define RTCA3_RYRAR 0x1c +#define RTCA3_RYRAR_YR GENMASK(7, 0) +#define RTCA3_RYRAREN 0x1e + +/* Alarm enable bit (for all alarm registers). */ +#define RTCA3_AR_ENB BIT(7) + +/* Control registers. */ +#define RTCA3_RCR1 0x22 +#define RTCA3_RCR1_AIE BIT(0) +#define RTCA3_RCR1_CIE BIT(1) +#define RTCA3_RCR1_PIE BIT(2) +#define RTCA3_RCR1_PES GENMASK(7, 4) +#define RTCA3_RCR1_PES_1_64_SEC 0x8 +#define RTCA3_RCR2 0x24 +#define RTCA3_RCR2_START BIT(0) +#define RTCA3_RCR2_RESET BIT(1) +#define RTCA3_RCR2_AADJE BIT(4) +#define RTCA3_RCR2_ADJP BIT(5) +#define RTCA3_RCR2_HR24 BIT(6) +#define RTCA3_RCR2_CNTMD BIT(7) +#define RTCA3_RSR 0x20 +#define RTCA3_RSR_AF BIT(0) +#define RTCA3_RSR_CF BIT(1) +#define RTCA3_RSR_PF BIT(2) +#define RTCA3_RADJ 0x2e +#define RTCA3_RADJ_ADJ GENMASK(5, 0) +#define RTCA3_RADJ_ADJ_MAX 0x3f +#define RTCA3_RADJ_PMADJ GENMASK(7, 6) +#define RTCA3_RADJ_PMADJ_NONE 0 +#define RTCA3_RADJ_PMADJ_ADD 1 +#define RTCA3_RADJ_PMADJ_SUB 2 + +/* Polling operation timeouts. */ +#define RTCA3_DEFAULT_TIMEOUT_US 150 +#define RTCA3_IRQSET_TIMEOUT_US 5000 +#define RTCA3_START_TIMEOUT_US 150000 +#define RTCA3_RESET_TIMEOUT_US 200000 + +/** + * enum rtca3_alrm_set_step - RTCA3 alarm set steps + * @RTCA3_ALRM_SSTEP_DONE: alarm setup done step + * @RTCA3_ALRM_SSTEP_IRQ: two 1/64 periodic IRQs were generated step + * @RTCA3_ALRM_SSTEP_INIT: alarm setup initialization step + */ +enum rtca3_alrm_set_step { + RTCA3_ALRM_SSTEP_DONE = 0, + RTCA3_ALRM_SSTEP_IRQ = 1, + RTCA3_ALRM_SSTEP_INIT = 3, +}; + +/** + * struct rtca3_ppb_per_cycle - PPB per cycle + * @ten_sec: PPB per cycle in 10 seconds adjutment mode + * @sixty_sec: PPB per cycle in 60 seconds adjustment mode + */ +struct rtca3_ppb_per_cycle { + int ten_sec; + int sixty_sec; +}; + +/** + * struct rtca3_priv - RTCA3 private data structure + * @base: base address + * @clk: RTC clock + * @rtc_dev: RTC device + * @set_alarm_completion: alarm setup completion + * @alrm_sstep: alarm setup step (see enum rtca3_alrm_set_step) + * @lock: device lock + * @ppb: ppb per cycle for each the available adjustment modes + * @wakeup_irq: wakeup IRQ + */ +struct rtca3_priv { + void __iomem *base; + struct clk *clk; + struct rtc_device *rtc_dev; + struct completion set_alarm_completion; + atomic_t alrm_sstep; + spinlock_t lock; + struct rtca3_ppb_per_cycle ppb; + int wakeup_irq; +}; + +static void rtca3_byte_update_bits(struct rtca3_priv *priv, u8 off, u8 mask, u8 val) +{ + u8 tmp; + + tmp = readb(priv->base + off); + tmp &= ~(mask); + tmp |= (val & mask); + writeb(tmp, priv->base + off); +} + +static u8 rtca3_alarm_handler_helper(struct rtca3_priv *priv) +{ + u8 val, pending; + + val = readb(priv->base + RTCA3_RSR); + pending = val & RTCA3_RSR_AF; + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return pending; +} + +static irqreturn_t rtca3_alarm_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv = dev_id; + u8 pending; + + spin_lock(&priv->lock); + pending = rtca3_alarm_handler_helper(priv); + spin_unlock(&priv->lock); + + return IRQ_RETVAL(pending); +} + +static irqreturn_t rtca3_periodic_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv = dev_id; + u8 val, pending; + + spin_lock(&priv->lock); + + val = readb(priv->base + RTCA3_RSR); + pending = val & RTCA3_RSR_PF; + + if (pending) { + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (atomic_read(&priv->alrm_sstep) > RTCA3_ALRM_SSTEP_IRQ) { + /* Alarm setup in progress. */ + atomic_dec(&priv->alrm_sstep); + + if (atomic_read(&priv->alrm_sstep) == RTCA3_ALRM_SSTEP_IRQ) { + /* + * We got 2 * 1/64 periodic interrupts. Disable + * interrupt and let alarm setup continue. + */ + rtca3_byte_update_bits(priv, RTCA3_RCR1, + RTCA3_RCR1_PIE, 0); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val, + !(val & RTCA3_RCR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + complete(&priv->set_alarm_completion); + } + } + } + + spin_unlock(&priv->lock); + + return IRQ_RETVAL(pending); +} + +static void rtca3_prepare_cntalrm_regs_for_read(struct rtca3_priv *priv, bool cnt) +{ + /* Offset b/w time and alarm registers. */ + u8 offset = cnt ? 0 : 0xe; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and + * reading from registers) after writing to count registers, alarm + * registers, year alarm enable register, bits RCR2.AADJE, AADJP, + * and HR24 register, we need to do 3 empty reads before being + * able to fetch the registers content. + */ + for (u8 i = 0; i < 3; i++) { + readb(priv->base + RTCA3_RSECCNT + offset); + readb(priv->base + RTCA3_RMINCNT + offset); + readb(priv->base + RTCA3_RHRCNT + offset); + readb(priv->base + RTCA3_RWKCNT + offset); + readb(priv->base + RTCA3_RDAYCNT + offset); + readw(priv->base + RTCA3_RYRCNT + offset); + if (!cnt) + readb(priv->base + RTCA3_RYRAREN); + } +} + +static int rtca3_read_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month, tmp; + unsigned long flags; + u8 trials = 0; + int ret = 0; + u32 year100; + u16 year; + + spin_lock_irqsave(&priv->lock, flags); + + tmp = readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) { + ret = -EINVAL; + goto unlock; + } + + do { + /* Clear carry interrupt. */ + rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_CF, 0); + + /* Read counters. */ + sec = readb(priv->base + RTCA3_RSECCNT); + min = readb(priv->base + RTCA3_RMINCNT); + hour = readb(priv->base + RTCA3_RHRCNT); + wday = readb(priv->base + RTCA3_RWKCNT); + mday = readb(priv->base + RTCA3_RDAYCNT); + month = readb(priv->base + RTCA3_RMONCNT); + year = readw(priv->base + RTCA3_RYRCNT); + + tmp = readb(priv->base + RTCA3_RSR); + + /* + * We cannot generate carries due to reading 64Hz counter as + * the driver doesn't implement carry, thus, carries will be + * generated once per seconds. Add a timeout of 5 trials here + * to avoid infinite loop, if any. + */ + } while ((tmp & RTCA3_RSR_CF) && ++trials < 5); + + if (trials >= 5) { + ret = -ETIMEDOUT; + goto unlock; + } + + tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); + tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINCNT_MIN, min)); + tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRCNT_HR, hour)); + if (hour & RTCA3_RHRCNT_PM) + tm->tm_hour += 12; + tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKCNT_WK, wday)); + tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYCNT_DAY, mday)); + tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONCNT_MONTH, month)) - 1; + year = FIELD_GET(RTCA3_RYRCNT_YEAR, year); + year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20); + tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900; + +unlock: + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} + +static int rtca3_set_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + unsigned long flags; + u8 rcr2, tmp; + int ret; + + spin_lock_irqsave(&priv->lock, flags); + + /* Stop the RTC. */ + rcr2 = readb(priv->base + RTCA3_RCR2); + writeb(rcr2 & ~RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + !(tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + goto unlock; + + /* Update time. */ + writeb(bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECCNT); + writeb(bin2bcd(tm->tm_min), priv->base + RTCA3_RMINCNT); + if (tm->tm_hour > 12) + writeb(RTCA3_RHRCNT_PM | bin2bcd(tm->tm_hour - 12), priv->base + RTCA3_RHRCNT); + else + writeb(bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRCNT); + writeb(bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKCNT); + writeb(bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYCNT); + writeb(bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONCNT); + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRCNT); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, true); + + /* Start RTC. */ + writeb(rcr2 | RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + (tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); + +unlock: + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} + +static int rtca3_alarm_irq_enable_helper(struct rtca3_priv *priv, + unsigned int enabled) +{ + u8 tmp, mask; + + if (enabled) { + rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_AF, 0); + mask = RTCA3_RCR1_AIE; + } else { + mask = 0; + } + + rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_AIE, mask); + return readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + ((tmp & RTCA3_RCR1_AIE) == mask), + 10, RTCA3_IRQSET_TIMEOUT_US); +} + +static int rtca3_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + unsigned long flags; + int ret; + + spin_lock_irqsave(&priv->lock, flags); + ret = rtca3_alarm_irq_enable_helper(priv, enabled); + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} + +static int rtca3_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month; + struct rtc_time *tm = &wkalrm->time; + unsigned long flags; + u32 year100; + u16 year; + + spin_lock_irqsave(&priv->lock, flags); + + sec = readb(priv->base + RTCA3_RSECAR); + min = readb(priv->base + RTCA3_RMINAR); + hour = readb(priv->base + RTCA3_RHRAR); + wday = readb(priv->base + RTCA3_RWKAR); + mday = readb(priv->base + RTCA3_RDAYAR); + month = readb(priv->base + RTCA3_RMONAR); + year = readw(priv->base + RTCA3_RYRAR); + + tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); + tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINAR_MIN, min)); + tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRAR_HR, hour)); + if (hour & RTCA3_RHRAR_PM) + tm->tm_hour += 12; + tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKAR_DAYW, wday)); + tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYAR_DATE, mday)); + tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONAR_MON, month)) - 1; + year = FIELD_GET(RTCA3_RYRAR_YR, year); + year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20); + tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900; + + wkalrm->enabled = !!(readb(priv->base + RTCA3_RCR1) & RTCA3_RCR1_AIE); + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int rtca3_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + struct rtc_time *tm = &wkalrm->time; + unsigned long flags; + u8 rcr1, tmp; + int ret; + + spin_lock_irqsave(&priv->lock, flags); + + tmp = readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) { + ret = -EPERM; + goto unlock; + } + + /* Disable AIE to prevent false interrupts. */ + rcr1 = readb(priv->base + RTCA3_RCR1); + rcr1 &= ~RTCA3_RCR1_AIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + !(tmp & RTCA3_RCR1_AIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + goto unlock; + + /* Set the time and enable the alarm. */ + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_min), priv->base + RTCA3_RMINAR); + if (tm->tm_hour > 12) { + writeb(RTCA3_AR_ENB | RTCA3_RHRAR_PM | bin2bcd(tm->tm_hour - 12), + priv->base + RTCA3_RHRAR); + } else { + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRAR); + } + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONAR); + + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRAR); + writeb(RTCA3_AR_ENB, priv->base + RTCA3_RYRAREN); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, false); + + /* Need to wait for 2 * 1/64 periodic interrupts to be generated. */ + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_INIT); + reinit_completion(&priv->set_alarm_completion); + + /* Enable periodic interrupt. */ + rcr1 |= RTCA3_RCR1_PIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + (tmp & RTCA3_RCR1_PIE), + 10, RTCA3_IRQSET_TIMEOUT_US); + + spin_unlock_irqrestore(&priv->lock, flags); + + if (ret) + goto setup_failed; + + /* Wait for the 2 * 1/64 periodic interrupts. */ + ret = wait_for_completion_interruptible_timeout(&priv->set_alarm_completion, + msecs_to_jiffies(500)); + if (ret <= 0) { + ret = -ETIMEDOUT; + goto setup_failed; + } + + spin_lock_irqsave(&priv->lock, flags); + + ret = rtca3_alarm_irq_enable_helper(priv, wkalrm->enabled); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + +unlock: + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; + +setup_failed: + spin_lock_irqsave(&priv->lock, flags); + /* + * Disable PIE to avoid interrupt storm in case HW needed more than + * specified timeout for setup. + */ + writeb(rcr1 & ~RTCA3_RCR1_PIE, priv->base + RTCA3_RCR1); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & ~RTCA3_RCR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} + +static int rtca3_read_offset(struct device *dev, long *offset) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 val, radj, cycles; + unsigned long flags; + u32 ppb_per_cycle; + + spin_lock_irqsave(&priv->lock, flags); + radj = readb(priv->base + RTCA3_RADJ); + val = readb(priv->base + RTCA3_RCR2); + spin_unlock_irqrestore(&priv->lock, flags); + + cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj); + + if (!cycles) { + *offset = 0; + return 0; + } + + if (val & RTCA3_RCR2_ADJP) + ppb_per_cycle = priv->ppb.ten_sec; + else + ppb_per_cycle = priv->ppb.sixty_sec; + + *offset = cycles * ppb_per_cycle; + val = FIELD_GET(RTCA3_RADJ_PMADJ, radj); + if (val == RTCA3_RADJ_PMADJ_SUB) + *offset = -(*offset); + + return 0; +} + +static int rtca3_set_offset(struct device *dev, long offset) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + int cycles, cycles10, cycles60; + unsigned long flags; + u8 radj, adjp, tmp; + int ret; + + /* + * Automatic time error adjustment could be set at intervals of 10 + * or 60 seconds. + */ + cycles10 = DIV_ROUND_CLOSEST(offset, priv->ppb.ten_sec); + cycles60 = DIV_ROUND_CLOSEST(offset, priv->ppb.sixty_sec); + + /* We can set b/w 1 and 63 clock cycles. */ + if (cycles60 >= -RTCA3_RADJ_ADJ_MAX && + cycles60 <= RTCA3_RADJ_ADJ_MAX) { + cycles = cycles60; + adjp = 0; + } else if (cycles10 >= -RTCA3_RADJ_ADJ_MAX && + cycles10 <= RTCA3_RADJ_ADJ_MAX) { + cycles = cycles10; + adjp = RTCA3_RCR2_ADJP; + } else { + return -ERANGE; + } + + radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); + if (!cycles) + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_NONE); + else if (cycles > 0) + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_ADD); + else + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_SUB); + + spin_lock_irqsave(&priv->lock, flags); + + tmp = readb(priv->base + RTCA3_RCR2); + + if ((tmp & RTCA3_RCR2_ADJP) != adjp) { + /* RADJ.PMADJ need to be set to zero before setting RCR2.ADJP. */ + writeb(0, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, !tmp, + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + goto unlock; + + rtca3_byte_update_bits(priv, RTCA3_RCR2, RTCA3_RCR2_ADJP, adjp); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + ((tmp & RTCA3_RCR2_ADJP) == adjp), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + goto unlock; + } + + writeb(radj, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, (tmp == radj), + 10, RTCA3_DEFAULT_TIMEOUT_US); +unlock: + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} + +static const struct rtc_class_ops rtca3_ops = { + .read_time = rtca3_read_time, + .set_time = rtca3_set_time, + .read_alarm = rtca3_read_alarm, + .set_alarm = rtca3_set_alarm, + .alarm_irq_enable = rtca3_alarm_irq_enable, + .set_offset = rtca3_set_offset, + .read_offset = rtca3_read_offset, +}; + +static int rtca3_initial_setup(struct rtca3_priv *priv) +{ + unsigned long osc32k_rate; + u8 pes, tmp, mask; + u32 sleep_us; + int ret; + + osc32k_rate = clk_get_rate(priv->clk); + if (!osc32k_rate) + return -EINVAL; + + sleep_us = DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6; + + priv->ppb.ten_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 10)); + priv->ppb.sixty_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 60)); + + /* + * According to HW manual (section 22.4.2. Clock and count mode setting procedure) + * we need to wait at least 6 cycles of the 32KHz clock after clock was enabled. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Disable alarm and carry interrupts. */ + mask = RTCA3_RCR1_AIE | RTCA3_RCR1_CIE; + rtca3_byte_update_bits(priv, RTCA3_RCR1, mask, 0); + ret = readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, !(tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* + * Stop the RTC and set to 12 hours mode and calendar count mode. + * RCR2.START initial value is undefined so we need to stop here + * all the time. + */ + mask = RTCA3_RCR2_START | RTCA3_RCR2_HR24 | RTCA3_RCR2_CNTMD; + writeb(0, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Execute reset and wait for reset and calendar count mode to be applied. */ + mask = RTCA3_RCR2_RESET | RTCA3_RCR2_CNTMD; + writeb(RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_RESET_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.3. Notes on writing to and reading + * from registers) after reset we need to wait 6 clock cycles before + * writing to RTC registers. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Set no adjustment. */ + writeb(0, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10, + RTCA3_DEFAULT_TIMEOUT_US); + + /* Start the RTC and enable automatic time error adjustment. */ + mask = RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + writeb(RTCA3_RCR2_START | RTCA3_RCR2_AADJE, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) == mask), + 10, RTCA3_START_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and reading + * from registers) we need to wait 1/128 seconds while the clock is operating + * (RCR2.START bit = 1) to be able to read the counters after a return from + * reset. + */ + usleep_range(8000, 9000); + + /* Set period interrupt to 1/64 seconds. It is necessary for alarm setup. */ + pes = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC); + rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, pes); + return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR1_PES) == pes), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static int rtca3_request_irqs(struct platform_device *pdev, struct rtca3_priv *priv) +{ + struct device *dev = &pdev->dev; + int ret, irq; + + irq = platform_get_irq_byname(pdev, "alarm"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n"); + + ret = devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm", priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n"); + priv->wakeup_irq = irq; + + irq = platform_get_irq_byname(pdev, "period"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get period IRQ!\n"); + + ret = devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-period", priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request period IRQ!\n"); + + /* + * Driver doesn't implement carry handler. Just get the IRQ here + * for backward compatibility, in case carry support will be added later. + */ + irq = platform_get_irq_byname(pdev, "carry"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n"); + + return 0; +} + +static int rtca3_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rtca3_priv *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->clk = devm_clk_get_enabled(dev, "counter"); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + platform_set_drvdata(pdev, priv); + + spin_lock_init(&priv->lock); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + init_completion(&priv->set_alarm_completion); + + ret = rtca3_initial_setup(priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to setup the RTC!\n"); + + ret = rtca3_request_irqs(pdev, priv); + if (ret) + return ret; + + device_init_wakeup(&pdev->dev, 1); + + priv->rtc_dev = devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(priv->rtc_dev)) + return PTR_ERR(priv->rtc_dev); + + priv->rtc_dev->ops = &rtca3_ops; + priv->rtc_dev->max_user_freq = 256; + priv->rtc_dev->range_min = mktime64(1999, 1, 1, 0, 0, 0); + priv->rtc_dev->range_max = mktime64(2098, 12, 31, 23, 59, 59); + + return devm_rtc_register_device(priv->rtc_dev); +} + +static void rtca3_remove(struct platform_device *pdev) +{ + struct rtca3_priv *priv = platform_get_drvdata(pdev); + u8 tmp, mask = RTCA3_RCR1_AIE | RTCA3_RCR1_PIE; + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + /* Disable alarm, periodic interrupt. */ + rtca3_byte_update_bits(priv, RTCA3_RCR1, mask, 0); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & mask), + 10, RTCA3_IRQSET_TIMEOUT_US); + + spin_unlock_irqrestore(&priv->lock, flags); +} + +static int __maybe_unused rtca3_suspend(struct device *dev) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + /* Alarm setup in progress. */ + if (atomic_read(&priv->alrm_sstep) != RTCA3_ALRM_SSTEP_DONE) + return -EBUSY; + + enable_irq_wake(priv->wakeup_irq); + + return 0; +} + +static int rtca3_clean_alarm(struct rtca3_priv *priv) +{ + struct rtc_device *rtc_dev = priv->rtc_dev; + time64_t alarm_time, now; + struct rtc_wkalrm alarm; + unsigned long flags; + struct rtc_time tm; + u8 pending; + int ret; + + ret = rtc_read_alarm(rtc_dev, &alarm); + if (ret) + return ret; + + if (!alarm.enabled) + return 0; + + ret = rtc_read_time(rtc_dev, &tm); + if (ret) + return ret; + + alarm_time = rtc_tm_to_time64(&alarm.time); + now = rtc_tm_to_time64(&tm); + if (alarm_time >= now) + return 0; + + /* + * Heuristically, it has been determined that when returning from deep + * sleep state the RTCA3_RSR.AF is zero even though the alarm expired. + * Call again the rtc_update_irq() if alarm helper detects this. + */ + + spin_lock_irqsave(&priv->lock, flags); + pending = rtca3_alarm_handler_helper(priv); + if (!pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int __maybe_unused rtca3_resume(struct device *dev) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + disable_irq_wake(priv->wakeup_irq); + + /* + * According to the HW manual (section 22.6.4 Notes on writing to + * and reading from registers) we need to wait 1/128 seconds while + * RCR2.START = 1 to be able to read the counters after a return from low + * power consumption state. + */ + mdelay(8); + + /* + * The alarm cannot wake the system from deep sleep states. In case + * we return from deep sleep states and the alarm expired we need + * to disable it to avoid failures when setting another alarm. + */ + return rtca3_clean_alarm(priv); +} + +static SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume); + +static const struct of_device_id rtca3_of_match[] = { + { .compatible = "renesas,rzg3s-rtc", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtca3_of_match); + +static struct platform_driver rtca3_platform_driver = { + .driver = { + .name = "rtc-rtca3", + .pm = &rtca3_pm_ops, + .of_match_table = rtca3_of_match, + }, + .probe = rtca3_probe, + .remove_new = rtca3_remove, +}; +module_platform_driver(rtca3_platform_driver); + +MODULE_DESCRIPTION("Renesas RTCA-3 RTC driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); From patchwork Fri Jun 14 07:19:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13697974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7A9BC27C77 for ; Fri, 14 Jun 2024 07:20:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=kXKVp/I1qd30TXm2YU7BrLpdhU1oFUuJMaRiNvsEfzg=; b=CIY81Rc38DPXmDOtdvCKV7uEnK UQz7O9Ozo35fKH5IlpuPlXTzBiBcQVvfgpwQMoxw5OcMQPjUq+EPRlfAWujIoMJAmSDn/SrA3ssKy 2QR5dKA4PBWStsPXO1tXudvp8CWZwEp5Twu6ay2F5r/wAdh4jCR3qMnUFRDD2bGb21uP0C+MZ1UFd 3SSVkbOfUgXDORaLHvFst5WC2UnvDjepMuSgIL+BtWO86kdJPStg9P/qV7gsaUjn9zQGyHSFpW6T2 +Dlyy1w/1DzdUGSefgxxX2REekOjGbMIyiE2m7SE73oWQvGxC2FRCtzmLP/DRMszXJKaHs8lukU+7 V30AGn0w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sI1Ek-00000001jpy-1Hrg; Fri, 14 Jun 2024 07:20:38 +0000 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sI1EH-00000001jWI-3Ogv for linux-arm-kernel@lists.infradead.org; Fri, 14 Jun 2024 07:20:13 +0000 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-421820fc26dso15971775e9.2 for ; Fri, 14 Jun 2024 00:20:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1718349606; x=1718954406; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kXKVp/I1qd30TXm2YU7BrLpdhU1oFUuJMaRiNvsEfzg=; b=KHtzJ6lq7SQy9HjJ+wVo6HHf+30QRSRTwSyt4cw3XldKzd/nU4rL9NtYoB1IA4XYn/ NqGqi6lTQVTOjlfW3EMzXG/oeBP28eAQ5tgNHbxk5PWmoLOh5XfL8GW5J+VwB2LHhpJn c0Bb2/tFxG00PWblT1e7yvLGi9a7rF5wtmnAXK2/O5wgR2q6e70vCzDWES+snMo7KEXh RSwHKvOkUZOiIcZcYIFDYwX6lmZ/c2PcCi/bl8eE7gJSadddzLNKyw1UeUllOPwLpxwQ ozjez9fwcTlu7yvf5j6YeMYyYgaE5LIZbeb/XJ4CLsFMPZd1uKYZ+fG9dDoTl+V7MqYq iLTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718349606; x=1718954406; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kXKVp/I1qd30TXm2YU7BrLpdhU1oFUuJMaRiNvsEfzg=; b=WLsucaIGA79ghs7rNX4eyn2xF2xpxTKlPflDx6JBxvZCmG4d9nlanlo3k6D/CmRTB3 0/MYVf0ST5KDUKZzAZMb6fp52lRLfZS1vezzfL6AflW9Obr/xlqe9CnLK352QslwpYJS d8GKa4chGJp1Mq4dFihASc3BS6zOmenF2toamk9MdGMXWdFxi/OW8h0hFbjgBEH8GxzO znV7c6IMTgX/IDWcExTF33FBqlKq/vOTInL5WSmN7cXGIwgjrM8Vpc3r5xpVkz17BYHJ sJRXldctk27cn014kj/67Th+F3yrM/4JXXFa88kmJhYnVUKb/Mo43XRoiIQ5fcdigS77 /vyg== X-Forwarded-Encrypted: i=1; AJvYcCVCQPDJX5VqK982C9dzh/rpbL5N/bYcJmOxHAKmEPyHy/hb0MJH6gMEHLT1WQuitmanyYH12WMN2vkUgTifxDvFNzsx5DEeffXdho6OXf0EM/Te0/M= X-Gm-Message-State: AOJu0Yyj6N6m+A3gi4cz43mKvt0eGUkl82j2HuUkCJTSvPp1FV6XtKd0 mKuIbdiPAtChvCvXI33fuEyDD7sHQhqWK5KVFBa8t4zfhl0u56a3y7jhca2C74w= X-Google-Smtp-Source: AGHT+IELHWn4BzKIGJx3SJDAu+6lh0yAH4ZMV9I9BhoPMupkp0AFTyAryhX00A34g6cHm0AlspWEVA== X-Received: by 2002:a05:600c:358d:b0:422:683b:df4d with SMTP id 5b1f17b1804b1-4230481a008mr16406855e9.8.1718349601911; Fri, 14 Jun 2024 00:20:01 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286eef9eesm87272555e9.9.2024.06.14.00.20.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 00:20:01 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 07/12] arm64: dts: renesas: r9a08g045: Add VBATTB node Date: Fri, 14 Jun 2024 10:19:27 +0300 Message-Id: <20240614071932.1014067-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> References: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240614_002010_034501_313B5312 X-CRM114-Status: GOOD ( 10.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Add the DT node for the VBATTB IP along with DT bindings for the clock it provides. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 2162c247d6de..b7bd2e1f3462 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,31 @@ scif0: serial@1004b800 { status = "disabled"; }; + vbattb: vbattb@1005c000 { + compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd"; + reg = <0 0x1005c000 0 0x1000>; + ranges = <0 0 0 0x1005c000 0 0x1000>; + interrupts = ; + interrupt-names = "tampdi"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>; + clock-names = "bclk"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + vbattclk: clock-controller@1c { + compatible = "renesas,rzg3s-vbattb-clk"; + reg = <0 0x1c 0 0x10>; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "vbattb_xtal"; + #clock-cells = <0>; + power-domains = <&cpg>; + status = "disabled"; + }; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a08g045-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -296,4 +321,11 @@ timer { <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; + + vbattb_xtal: vbattb-xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; }; From patchwork Fri Jun 14 07:19:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13697973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB6A9C27C6E for ; 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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286eef9eesm87272555e9.9.2024.06.14.00.20.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 00:20:07 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 08/12] arm64: dts: renesas: r9a08g045: Add RTC node Date: Fri, 14 Jun 2024 10:19:28 +0300 Message-Id: <20240614071932.1014067-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> References: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240614_002010_312688_1D89A2FB X-CRM114-Status: UNSURE ( 9.19 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index b7bd2e1f3462..88a20c954ca6 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,18 @@ scif0: serial@1004b800 { status = "disabled"; }; + rtc: rtc@1004ec00 { + compatible = "renesas,rzg3s-rtc"; + reg = <0 0x1004ec00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&vbattclk>; + clock-names = "counter"; + status = "disabled"; + }; + vbattb: vbattb@1005c000 { compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd"; reg = <0 0x1005c000 0 0x1000>; From patchwork Fri Jun 14 07:19:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13697976 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85A7CC27C6E for ; Fri, 14 Jun 2024 07:20:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=QbQrIqY2eU2jnbuMgO8MBbRBaF6tXHcA5GNB0e2E/Yg=; b=in3wtZZEdTsLIT224TjSL9e+N+ MPJ5SEcX3R2ShzwVZoL7XrHj9Qj6WQV7xnnQwnqOYjpMBhPSPZe0e0KSbH5930XtsIIFzcpK/tZJm hq8EjBCWGsKT1TMBeVb+AYRhWggQoE8GAHxCa6z78ur9Qr82QoGOR8/rfVAnFk3kIj50b0+8aZSQL A1CZrFKLqbcZcbpk6dspijVpUAGUIe7xvN66eXe4ZuW1UUQVzQseBOwhSnC192ll7FykVm697n2qZ mpSiaQHk2SKwIyLYmx+fFEHoycned7D03c2eGGcqR6YJIRDL/yGViWkZL4FqYu5tnpHqG4jzpqPyZ p/8s9SWg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sI1Em-00000001jr8-1GNH; Fri, 14 Jun 2024 07:20:40 +0000 Received: from mail-lj1-x233.google.com ([2a00:1450:4864:20::233]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sI1EK-00000001jZk-33UT for linux-arm-kernel@lists.infradead.org; Fri, 14 Jun 2024 07:20:15 +0000 Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2e724bc466fso21286221fa.3 for ; Fri, 14 Jun 2024 00:20:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1718349610; x=1718954410; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QbQrIqY2eU2jnbuMgO8MBbRBaF6tXHcA5GNB0e2E/Yg=; b=B0GSLuTddHdYr6oJNuyOGz2BWeK45KBy/KgkVD1mVpqNnfttiWvicVKD1djPhMKewZ q/S8509ugNw8vPGRZt0brdYIvfyfCScBAxzwoe4j/Tu+33Y9hzdySdJPvaBUwkl10aAv 1KPAj4fWVrTSjmNJEEeEpzg73s89enPtudxJGzmga4vRmTbFEVGjBuprDEoiGRtYbziX Zfb+kVyd//ERxLpcw3MuNlZiH3HMVztFNalGdb4edaPec8whzsuTqQMlmvxiVqaEpoQp eIU1ol9yJVkUsTNNauY7VFI93l+vtvZ9erB+xjJ5g4HRj+WQI2uK2K2zFcJb7ZQQQAyC 0jkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718349610; x=1718954410; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QbQrIqY2eU2jnbuMgO8MBbRBaF6tXHcA5GNB0e2E/Yg=; b=pULXHy6Lj6JtaQ/PTRCs4FEMYP6aSujwXvrJCemx084CnqZOH7FZJdRBKox3p7N55U 1C/jxSZWmPLWN1sE16i11XTNF+AKKQilzHdsERoiY+2wdGl3+MZ77ly26lcCP2dPfmXm vCVKrfFlNgPN0g8AfwGH6UxVqjPgsuOQqBygCBNbhnNada+v84DMA0ZNR63F+6bCUcKN WJmgInmz9U7vGY1nUy1oyG96WLw6MGBfpW5Zdf4t3tfVKWO9JRQVHifl759tjzor9bqU 9eXntE9A0wKOcGBQrX2jeGB2WKYWcSRFPNUldmmSuEUdhcyrD2xxEaczJEbVZDAuKrLX Oufg== X-Forwarded-Encrypted: i=1; AJvYcCUWvlTCWjYT4AiLwu3jol5eeQWiqW8hSg+jQtX7Rwm2QXT2Yn2Eam1mka41+SXERMu2NaWT/q1KgMDGi9jChD9ckZf0aMjGi2Q3POB8qetad8SrY64= X-Gm-Message-State: AOJu0YzTyFIKyEYUBmBSfuhjY4+EkNq9O/GmtYiXcnOtQ0JEt8zFLUrl z5OPrncDsH+Q1zcgpCJwVRPotA9s2081WNC+ZMp2Ii4vYPw+AG0e22bWeAIpB14= X-Google-Smtp-Source: AGHT+IFZZkLDeJzXHvlYCemJLbFCg9wPwBeMniUyHJS2jzufU48y7tXw4OjUh61TsSRxd6/LsiaPGg== X-Received: by 2002:a2e:808c:0:b0:2eb:df11:ca0b with SMTP id 38308e7fff4ca-2ec0e5c6bf3mr16572681fa.14.1718349610351; Fri, 14 Jun 2024 00:20:10 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286eef9eesm87272555e9.9.2024.06.14.00.20.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 00:20:09 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 09/12] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB clock Date: Fri, 14 Jun 2024 10:19:29 +0300 Message-Id: <20240614071932.1014067-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> References: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240614_002013_127918_5A31166B X-CRM114-Status: UNSURE ( 9.26 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Enable the VBATTB clock controller. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 8a3d302f1535..517ce275916a 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -341,6 +341,19 @@ mux { }; }; +&vbattb_xtal { + clock-frequency = <32768>; +}; + +&vbattb { + status = "okay"; +}; + +&vbattclk { + renesas,vbattb-load-nanofarads = <12500>; + status = "okay"; +}; + &wdt0 { timeout-sec = <60>; status = "okay"; From patchwork Fri Jun 14 07:19:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13697975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21039C41513 for ; Fri, 14 Jun 2024 07:20:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Z3KEj0xEDN1Ax2G/RC5gQRFWvCzGHgOqwoRcyc6hKKA=; b=3Xwp0dGNKpfm5MoCnwg7pH3+79 r75UeEstkte6aYis+TtoWXn6HeqsyuVRRyKxTr7UOf2xHmfJb2ralbnl8nPHXoRed6os97R+5wgxV 0JESxSRUuUMjF3631uXm9vdHWE19StFmzzfucmiYlHo4s+Y3Eem1BREGNLAsA2YKjqfH+oMdJdkr0 9CTktEDyHePNBEwt/jxx/vcai3irbeGmM4bk3OkETTU/rdSsAnXWyFUtScphWN2mzKJHmMOpl5/Uh cXsEwg5CSXgk+P8lFy9VdZ22294c1Eyn3/s3zEhczKZQWjcdFySjUFrlgxgOddO8JjhkO0Kgg9ZLp floSvmlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sI1En-00000001jrk-19xh; Fri, 14 Jun 2024 07:20:41 +0000 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sI1EM-00000001jb4-0ZUv for linux-arm-kernel@lists.infradead.org; Fri, 14 Jun 2024 07:20:16 +0000 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-42189d3c7efso20810985e9.2 for ; Fri, 14 Jun 2024 00:20:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1718349612; x=1718954412; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z3KEj0xEDN1Ax2G/RC5gQRFWvCzGHgOqwoRcyc6hKKA=; b=a0UNEqAVONqXmMWKoOJpzshCde89zBdsVwrlREQHAqa4SEFU7r4ygUJVIwpSo76D4F WT+bSUDFc/Y8223yTb0AzhkFWW5ECXrKkco7Tg7mAqpvXqEeANLTn/t1JbhmNo1/pa8r FI7VBdx5biS0K4xczl7FWg9H1XGJ3SyHQb7KiRyBvWhNSbLfBgBeVGLgYh3BW8ynPfxX 52Ioa6QtSiaKVJ61DpmSdVlx1HOYq58cOk29ULrNSyiNcFBKdcib5UVc6qBCjEFeCxte nhCiHSWhtXV6v9v3uGy87XiNeKv8rP7h3BoUKeJliS16mzne9DVqjyGv0dT3XojNJI26 uP9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718349612; x=1718954412; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z3KEj0xEDN1Ax2G/RC5gQRFWvCzGHgOqwoRcyc6hKKA=; b=BQ4E8N7jxtkD8VdfdLgnanS+W/VVkqQ4gt8P3a2jAD12UIYrb/o0BG4WDfDHTEggRH +6382mgf+pN1P1E1iZNONZHYCHR4kyxUAumn4UTlsZ5fcMJeYyKII6ix6obulxbCbLKn GwPepy5GnOx3r9XDSaRBljJxuXiJn6BfoMG4CjpOanIv10iGZ/KnvvlOSvFIuf2HkE64 FFreyEueLnc3CTZlobQXkDEOuzGffobwu13IsZTtHNul92RJ6poSK0H7jwxNV1D2+OD9 ZFlTTkFjyhpR9crKpe/K6MXFget18AgebU+eBtfnJpT21Ao7IwL+o6SBxewrjEFoUJNO /NRw== X-Forwarded-Encrypted: i=1; AJvYcCUDVmYrIFAW2AnBVXyQTskOretgsxI/PpWWCdvjew32zh12gLbHDhEAA4+jhBcKT8wc8KPhtsgqvyuSHAi/J1VvRCrSJOyiJzhepjyG5VSi6phY8n4= X-Gm-Message-State: AOJu0Yz4g17lwbn4oYgIv21UmkTl7FofYl6xNaisyTibr5fAicWOwcah kLNSXiVAxMeAeywmKH6+r7bdAaIxMW1HLYP/FYuZ12xSIBBbyCVCvmz1bD7wyyE= X-Google-Smtp-Source: AGHT+IERYkDmu/GQZcsA7JnGF3XH8j0KFhCh57EyDaAQ7G6QLfCcYTHe4SjtRlsH0Gxh6NSndlHjKA== X-Received: by 2002:a05:600c:a44:b0:421:7f07:92cf with SMTP id 5b1f17b1804b1-4230484c563mr21714755e9.36.1718349612467; Fri, 14 Jun 2024 00:20:12 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286eef9eesm87272555e9.9.2024.06.14.00.20.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 00:20:11 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 10/12] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC Date: Fri, 14 Jun 2024 10:19:30 +0300 Message-Id: <20240614071932.1014067-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> References: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240614_002014_608487_482F24D0 X-CRM114-Status: UNSURE ( 8.96 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Enable RTC. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 517ce275916a..82a80fd8e7ec 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -341,6 +341,10 @@ mux { }; }; +&rtc { + status = "okay"; +}; + &vbattb_xtal { clock-frequency = <32768>; }; From patchwork Fri Jun 14 07:19:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13697978 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5686AC27C77 for ; Fri, 14 Jun 2024 07:20:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bBQryArzwC0pcpfTb6INLK/D8vEzmJaod3AONhND7ow=; b=SuMMT+aKnPHESVwWw34Lv0id/j KRJySECTJ0ylT+iEQnQBxABsQCgZcpBmnY2B8a6QxVQOIXW2WnvTTceZaFvIXRfX2is8EzB9mLtn+ Dr5ofe0wGzTFTIVj8lHKstT+B6IlR1pQM5kq9GzzfSJr5azKH8L9+IlrMc4V10hA4l+4hSxsrQtTK Bw9E1/4NUJnWgvfghtSAuDLzPOfrZSrh2wjjCh6/HMg9FiXxSmzaavNzT4a4l/at1jkecr/oKDgeA oQY0w2GPp0hcs8aMyWn00HxNILRfwhKqp2YdRYcdeUhmyn7bgYR1Ri2QBG+UvPJYXnpFerq2/TUc3 Mi4KGLEw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sI1Eo-00000001jsn-2NgS; Fri, 14 Jun 2024 07:20:42 +0000 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sI1EO-00000001jdC-0tj3 for linux-arm-kernel@lists.infradead.org; Fri, 14 Jun 2024 07:20:18 +0000 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-42249a4f9e4so13308325e9.2 for ; Fri, 14 Jun 2024 00:20:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1718349614; x=1718954414; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bBQryArzwC0pcpfTb6INLK/D8vEzmJaod3AONhND7ow=; b=P7K14obQ7Zik0DP+YgTnPJAknrm8r2lxPO8av6iEbynE101AauXsgzGauHKg5gTeV5 Py/vObo0WS1wUzuveJ+ONI9kuPN9hxWI8LBv/kwpSDX2jdTJTidsrZqKFKwnrQ1nrS+i /Mk4ULM1DKMaeBwCw5Aha7pm+dOOS8KctA9XGOX3tCvFHzcEXp64AT/gdOp7eHwOb3PH VQY9MarO+LRrcgE9l3rx9S5U1es8jDzK3flwmvXxh2JLpN1jnlkTVpiOLOpNJSOFkbfc 5P12cHNNigcISPJwYnOxHjaVDuqeE1OgCzFLo3dCDyD5PXzIXKy/jwDuozGwPREUp/H9 1KfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718349614; x=1718954414; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bBQryArzwC0pcpfTb6INLK/D8vEzmJaod3AONhND7ow=; b=j0e7LD4zVPeL/tfvmMO7WMZcgASqEM+e8N51pOF+7ulpE9VFYBO2riyvt59yLU6A5c DDoTI1pJzmz+uPByKeQlxiTjIkxw8NQt2ecQns1X/RongDvOABOoKdsVl14IvOMp1oFC Ujbd3xkWinzT0/4TMCWnuEHV0RlGvRxDaGeQroE3tvQYC0wdorOIqJ/Mj2VzIjXeOY4B 1mODFZPvk5gkOjPHQlaZMOv8ylq9rIwNmkJ4zws+usr0zy4KOLPMQYnRApHPPRmzpW2Z OANDce8bm7bEqzr4S8gX83kfVYT4Uh/uHXN8eK8UHBf9+eG/YFCAJMHYOwboO0xGIuNb IHeg== X-Forwarded-Encrypted: i=1; AJvYcCV+8hVouYrm6COHq2LQjFPkdNBebSJLa08JiDtIw2YfgRP5H48N/pkhcLj375KkDI4c7Z4MYqom76QXcK039W+g9HZunWxmgzYkxYhYCm+nv5PkfpQ= X-Gm-Message-State: AOJu0YzakbZHgoXJoEOW6G5HXRO1aW/gCB7tb+fEzcci1cenYxgayPbE iZnvOQU0yQ9Ih0c73QtMykMxIesAv6OorJeArOVlIbwSlw3U0uQ0IktYtNaqess= X-Google-Smtp-Source: AGHT+IHPaQD10DLPhpZ7aY3WCufuA4Kxyjs3R72r9aYkAI7AVznPL9Zts5GX/ZtfATd4xeTNB6QBsg== X-Received: by 2002:a05:600c:45c7:b0:422:727c:70b1 with SMTP id 5b1f17b1804b1-4230481f0cbmr18120785e9.8.1718349614367; Fri, 14 Jun 2024 00:20:14 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286eef9eesm87272555e9.9.2024.06.14.00.20.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 00:20:13 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 11/12] arm64: defconfig: Enable VBATTB clock flag Date: Fri, 14 Jun 2024 10:19:31 +0300 Message-Id: <20240614071932.1014067-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> References: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240614_002016_444538_14D5227E X-CRM114-Status: UNSURE ( 8.09 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Enable VBATTB clock driver flag (CONFIG_CLK_VBATTB). Signed-off-by: Claudiu Beznea --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 05abba0a0209..fcb0c7ee8769 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1348,6 +1348,7 @@ CONFIG_SM_VIDEOCC_8250=y CONFIG_QCOM_HFPLL=y CONFIG_CLK_GFM_LPASS_SM8250=m CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y +CONFIG_CLK_VBATTB=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_TEGRA186_TIMER=y From patchwork Fri Jun 14 07:19:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13697979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF704C27C6E for ; Fri, 14 Jun 2024 07:20:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=yLVszOBXKdCsK5qaPuAoiXu9R/5md9OnkOvi6MZ6Vqw=; b=3gL9cZ5rDMSWDgz/O669KDYCUE rjJTILBuDJrmvqnMrymZQ3C2koRku6JrVxd1HF1gRgCEy1MiETSkRUqUo2bUdwMRO1xYI3pVLjfop kNcLbylO+atMr5j3btbAnUTdOrrxaR0DZvY6pwtMPE2ex93FFAmYldphYfiGyo/xdHscX2fm7mWps xrEWU3z8DhaVaGTyU622SS+Io7uC8wdjbAxMweFJzLz/vGUsyl8UpK7a3l7XofM3t9P+14y/7ePsj 6SUb5C4DmoGTuRIsNFzmaB0K+zHPtsrT4Lf83eZl4Zt8ACqukVStZI9KSretSYY/DjLs2Z2ex4THm mYeMApkQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sI1Eq-00000001ju0-0h4k; Fri, 14 Jun 2024 07:20:44 +0000 Received: from mail-lf1-x129.google.com ([2a00:1450:4864:20::129]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sI1EQ-00000001jex-0FEw for linux-arm-kernel@lists.infradead.org; Fri, 14 Jun 2024 07:20:20 +0000 Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-52bc3130ae6so2098114e87.3 for ; Fri, 14 Jun 2024 00:20:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1718349616; x=1718954416; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yLVszOBXKdCsK5qaPuAoiXu9R/5md9OnkOvi6MZ6Vqw=; b=OgCWEfcBy7JCHLRRgHIXc0Upf/+AxRq247YF8VyfkMtuNm+Aae855ocisU0ty1W/lS yBGAzZd2azz3wEnzwle2EDzedoRzSWKrJMa2oXz6qZGlg2jJ2syApFDCt8zF5cDVOH47 uCbQP5NCE378Aa6/Ad0L713cJGfMbqsm8tp9k81n4/mEN5I23sCcAorL+GxZpWcL9KzD BGJd11Xf/p8UCpFO5+S/TDhohZWWjslpd4inWxeoeUp7YrEdcLjP7+akWbGtQSPRkrv0 cV8JMECrDi2NHAwE9dCkiX0yOMLIal05gjta/aTyO95qmVeYSSoKSVOBqABPpjcnqV9b W5+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718349616; x=1718954416; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yLVszOBXKdCsK5qaPuAoiXu9R/5md9OnkOvi6MZ6Vqw=; b=T/N6pqc79vlb5k1nvskns1lqytNUnQJGMPIJYfPstzCe+j0m9SlXv1xOhdJwsPMY2D pk6WtnfRiO4xp3Uai5srlX6TRpGCjP8spYJlY/Vk6cGLynrfKzCUqk/BP2shSLIG1F7t QUKEfmHueByXBrq1SIfmoxW23DWnbnKGo6SPiSjsb4TYqVEy/vTO2TXK75Dw/xmvAJmi ME8jIHBAEcJfe9y1Awzeqf3CyBXjZwHWeC8SLgqX1ERsy6GB45HHb3JTgRLnCFcxmoEj 1vbQL2WF4Mx968Gq557pjUENaZe4K2vGENsdVd8xVL+ceXeMeEHzbP7GCeCaIkZzrH6x iBKQ== X-Forwarded-Encrypted: i=1; AJvYcCWTOaDDtuKHUkLBs0x2TdbTeCuYnqgAJLDRyBqRhZptFKIM+29DApoBrg+vwGa7tTvUrhTY1lJD//jJQy/35qVq+2kgWQlnHEh2D0LyoURFmdF4iXo= X-Gm-Message-State: AOJu0Yyf//RKZ4xKUgUyQ/rEsmXEWJ76kYEHu9zBTP7ht2w2ja0L9fbY CUtXqBYoSWT0b9Ht9hPAobscabWPBCDCbtKviQw19x95Xcd40EWne2+N0RngSD4= X-Google-Smtp-Source: AGHT+IElxpc841rHD2Xiu2oaf6mrTuypBvT7Rrfq0KAuW6+UruOfjHi/qGNE1rhY2ZoG24NezULOsQ== X-Received: by 2002:ac2:4181:0:b0:516:d219:3779 with SMTP id 2adb3069b0e04-52ca6e99397mr1027545e87.58.1718349616181; Fri, 14 Jun 2024 00:20:16 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286eef9eesm87272555e9.9.2024.06.14.00.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 00:20:15 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 12/12] arm64: defconfig: Enable Renesas RTCA-3 flag Date: Fri, 14 Jun 2024 10:19:32 +0300 Message-Id: <20240614071932.1014067-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> References: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240614_002018_329633_10F7AF2D X-CRM114-Status: UNSURE ( 8.24 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Claudiu Beznea Enable Renesas RTCA-3 flag for the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index fcb0c7ee8769..86e74da7a9c9 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1202,6 +1202,7 @@ CONFIG_RTC_DRV_IMX_SC=m CONFIG_RTC_DRV_MT6397=m CONFIG_RTC_DRV_XGENE=y CONFIG_RTC_DRV_TI_K3=m +CONFIG_RTC_DRV_RENESAS_RTCA3=y CONFIG_DMADEVICES=y CONFIG_DMA_BCM2835=y CONFIG_DMA_SUN6I=m