From patchwork Fri Jun 14 10:12:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13698505 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22754C27C79 for ; Fri, 14 Jun 2024 10:13:18 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.8276.1718359994763562701 for ; Fri, 14 Jun 2024 03:13:16 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.08,237,1712588400"; d="scan'208";a="207938150" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 14 Jun 2024 19:13:15 +0900 Received: from localhost.localdomain (unknown [10.226.92.95]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id DBEA6428BB21; Fri, 14 Jun 2024 19:13:13 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 5.10.y-cip 01/14] drm: Place Renesas drivers in a separate dir Date: Fri, 14 Jun 2024 11:12:55 +0100 Message-Id: <20240614101308.40407-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> References: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 14 Jun 2024 10:13:18 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16234 commit 11696c5e89245a1d360f75be3dfc4960b25a265a upstream. Create vendor specific renesas directory and move renesas drivers to that directory. Signed-off-by: Biju Das Acked-by: Kieran Bingham Reviewed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart [ Biju: Dropped {rcar_mipi_dsi.c, rcar_mipi_dsi.h, rcar_mipi_dsi_regs.h} as support not available in 5.10 Manually moved the 5.10 files rcar_du_of.{c,h} and rcar_du_of_lvds_r8a779{0,1,3,5,6}.dts to drivers/gpu/drm/renesas/ directory ] Signed-off-by: Biju Das --- MAINTAINERS | 1 + drivers/gpu/drm/Kconfig | 4 +- drivers/gpu/drm/Makefile | 3 +- drivers/gpu/drm/renesas/Kconfig | 4 + drivers/gpu/drm/renesas/Makefile | 4 + drivers/gpu/drm/{ => renesas}/rcar-du/Kconfig | 0 .../gpu/drm/{ => renesas}/rcar-du/Makefile | 0 .../gpu/drm/{ => renesas}/rcar-du/rcar_cmm.c | 0 .../gpu/drm/{ => renesas}/rcar-du/rcar_cmm.h | 0 .../drm/{ => renesas}/rcar-du/rcar_du_crtc.c | 0 .../drm/{ => renesas}/rcar-du/rcar_du_crtc.h | 0 .../drm/{ => renesas}/rcar-du/rcar_du_drv.c | 0 .../drm/{ => renesas}/rcar-du/rcar_du_drv.h | 0 .../{ => renesas}/rcar-du/rcar_du_encoder.c | 0 .../{ => renesas}/rcar-du/rcar_du_encoder.h | 0 .../drm/{ => renesas}/rcar-du/rcar_du_group.c | 0 .../drm/{ => renesas}/rcar-du/rcar_du_group.h | 0 .../drm/{ => renesas}/rcar-du/rcar_du_kms.c | 0 .../drm/{ => renesas}/rcar-du/rcar_du_kms.h | 0 drivers/gpu/drm/renesas/rcar-du/rcar_du_of.c | 323 ++++++++++++++++++ drivers/gpu/drm/renesas/rcar-du/rcar_du_of.h | 20 ++ .../rcar-du/rcar_du_of_lvds_r8a7790.dts | 69 ++++ .../rcar-du/rcar_du_of_lvds_r8a7791.dts | 43 +++ .../rcar-du/rcar_du_of_lvds_r8a7793.dts | 43 +++ .../rcar-du/rcar_du_of_lvds_r8a7795.dts | 43 +++ .../rcar-du/rcar_du_of_lvds_r8a7796.dts | 43 +++ .../drm/{ => renesas}/rcar-du/rcar_du_plane.c | 0 .../drm/{ => renesas}/rcar-du/rcar_du_plane.h | 0 .../drm/{ => renesas}/rcar-du/rcar_du_regs.h | 0 .../drm/{ => renesas}/rcar-du/rcar_du_vsp.c | 0 .../drm/{ => renesas}/rcar-du/rcar_du_vsp.h | 0 .../{ => renesas}/rcar-du/rcar_du_writeback.c | 0 .../{ => renesas}/rcar-du/rcar_du_writeback.h | 0 .../drm/{ => renesas}/rcar-du/rcar_dw_hdmi.c | 0 .../gpu/drm/{ => renesas}/rcar-du/rcar_lvds.c | 0 .../gpu/drm/{ => renesas}/rcar-du/rcar_lvds.h | 0 .../{ => renesas}/rcar-du/rcar_lvds_regs.h | 0 .../{ => renesas}/rcar-du/rzg2l_mipi_dsi.c | 0 .../rcar-du/rzg2l_mipi_dsi_regs.h | 0 .../gpu/drm/{ => renesas}/shmobile/Kconfig | 0 .../gpu/drm/{ => renesas}/shmobile/Makefile | 0 .../shmobile/shmob_drm_backlight.c | 0 .../shmobile/shmob_drm_backlight.h | 0 .../{ => renesas}/shmobile/shmob_drm_crtc.c | 0 .../{ => renesas}/shmobile/shmob_drm_crtc.h | 0 .../{ => renesas}/shmobile/shmob_drm_drv.c | 0 .../{ => renesas}/shmobile/shmob_drm_drv.h | 0 .../{ => renesas}/shmobile/shmob_drm_kms.c | 0 .../{ => renesas}/shmobile/shmob_drm_kms.h | 0 .../{ => renesas}/shmobile/shmob_drm_plane.c | 0 .../{ => renesas}/shmobile/shmob_drm_plane.h | 0 .../{ => renesas}/shmobile/shmob_drm_regs.h | 0 52 files changed, 595 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/renesas/Kconfig create mode 100644 drivers/gpu/drm/renesas/Makefile rename drivers/gpu/drm/{ => renesas}/rcar-du/Kconfig (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/Makefile (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_cmm.c (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_cmm.h (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_crtc.c (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_crtc.h (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_drv.c (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_drv.h (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_encoder.c (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_encoder.h (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_group.c (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_group.h (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_kms.c (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_kms.h (100%) create mode 100644 drivers/gpu/drm/renesas/rcar-du/rcar_du_of.c create mode 100644 drivers/gpu/drm/renesas/rcar-du/rcar_du_of.h create mode 100644 drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7790.dts create mode 100644 drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7791.dts create mode 100644 drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7793.dts create mode 100644 drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7795.dts create mode 100644 drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7796.dts rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_plane.c (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_plane.h (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_regs.h (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_vsp.c (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_vsp.h (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_writeback.c (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_du_writeback.h (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_dw_hdmi.c (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_lvds.c (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_lvds.h (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rcar_lvds_regs.h (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rzg2l_mipi_dsi.c (100%) rename drivers/gpu/drm/{ => renesas}/rcar-du/rzg2l_mipi_dsi_regs.h (100%) rename drivers/gpu/drm/{ => renesas}/shmobile/Kconfig (100%) rename drivers/gpu/drm/{ => renesas}/shmobile/Makefile (100%) rename drivers/gpu/drm/{ => renesas}/shmobile/shmob_drm_backlight.c (100%) rename drivers/gpu/drm/{ => renesas}/shmobile/shmob_drm_backlight.h (100%) rename drivers/gpu/drm/{ => renesas}/shmobile/shmob_drm_crtc.c (100%) rename drivers/gpu/drm/{ => renesas}/shmobile/shmob_drm_crtc.h (100%) rename drivers/gpu/drm/{ => renesas}/shmobile/shmob_drm_drv.c (100%) rename drivers/gpu/drm/{ => renesas}/shmobile/shmob_drm_drv.h (100%) rename drivers/gpu/drm/{ => renesas}/shmobile/shmob_drm_kms.c (100%) rename drivers/gpu/drm/{ => renesas}/shmobile/shmob_drm_kms.h (100%) rename drivers/gpu/drm/{ => renesas}/shmobile/shmob_drm_plane.c (100%) rename drivers/gpu/drm/{ => renesas}/shmobile/shmob_drm_plane.h (100%) rename drivers/gpu/drm/{ => renesas}/shmobile/shmob_drm_regs.h (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 8f2e94c0ec19..ab7997f96fed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5893,6 +5893,7 @@ F: Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml F: Documentation/devicetree/bindings/display/renesas,du.txt F: drivers/gpu/drm/rcar-du/ F: drivers/gpu/drm/shmobile/ +F: drivers/gpu/drm/renesas/ F: include/linux/platform_data/shmob_drm.h DRM DRIVERS FOR ROCKCHIP diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 4e9b3a95fa7c..f9709a2dd1f0 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -319,9 +319,7 @@ source "drivers/gpu/drm/armada/Kconfig" source "drivers/gpu/drm/atmel-hlcdc/Kconfig" -source "drivers/gpu/drm/rcar-du/Kconfig" - -source "drivers/gpu/drm/shmobile/Kconfig" +source "drivers/gpu/drm/renesas/Kconfig" source "drivers/gpu/drm/sun4i/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 81569009f884..cd8b2d372b5e 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -88,8 +88,7 @@ obj-$(CONFIG_DRM_UDL) += udl/ obj-$(CONFIG_DRM_AST) += ast/ obj-$(CONFIG_DRM_ARMADA) += armada/ obj-$(CONFIG_DRM_ATMEL_HLCDC) += atmel-hlcdc/ -obj-y += rcar-du/ -obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/ +obj-y += renesas/ obj-y += omapdrm/ obj-$(CONFIG_DRM_SUN4I) += sun4i/ obj-y += tilcdc/ diff --git a/drivers/gpu/drm/renesas/Kconfig b/drivers/gpu/drm/renesas/Kconfig new file mode 100644 index 000000000000..3777dad17f81 --- /dev/null +++ b/drivers/gpu/drm/renesas/Kconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +source "drivers/gpu/drm/renesas/rcar-du/Kconfig" +source "drivers/gpu/drm/renesas/shmobile/Kconfig" diff --git a/drivers/gpu/drm/renesas/Makefile b/drivers/gpu/drm/renesas/Makefile new file mode 100644 index 000000000000..ec0e89e7a592 --- /dev/null +++ b/drivers/gpu/drm/renesas/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += rcar-du/ +obj-$(CONFIG_DRM_SHMOBILE) += shmobile/ diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/renesas/rcar-du/Kconfig similarity index 100% rename from drivers/gpu/drm/rcar-du/Kconfig rename to drivers/gpu/drm/renesas/rcar-du/Kconfig diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/renesas/rcar-du/Makefile similarity index 100% rename from drivers/gpu/drm/rcar-du/Makefile rename to drivers/gpu/drm/renesas/rcar-du/Makefile diff --git a/drivers/gpu/drm/rcar-du/rcar_cmm.c b/drivers/gpu/drm/renesas/rcar-du/rcar_cmm.c similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_cmm.c rename to drivers/gpu/drm/renesas/rcar-du/rcar_cmm.c diff --git a/drivers/gpu/drm/rcar-du/rcar_cmm.h b/drivers/gpu/drm/renesas/rcar-du/rcar_cmm.h similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_cmm.h rename to drivers/gpu/drm/renesas/rcar-du/rcar_cmm.h diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_crtc.c rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h b/drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.h similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_crtc.h rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.h diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_drv.c rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.h similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_drv.h rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.h diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_encoder.c similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_encoder.c rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_encoder.c diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h b/drivers/gpu/drm/renesas/rcar-du/rcar_du_encoder.h similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_encoder.h rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_encoder.h diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_group.c rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.h b/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.h similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_group.h rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_group.h diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_kms.c rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.h b/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.h similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_kms.h rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.h diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_of.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_of.c new file mode 100644 index 000000000000..afef69669bb4 --- /dev/null +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_of.c @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * rcar_du_of.c - Legacy DT bindings compatibility + * + * Copyright (C) 2018 Laurent Pinchart + * + * Based on work from Jyri Sarha + * Copyright (C) 2015 Texas Instruments + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "rcar_du_crtc.h" +#include "rcar_du_drv.h" +#include "rcar_du_of.h" + +/* ----------------------------------------------------------------------------- + * Generic Overlay Handling + */ + +struct rcar_du_of_overlay { + const char *compatible; + void *begin; + void *end; +}; + +#define RCAR_DU_OF_DTB(type, soc) \ + extern char __dtb_rcar_du_of_##type##_##soc##_begin[]; \ + extern char __dtb_rcar_du_of_##type##_##soc##_end[] + +#define RCAR_DU_OF_OVERLAY(type, soc) \ + { \ + .compatible = "renesas,du-" #soc, \ + .begin = __dtb_rcar_du_of_##type##_##soc##_begin, \ + .end = __dtb_rcar_du_of_##type##_##soc##_end, \ + } + +static int __init rcar_du_of_apply_overlay(const struct rcar_du_of_overlay *dtbs, + const char *compatible) +{ + const struct rcar_du_of_overlay *dtb = NULL; + unsigned int i; + int ovcs_id; + + for (i = 0; dtbs[i].compatible; ++i) { + if (!strcmp(dtbs[i].compatible, compatible)) { + dtb = &dtbs[i]; + break; + } + } + + if (!dtb) + return -ENODEV; + + ovcs_id = 0; + return of_overlay_fdt_apply(dtb->begin, dtb->end - dtb->begin, + &ovcs_id); +} + +static int __init rcar_du_of_add_property(struct of_changeset *ocs, + struct device_node *np, + const char *name, const void *value, + int length) +{ + struct property *prop; + int ret = -ENOMEM; + + prop = kzalloc(sizeof(*prop), GFP_KERNEL); + if (!prop) + return -ENOMEM; + + prop->name = kstrdup(name, GFP_KERNEL); + if (!prop->name) + goto out_err; + + prop->value = kmemdup(value, length, GFP_KERNEL); + if (!prop->value) + goto out_err; + + of_property_set_flag(prop, OF_DYNAMIC); + + prop->length = length; + + ret = of_changeset_add_property(ocs, np, prop); + if (!ret) + return 0; + +out_err: + kfree(prop->value); + kfree(prop->name); + kfree(prop); + return ret; +} + +/* ----------------------------------------------------------------------------- + * LVDS Overlays + */ + +RCAR_DU_OF_DTB(lvds, r8a7790); +RCAR_DU_OF_DTB(lvds, r8a7791); +RCAR_DU_OF_DTB(lvds, r8a7793); +RCAR_DU_OF_DTB(lvds, r8a7795); +RCAR_DU_OF_DTB(lvds, r8a7796); + +static const struct rcar_du_of_overlay rcar_du_lvds_overlays[] __initconst = { + RCAR_DU_OF_OVERLAY(lvds, r8a7790), + RCAR_DU_OF_OVERLAY(lvds, r8a7791), + RCAR_DU_OF_OVERLAY(lvds, r8a7793), + RCAR_DU_OF_OVERLAY(lvds, r8a7795), + RCAR_DU_OF_OVERLAY(lvds, r8a7796), + { /* Sentinel */ }, +}; + +static struct of_changeset rcar_du_lvds_changeset; + +static void __init rcar_du_of_lvds_patch_one(struct device_node *lvds, + const struct of_phandle_args *clk, + struct device_node *local, + struct device_node *remote) +{ + unsigned int psize; + unsigned int i; + __be32 value[4]; + int ret; + + /* + * Set the LVDS clocks property. This can't be performed by the overlay + * as the structure of the clock specifier has changed over time, and we + * don't know at compile time which binding version the system we will + * run on uses. + */ + if (clk->args_count >= ARRAY_SIZE(value) - 1) + return; + + of_changeset_init(&rcar_du_lvds_changeset); + + value[0] = cpu_to_be32(clk->np->phandle); + for (i = 0; i < clk->args_count; ++i) + value[i + 1] = cpu_to_be32(clk->args[i]); + + psize = (clk->args_count + 1) * 4; + ret = rcar_du_of_add_property(&rcar_du_lvds_changeset, lvds, + "clocks", value, psize); + if (ret < 0) + goto done; + + /* + * Insert the node in the OF graph: patch the LVDS ports remote-endpoint + * properties to point to the endpoints of the sibling nodes in the + * graph. This can't be performed by the overlay: on the input side the + * overlay would contain a phandle for the DU LVDS output port that + * would clash with the system DT, and on the output side the connection + * is board-specific. + */ + value[0] = cpu_to_be32(local->phandle); + value[1] = cpu_to_be32(remote->phandle); + + for (i = 0; i < 2; ++i) { + struct device_node *endpoint; + + endpoint = of_graph_get_endpoint_by_regs(lvds, i, 0); + if (!endpoint) { + ret = -EINVAL; + goto done; + } + + ret = rcar_du_of_add_property(&rcar_du_lvds_changeset, + endpoint, "remote-endpoint", + &value[i], sizeof(value[i])); + of_node_put(endpoint); + if (ret < 0) + goto done; + } + + ret = of_changeset_apply(&rcar_du_lvds_changeset); + +done: + if (ret < 0) + of_changeset_destroy(&rcar_du_lvds_changeset); +} + +struct lvds_of_data { + struct resource res; + struct of_phandle_args clkspec; + struct device_node *local; + struct device_node *remote; +}; + +static void __init rcar_du_of_lvds_patch(const struct of_device_id *of_ids) +{ + const struct rcar_du_device_info *info; + const struct of_device_id *match; + struct lvds_of_data lvds_data[2] = { }; + struct device_node *lvds_node; + struct device_node *soc_node; + struct device_node *du_node; + char compatible[22]; + const char *soc_name; + unsigned int i; + int ret; + + /* Get the DU node and exit if not present or disabled. */ + du_node = of_find_matching_node_and_match(NULL, of_ids, &match); + if (!du_node || !of_device_is_available(du_node)) { + of_node_put(du_node); + return; + } + + info = match->data; + soc_node = of_get_parent(du_node); + + if (WARN_ON(info->num_lvds > ARRAY_SIZE(lvds_data))) + goto done; + + /* + * Skip if the LVDS nodes already exists. + * + * The nodes are searched based on the compatible string, which we + * construct from the SoC name found in the DU compatible string. As a + * match has been found we know the compatible string matches the + * expected format and can thus skip some of the string manipulation + * normal safety checks. + */ + soc_name = strchr(match->compatible, '-') + 1; + sprintf(compatible, "renesas,%s-lvds", soc_name); + lvds_node = of_find_compatible_node(NULL, NULL, compatible); + if (lvds_node) { + of_node_put(lvds_node); + return; + } + + /* + * Parse the DU node and store the register specifier, the clock + * specifier and the local and remote endpoint of the LVDS link for + * later use. + */ + for (i = 0; i < info->num_lvds; ++i) { + struct lvds_of_data *lvds = &lvds_data[i]; + unsigned int port; + char name[7]; + int index; + + sprintf(name, "lvds.%u", i); + index = of_property_match_string(du_node, "clock-names", name); + if (index < 0) + continue; + + ret = of_parse_phandle_with_args(du_node, "clocks", + "#clock-cells", index, + &lvds->clkspec); + if (ret < 0) + continue; + + port = info->routes[RCAR_DU_OUTPUT_LVDS0 + i].port; + + lvds->local = of_graph_get_endpoint_by_regs(du_node, port, 0); + if (!lvds->local) + continue; + + lvds->remote = of_graph_get_remote_endpoint(lvds->local); + if (!lvds->remote) + continue; + + index = of_property_match_string(du_node, "reg-names", name); + if (index < 0) + continue; + + of_address_to_resource(du_node, index, &lvds->res); + } + + /* Parse and apply the overlay. This will resolve phandles. */ + ret = rcar_du_of_apply_overlay(rcar_du_lvds_overlays, + match->compatible); + if (ret < 0) + goto done; + + /* Patch the newly created LVDS encoder nodes. */ + for_each_child_of_node(soc_node, lvds_node) { + struct resource res; + + if (!of_device_is_compatible(lvds_node, compatible)) + continue; + + /* Locate the lvds_data entry based on the resource start. */ + ret = of_address_to_resource(lvds_node, 0, &res); + if (ret < 0) + continue; + + for (i = 0; i < ARRAY_SIZE(lvds_data); ++i) { + if (lvds_data[i].res.start == res.start) + break; + } + + if (i == ARRAY_SIZE(lvds_data)) + continue; + + /* Patch the LVDS encoder. */ + rcar_du_of_lvds_patch_one(lvds_node, &lvds_data[i].clkspec, + lvds_data[i].local, + lvds_data[i].remote); + } + +done: + for (i = 0; i < info->num_lvds; ++i) { + of_node_put(lvds_data[i].clkspec.np); + of_node_put(lvds_data[i].local); + of_node_put(lvds_data[i].remote); + } + + of_node_put(soc_node); + of_node_put(du_node); +} + +void __init rcar_du_of_init(const struct of_device_id *of_ids) +{ + rcar_du_of_lvds_patch(of_ids); +} diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_of.h b/drivers/gpu/drm/renesas/rcar-du/rcar_du_of.h new file mode 100644 index 000000000000..8dd3fbe96650 --- /dev/null +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_of.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * rcar_du_of.h - Legacy DT bindings compatibility + * + * Copyright (C) 2018 Laurent Pinchart + */ +#ifndef __RCAR_DU_OF_H__ +#define __RCAR_DU_OF_H__ + +#include + +struct of_device_id; + +#if IS_ENABLED(CONFIG_DRM_RCAR_LVDS) +void __init rcar_du_of_init(const struct of_device_id *of_ids); +#else +static inline void rcar_du_of_init(const struct of_device_id *of_ids) { } +#endif /* CONFIG_DRM_RCAR_LVDS */ + +#endif /* __RCAR_DU_OF_H__ */ diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7790.dts b/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7790.dts new file mode 100644 index 000000000000..8bee4e787a0a --- /dev/null +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7790.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * rcar_du_of_lvds_r8a7790.dts - Legacy LVDS DT bindings conversion for R8A7790 + * + * Copyright (C) 2018 Laurent Pinchart + */ + +/dts-v1/; +/plugin/; + +&{/} { + #address-cells = <2>; + #size-cells = <2>; + + lvds@feb90000 { + compatible = "renesas,r8a7790-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_input: endpoint { + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + lvds@feb94000 { + compatible = "renesas,r8a7790-lvds"; + reg = <0 0xfeb94000 0 0x1c>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds1_input: endpoint { + }; + }; + port@1 { + reg = <1>; + lvds1_out: endpoint { + }; + }; + }; + }; +}; + +&{/display@feb00000/ports} { + port@1 { + endpoint { + remote-endpoint = <&lvds0_input>; + }; + }; + port@2 { + endpoint { + remote-endpoint = <&lvds1_input>; + }; + }; +}; diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7791.dts b/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7791.dts new file mode 100644 index 000000000000..92c0509971ec --- /dev/null +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7791.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * rcar_du_of_lvds_r8a7791.dts - Legacy LVDS DT bindings conversion for R8A7791 + * + * Copyright (C) 2018 Laurent Pinchart + */ + +/dts-v1/; +/plugin/; + +&{/} { + #address-cells = <2>; + #size-cells = <2>; + + lvds@feb90000 { + compatible = "renesas,r8a7791-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_input: endpoint { + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; +}; + +&{/display@feb00000/ports} { + port@1 { + endpoint { + remote-endpoint = <&lvds0_input>; + }; + }; +}; diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7793.dts b/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7793.dts new file mode 100644 index 000000000000..c8b93f21de0f --- /dev/null +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7793.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * rcar_du_of_lvds_r8a7793.dts - Legacy LVDS DT bindings conversion for R8A7793 + * + * Copyright (C) 2018 Laurent Pinchart + */ + +/dts-v1/; +/plugin/; + +&{/} { + #address-cells = <2>; + #size-cells = <2>; + + lvds@feb90000 { + compatible = "renesas,r8a7793-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_input: endpoint { + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; +}; + +&{/display@feb00000/ports} { + port@1 { + endpoint { + remote-endpoint = <&lvds0_input>; + }; + }; +}; diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7795.dts b/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7795.dts new file mode 100644 index 000000000000..16c2d03cb016 --- /dev/null +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7795.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * rcar_du_of_lvds_r8a7795.dts - Legacy LVDS DT bindings conversion for R8A7795 + * + * Copyright (C) 2018 Laurent Pinchart + */ + +/dts-v1/; +/plugin/; + +&{/soc} { + #address-cells = <2>; + #size-cells = <2>; + + lvds@feb90000 { + compatible = "renesas,r8a7795-lvds"; + reg = <0 0xfeb90000 0 0x14>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_input: endpoint { + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; +}; + +&{/soc/display@feb00000/ports} { + port@3 { + endpoint { + remote-endpoint = <&lvds0_input>; + }; + }; +}; diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7796.dts b/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7796.dts new file mode 100644 index 000000000000..680e923ac036 --- /dev/null +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_of_lvds_r8a7796.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * rcar_du_of_lvds_r8a7796.dts - Legacy LVDS DT bindings conversion for R8A7796 + * + * Copyright (C) 2018 Laurent Pinchart + */ + +/dts-v1/; +/plugin/; + +&{/soc} { + #address-cells = <2>; + #size-cells = <2>; + + lvds@feb90000 { + compatible = "renesas,r8a7796-lvds"; + reg = <0 0xfeb90000 0 0x14>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_input: endpoint { + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; +}; + +&{/soc/display@feb00000/ports} { + port@3 { + endpoint { + remote-endpoint = <&lvds0_input>; + }; + }; +}; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.c similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_plane.c rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.c diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.h b/drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.h similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_plane.h rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.h diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_du_regs.h similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_regs.h rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_regs.h diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_vsp.c similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_vsp.c rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_vsp.c diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h b/drivers/gpu/drm/renesas/rcar-du/rcar_du_vsp.h similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_vsp.h rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_vsp.h diff --git a/drivers/gpu/drm/rcar-du/rcar_du_writeback.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_writeback.c similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_writeback.c rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_writeback.c diff --git a/drivers/gpu/drm/rcar-du/rcar_du_writeback.h b/drivers/gpu/drm/renesas/rcar-du/rcar_du_writeback.h similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_du_writeback.h rename to drivers/gpu/drm/renesas/rcar-du/rcar_du_writeback.h diff --git a/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c rename to drivers/gpu/drm/renesas/rcar-du/rcar_dw_hdmi.c diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_lvds.c rename to drivers/gpu/drm/renesas/rcar-du/rcar_lvds.c diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.h b/drivers/gpu/drm/renesas/rcar-du/rcar_lvds.h similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_lvds.h rename to drivers/gpu/drm/renesas/rcar-du/rcar_lvds.h diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_lvds_regs.h similarity index 100% rename from drivers/gpu/drm/rcar-du/rcar_lvds_regs.h rename to drivers/gpu/drm/renesas/rcar-du/rcar_lvds_regs.h diff --git a/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rcar-du/rzg2l_mipi_dsi.c similarity index 100% rename from drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c rename to drivers/gpu/drm/renesas/rcar-du/rzg2l_mipi_dsi.c diff --git a/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rzg2l_mipi_dsi_regs.h similarity index 100% rename from drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h rename to drivers/gpu/drm/renesas/rcar-du/rzg2l_mipi_dsi_regs.h diff --git a/drivers/gpu/drm/shmobile/Kconfig b/drivers/gpu/drm/renesas/shmobile/Kconfig similarity index 100% rename from drivers/gpu/drm/shmobile/Kconfig rename to drivers/gpu/drm/renesas/shmobile/Kconfig diff --git a/drivers/gpu/drm/shmobile/Makefile b/drivers/gpu/drm/renesas/shmobile/Makefile similarity index 100% rename from drivers/gpu/drm/shmobile/Makefile rename to drivers/gpu/drm/renesas/shmobile/Makefile diff --git a/drivers/gpu/drm/shmobile/shmob_drm_backlight.c b/drivers/gpu/drm/renesas/shmobile/shmob_drm_backlight.c similarity index 100% rename from drivers/gpu/drm/shmobile/shmob_drm_backlight.c rename to drivers/gpu/drm/renesas/shmobile/shmob_drm_backlight.c diff --git a/drivers/gpu/drm/shmobile/shmob_drm_backlight.h b/drivers/gpu/drm/renesas/shmobile/shmob_drm_backlight.h similarity index 100% rename from drivers/gpu/drm/shmobile/shmob_drm_backlight.h rename to drivers/gpu/drm/renesas/shmobile/shmob_drm_backlight.h diff --git a/drivers/gpu/drm/shmobile/shmob_drm_crtc.c b/drivers/gpu/drm/renesas/shmobile/shmob_drm_crtc.c similarity index 100% rename from drivers/gpu/drm/shmobile/shmob_drm_crtc.c rename to drivers/gpu/drm/renesas/shmobile/shmob_drm_crtc.c diff --git a/drivers/gpu/drm/shmobile/shmob_drm_crtc.h b/drivers/gpu/drm/renesas/shmobile/shmob_drm_crtc.h similarity index 100% rename from drivers/gpu/drm/shmobile/shmob_drm_crtc.h rename to drivers/gpu/drm/renesas/shmobile/shmob_drm_crtc.h diff --git a/drivers/gpu/drm/shmobile/shmob_drm_drv.c b/drivers/gpu/drm/renesas/shmobile/shmob_drm_drv.c similarity index 100% rename from drivers/gpu/drm/shmobile/shmob_drm_drv.c rename to drivers/gpu/drm/renesas/shmobile/shmob_drm_drv.c diff --git a/drivers/gpu/drm/shmobile/shmob_drm_drv.h b/drivers/gpu/drm/renesas/shmobile/shmob_drm_drv.h similarity index 100% rename from drivers/gpu/drm/shmobile/shmob_drm_drv.h rename to drivers/gpu/drm/renesas/shmobile/shmob_drm_drv.h diff --git a/drivers/gpu/drm/shmobile/shmob_drm_kms.c b/drivers/gpu/drm/renesas/shmobile/shmob_drm_kms.c similarity index 100% rename from drivers/gpu/drm/shmobile/shmob_drm_kms.c rename to drivers/gpu/drm/renesas/shmobile/shmob_drm_kms.c diff --git a/drivers/gpu/drm/shmobile/shmob_drm_kms.h b/drivers/gpu/drm/renesas/shmobile/shmob_drm_kms.h similarity index 100% rename from drivers/gpu/drm/shmobile/shmob_drm_kms.h rename to drivers/gpu/drm/renesas/shmobile/shmob_drm_kms.h diff --git a/drivers/gpu/drm/shmobile/shmob_drm_plane.c b/drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c similarity index 100% rename from drivers/gpu/drm/shmobile/shmob_drm_plane.c rename to drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c diff --git a/drivers/gpu/drm/shmobile/shmob_drm_plane.h b/drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.h similarity index 100% rename from drivers/gpu/drm/shmobile/shmob_drm_plane.h rename to drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.h diff --git a/drivers/gpu/drm/shmobile/shmob_drm_regs.h b/drivers/gpu/drm/renesas/shmobile/shmob_drm_regs.h similarity index 100% rename from drivers/gpu/drm/shmobile/shmob_drm_regs.h rename to drivers/gpu/drm/renesas/shmobile/shmob_drm_regs.h From patchwork Fri Jun 14 10:12:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13698507 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E37F2C27C6E for ; Fri, 14 Jun 2024 10:13:27 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web10.8046.1718359999186778486 for ; Fri, 14 Jun 2024 03:13:19 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.08,237,1712588400"; d="scan'208";a="211895877" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Jun 2024 19:13:18 +0900 Received: from localhost.localdomain (unknown [10.226.92.95]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 90D22428BB19; Fri, 14 Jun 2024 19:13:16 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 5.10.y-cip 02/14] drm: Allow const struct drm_driver Date: Fri, 14 Jun 2024 11:12:56 +0100 Message-Id: <20240614101308.40407-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> References: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 14 Jun 2024 10:13:27 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16235 From: Daniel Vetter commit 8f5c7aa078cf6f81ef5afc3f0516b4049decb4eb upstream. It's nice if a big function/ioctl table like this is const. Only downside here is that we need a few more #ifdef to paper over the differences when CONFIG_DRM_LEGACY is enabled. Maybe provides more motivation to sunset that horror show :-) v2: - Fix super important checkpatch warning (Sam) - Update the kerneldoc example too (Sam) Acked-by: Maxime Ripard Reviewed-by: Sam Ravnborg Acked-by: Thomas Zimmermann Reviewed-by: Alex Deucher Signed-off-by: Daniel Vetter Cc: Sam Ravnborg Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Thomas Zimmermann Cc: David Airlie Cc: Daniel Vetter Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20201104100425.1922351-4-daniel.vetter@ffwll.ch Signed-off-by: Biju Das --- drivers/gpu/drm/drm_drv.c | 17 +++++++++++------ include/drm/drm_device.h | 4 ++++ include/drm/drm_drv.h | 5 +++-- 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index 10831d8d7148..b1313d8d96c9 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -284,7 +284,7 @@ void drm_minor_release(struct drm_minor *minor) * struct clk *pclk; * }; * - * static struct drm_driver driver_drm_driver = { + * static const struct drm_driver driver_drm_driver = { * [...] * }; * @@ -574,7 +574,7 @@ static void drm_dev_init_release(struct drm_device *dev, void *res) } static int drm_dev_init(struct drm_device *dev, - struct drm_driver *driver, + const struct drm_driver *driver, struct device *parent) { struct inode *inode; @@ -590,7 +590,11 @@ static int drm_dev_init(struct drm_device *dev, kref_init(&dev->ref); dev->dev = get_device(parent); +#ifdef CONFIG_DRM_LEGACY + dev->driver = (struct drm_driver *)driver; +#else dev->driver = driver; +#endif INIT_LIST_HEAD(&dev->managed.resources); spin_lock_init(&dev->managed.lock); @@ -666,7 +670,7 @@ static void devm_drm_dev_init_release(void *data) static int devm_drm_dev_init(struct device *parent, struct drm_device *dev, - struct drm_driver *driver) + const struct drm_driver *driver) { int ret; @@ -681,7 +685,8 @@ static int devm_drm_dev_init(struct device *parent, return ret; } -void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, +void *__devm_drm_dev_alloc(struct device *parent, + const struct drm_driver *driver, size_t size, size_t offset) { void *container; @@ -716,7 +721,7 @@ EXPORT_SYMBOL(__devm_drm_dev_alloc); * RETURNS: * Pointer to new DRM device, or ERR_PTR on failure. */ -struct drm_device *drm_dev_alloc(struct drm_driver *driver, +struct drm_device *drm_dev_alloc(const struct drm_driver *driver, struct device *parent) { struct drm_device *dev; @@ -861,7 +866,7 @@ static void remove_compat_control_link(struct drm_device *dev) */ int drm_dev_register(struct drm_device *dev, unsigned long flags) { - struct drm_driver *driver = dev->driver; + const struct drm_driver *driver = dev->driver; int ret; if (!driver->load) diff --git a/include/drm/drm_device.h b/include/drm/drm_device.h index f4f68e7a9149..2c361964aee7 100644 --- a/include/drm/drm_device.h +++ b/include/drm/drm_device.h @@ -83,7 +83,11 @@ struct drm_device { } managed; /** @driver: DRM driver managing the device */ +#ifdef CONFIG_DRM_LEGACY struct drm_driver *driver; +#else + const struct drm_driver *driver; +#endif /** * @dev_private: diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h index e57d0440f00f..8324b65b4dae 100644 --- a/include/drm/drm_drv.h +++ b/include/drm/drm_drv.h @@ -588,7 +588,8 @@ struct drm_driver { int dev_priv_size; }; -void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, +void *__devm_drm_dev_alloc(struct device *parent, + const struct drm_driver *driver, size_t size, size_t offset); /** @@ -621,7 +622,7 @@ void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, ((type *) __devm_drm_dev_alloc(parent, driver, sizeof(type), \ offsetof(type, member))) -struct drm_device *drm_dev_alloc(struct drm_driver *driver, +struct drm_device *drm_dev_alloc(const struct drm_driver *driver, struct device *parent); int drm_dev_register(struct drm_device *dev, unsigned long flags); void drm_dev_unregister(struct drm_device *dev); From patchwork Fri Jun 14 10:12:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13698506 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3822C41513 for ; Fri, 14 Jun 2024 10:13:27 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.8276.1718359994763562701 for ; Fri, 14 Jun 2024 03:13:21 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.08,237,1712588400"; d="scan'208";a="207938159" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 14 Jun 2024 19:13:20 +0900 Received: from localhost.localdomain (unknown [10.226.92.95]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id EF801428BB21; Fri, 14 Jun 2024 19:13:18 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 5.10.y-cip 03/14] drm: add drmm_encoder_alloc() Date: Fri, 14 Jun 2024 11:12:57 +0100 Message-Id: <20240614101308.40407-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> References: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 14 Jun 2024 10:13:27 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16236 From: Philipp Zabel commit ca5092d04d86986c03b6e0042e2f1cd119c50f5d upstream. Add an alternative to drm_encoder_init() that allocates and initializes an encoder and registers drm_encoder_cleanup() with drmm_add_action_or_reset(). Signed-off-by: Philipp Zabel Reviewed-by: Laurent Pinchart Reviewed-by: Daniel Vetter Signed-off-by: Biju Das --- drivers/gpu/drm/drm_encoder.c | 109 +++++++++++++++++++++++++++------- include/drm/drm_encoder.h | 30 ++++++++++ 2 files changed, 116 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/drm_encoder.c b/drivers/gpu/drm/drm_encoder.c index e555281f43d4..24ac9a2350ea 100644 --- a/drivers/gpu/drm/drm_encoder.c +++ b/drivers/gpu/drm/drm_encoder.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "drm_crtc_internal.h" @@ -91,25 +92,11 @@ void drm_encoder_unregister_all(struct drm_device *dev) } } -/** - * drm_encoder_init - Init a preallocated encoder - * @dev: drm device - * @encoder: the encoder to init - * @funcs: callbacks for this encoder - * @encoder_type: user visible type of the encoder - * @name: printf style format string for the encoder name, or NULL for default name - * - * Initialises a preallocated encoder. Encoder should be subclassed as part of - * driver encoder objects. At driver unload time drm_encoder_cleanup() should be - * called from the driver's &drm_encoder_funcs.destroy hook. - * - * Returns: - * Zero on success, error code on failure. - */ -int drm_encoder_init(struct drm_device *dev, - struct drm_encoder *encoder, - const struct drm_encoder_funcs *funcs, - int encoder_type, const char *name, ...) +__printf(5, 0) +static int __drm_encoder_init(struct drm_device *dev, + struct drm_encoder *encoder, + const struct drm_encoder_funcs *funcs, + int encoder_type, const char *name, va_list ap) { int ret; @@ -125,11 +112,7 @@ int drm_encoder_init(struct drm_device *dev, encoder->encoder_type = encoder_type; encoder->funcs = funcs; if (name) { - va_list ap; - - va_start(ap, name); encoder->name = kvasprintf(GFP_KERNEL, name, ap); - va_end(ap); } else { encoder->name = kasprintf(GFP_KERNEL, "%s-%d", drm_encoder_enum_list[encoder_type].name, @@ -150,6 +133,44 @@ int drm_encoder_init(struct drm_device *dev, return ret; } + +/** + * drm_encoder_init - Init a preallocated encoder + * @dev: drm device + * @encoder: the encoder to init + * @funcs: callbacks for this encoder + * @encoder_type: user visible type of the encoder + * @name: printf style format string for the encoder name, or NULL for default name + * + * Initializes a preallocated encoder. Encoder should be subclassed as part of + * driver encoder objects. At driver unload time the driver's + * &drm_encoder_funcs.destroy hook should call drm_encoder_cleanup() and kfree() + * the encoder structure. The encoder structure should not be allocated with + * devm_kzalloc(). + * + * Note: consider using drmm_encoder_alloc() instead of drm_encoder_init() to + * let the DRM managed resource infrastructure take care of cleanup and + * deallocation. + * + * Returns: + * Zero on success, error code on failure. + */ +int drm_encoder_init(struct drm_device *dev, + struct drm_encoder *encoder, + const struct drm_encoder_funcs *funcs, + int encoder_type, const char *name, ...) +{ + va_list ap; + int ret; + + WARN_ON(!funcs->destroy); + + va_start(ap, name); + ret = __drm_encoder_init(dev, encoder, funcs, encoder_type, name, ap); + va_end(ap); + + return ret; +} EXPORT_SYMBOL(drm_encoder_init); /** @@ -181,6 +202,48 @@ void drm_encoder_cleanup(struct drm_encoder *encoder) } EXPORT_SYMBOL(drm_encoder_cleanup); +static void drmm_encoder_alloc_release(struct drm_device *dev, void *ptr) +{ + struct drm_encoder *encoder = ptr; + + if (WARN_ON(!encoder->dev)) + return; + + drm_encoder_cleanup(encoder); +} + +void *__drmm_encoder_alloc(struct drm_device *dev, size_t size, size_t offset, + const struct drm_encoder_funcs *funcs, + int encoder_type, const char *name, ...) +{ + void *container; + struct drm_encoder *encoder; + va_list ap; + int ret; + + if (WARN_ON(funcs && funcs->destroy)) + return ERR_PTR(-EINVAL); + + container = drmm_kzalloc(dev, size, GFP_KERNEL); + if (!container) + return ERR_PTR(-EINVAL); + + encoder = container + offset; + + va_start(ap, name); + ret = __drm_encoder_init(dev, encoder, funcs, encoder_type, name, ap); + va_end(ap); + if (ret) + return ERR_PTR(ret); + + ret = drmm_add_action_or_reset(dev, drmm_encoder_alloc_release, encoder); + if (ret) + return ERR_PTR(ret); + + return container; +} +EXPORT_SYMBOL(__drmm_encoder_alloc); + static struct drm_crtc *drm_encoder_get_crtc(struct drm_encoder *encoder) { struct drm_connector *connector; diff --git a/include/drm/drm_encoder.h b/include/drm/drm_encoder.h index a60f5f1555ac..8e1316caba28 100644 --- a/include/drm/drm_encoder.h +++ b/include/drm/drm_encoder.h @@ -195,6 +195,36 @@ int drm_encoder_init(struct drm_device *dev, const struct drm_encoder_funcs *funcs, int encoder_type, const char *name, ...); +__printf(6, 7) +void *__drmm_encoder_alloc(struct drm_device *dev, + size_t size, size_t offset, + const struct drm_encoder_funcs *funcs, + int encoder_type, + const char *name, ...); + +/** + * drmm_encoder_alloc - Allocate and initialize an encoder + * @dev: drm device + * @type: the type of the struct which contains struct &drm_encoder + * @member: the name of the &drm_encoder within @type + * @funcs: callbacks for this encoder (optional) + * @encoder_type: user visible type of the encoder + * @name: printf style format string for the encoder name, or NULL for default name + * + * Allocates and initializes an encoder. Encoder should be subclassed as part of + * driver encoder objects. Cleanup is automatically handled through registering + * drm_encoder_cleanup() with drmm_add_action(). + * + * The @drm_encoder_funcs.destroy hook must be NULL. + * + * Returns: + * Pointer to new encoder, or ERR_PTR on failure. + */ +#define drmm_encoder_alloc(dev, type, member, funcs, encoder_type, name, ...) \ + ((type *)__drmm_encoder_alloc(dev, sizeof(type), \ + offsetof(type, member), funcs, \ + encoder_type, name, ##__VA_ARGS__)) + /** * drm_encoder_index - find the index of a registered encoder * @encoder: encoder to find index for From patchwork Fri Jun 14 10:12:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13698509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F10DEC27C79 for ; Fri, 14 Jun 2024 10:13:27 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.8276.1718359994763562701 for ; Fri, 14 Jun 2024 03:13:23 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.08,237,1712588400"; d="scan'208";a="207938166" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 14 Jun 2024 19:13:23 +0900 Received: from localhost.localdomain (unknown [10.226.92.95]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 571FA428BB21; Fri, 14 Jun 2024 19:13:21 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 5.10.y-cip 04/14] drm/plane: add drmm_universal_plane_alloc() Date: Fri, 14 Jun 2024 11:12:58 +0100 Message-Id: <20240614101308.40407-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> References: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 14 Jun 2024 10:13:27 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16237 From: Philipp Zabel commit 0a1b813f06f1009d1d44d48888e92e3a59ea0be3 upstream. Add an alternative to drm_universal_plane_init() that allocates and initializes a plane and registers drm_plane_cleanup() with drmm_add_action_or_reset(). Signed-off-by: Philipp Zabel Reviewed-by: Laurent Pinchart Reviewed-by: Daniel Vetter Signed-off-by: Biju Das --- drivers/gpu/drm/drm_plane.c | 134 ++++++++++++++++++++++++++++-------- include/drm/drm_plane.h | 42 +++++++++++ 2 files changed, 147 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index 79249568bdec..27456ba2443c 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include "drm_crtc_internal.h" @@ -152,31 +153,16 @@ static int create_in_format_blob(struct drm_device *dev, struct drm_plane *plane return 0; } -/** - * drm_universal_plane_init - Initialize a new universal plane object - * @dev: DRM device - * @plane: plane object to init - * @possible_crtcs: bitmask of possible CRTCs - * @funcs: callbacks for the new plane - * @formats: array of supported formats (DRM_FORMAT\_\*) - * @format_count: number of elements in @formats - * @format_modifiers: array of struct drm_format modifiers terminated by - * DRM_FORMAT_MOD_INVALID - * @type: type of plane (overlay, primary, cursor) - * @name: printf style format string for the plane name, or NULL for default name - * - * Initializes a plane object of type @type. - * - * Returns: - * Zero on success, error code on failure. - */ -int drm_universal_plane_init(struct drm_device *dev, struct drm_plane *plane, - uint32_t possible_crtcs, - const struct drm_plane_funcs *funcs, - const uint32_t *formats, unsigned int format_count, - const uint64_t *format_modifiers, - enum drm_plane_type type, - const char *name, ...) +__printf(9, 0) +static int __drm_universal_plane_init(struct drm_device *dev, + struct drm_plane *plane, + uint32_t possible_crtcs, + const struct drm_plane_funcs *funcs, + const uint32_t *formats, + unsigned int format_count, + const uint64_t *format_modifiers, + enum drm_plane_type type, + const char *name, va_list ap) { struct drm_mode_config *config = &dev->mode_config; unsigned int format_modifier_count = 0; @@ -237,11 +223,7 @@ int drm_universal_plane_init(struct drm_device *dev, struct drm_plane *plane, } if (name) { - va_list ap; - - va_start(ap, name); plane->name = kvasprintf(GFP_KERNEL, name, ap); - va_end(ap); } else { plane->name = kasprintf(GFP_KERNEL, "plane-%d", drm_num_planes(dev)); @@ -286,8 +268,102 @@ int drm_universal_plane_init(struct drm_device *dev, struct drm_plane *plane, return 0; } + +/** + * drm_universal_plane_init - Initialize a new universal plane object + * @dev: DRM device + * @plane: plane object to init + * @possible_crtcs: bitmask of possible CRTCs + * @funcs: callbacks for the new plane + * @formats: array of supported formats (DRM_FORMAT\_\*) + * @format_count: number of elements in @formats + * @format_modifiers: array of struct drm_format modifiers terminated by + * DRM_FORMAT_MOD_INVALID + * @type: type of plane (overlay, primary, cursor) + * @name: printf style format string for the plane name, or NULL for default name + * + * Initializes a plane object of type @type. The &drm_plane_funcs.destroy hook + * should call drm_plane_cleanup() and kfree() the plane structure. The plane + * structure should not be allocated with devm_kzalloc(). + * + * Note: consider using drmm_universal_plane_alloc() instead of + * drm_universal_plane_init() to let the DRM managed resource infrastructure + * take care of cleanup and deallocation. + * + * Returns: + * Zero on success, error code on failure. + */ +int drm_universal_plane_init(struct drm_device *dev, struct drm_plane *plane, + uint32_t possible_crtcs, + const struct drm_plane_funcs *funcs, + const uint32_t *formats, unsigned int format_count, + const uint64_t *format_modifiers, + enum drm_plane_type type, + const char *name, ...) +{ + va_list ap; + int ret; + + WARN_ON(!funcs->destroy); + + va_start(ap, name); + ret = __drm_universal_plane_init(dev, plane, possible_crtcs, funcs, + formats, format_count, format_modifiers, + type, name, ap); + va_end(ap); + return ret; +} EXPORT_SYMBOL(drm_universal_plane_init); +static void drmm_universal_plane_alloc_release(struct drm_device *dev, void *ptr) +{ + struct drm_plane *plane = ptr; + + if (WARN_ON(!plane->dev)) + return; + + drm_plane_cleanup(plane); +} + +void *__drmm_universal_plane_alloc(struct drm_device *dev, size_t size, + size_t offset, uint32_t possible_crtcs, + const struct drm_plane_funcs *funcs, + const uint32_t *formats, unsigned int format_count, + const uint64_t *format_modifiers, + enum drm_plane_type type, + const char *name, ...) +{ + void *container; + struct drm_plane *plane; + va_list ap; + int ret; + + if (WARN_ON(!funcs || funcs->destroy)) + return ERR_PTR(-EINVAL); + + container = drmm_kzalloc(dev, size, GFP_KERNEL); + if (!container) + return ERR_PTR(-ENOMEM); + + plane = container + offset; + + va_start(ap, name); + ret = __drm_universal_plane_init(dev, plane, possible_crtcs, funcs, + formats, format_count, format_modifiers, + type, name, ap); + va_end(ap); + if (ret) + return ERR_PTR(ret); + + ret = drmm_add_action_or_reset(dev, drmm_universal_plane_alloc_release, + plane); + if (ret) + return ERR_PTR(ret); + + return container; +} +EXPORT_SYMBOL(__drmm_universal_plane_alloc); + int drm_plane_register_all(struct drm_device *dev) { unsigned int num_planes = 0; diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 3f396d94afe4..82bd63710a39 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -746,6 +746,48 @@ int drm_plane_init(struct drm_device *dev, bool is_primary); void drm_plane_cleanup(struct drm_plane *plane); +__printf(10, 11) +void *__drmm_universal_plane_alloc(struct drm_device *dev, + size_t size, size_t offset, + uint32_t possible_crtcs, + const struct drm_plane_funcs *funcs, + const uint32_t *formats, + unsigned int format_count, + const uint64_t *format_modifiers, + enum drm_plane_type plane_type, + const char *name, ...); + +/** + * drmm_universal_plane_alloc - Allocate and initialize an universal plane object + * @dev: DRM device + * @type: the type of the struct which contains struct &drm_plane + * @member: the name of the &drm_plane within @type + * @possible_crtcs: bitmask of possible CRTCs + * @funcs: callbacks for the new plane + * @formats: array of supported formats (DRM_FORMAT\_\*) + * @format_count: number of elements in @formats + * @format_modifiers: array of struct drm_format modifiers terminated by + * DRM_FORMAT_MOD_INVALID + * @plane_type: type of plane (overlay, primary, cursor) + * @name: printf style format string for the plane name, or NULL for default name + * + * Allocates and initializes a plane object of type @type. Cleanup is + * automatically handled through registering drm_plane_cleanup() with + * drmm_add_action(). + * + * The @drm_plane_funcs.destroy hook must be NULL. + * + * Returns: + * Pointer to new plane, or ERR_PTR on failure. + */ +#define drmm_universal_plane_alloc(dev, type, member, possible_crtcs, funcs, formats, \ + format_count, format_modifiers, plane_type, name, ...) \ + ((type *)__drmm_universal_plane_alloc(dev, sizeof(type), \ + offsetof(type, member), \ + possible_crtcs, funcs, formats, \ + format_count, format_modifiers, \ + plane_type, name, ##__VA_ARGS__)) + /** * drm_plane_index - find the index of a registered plane * @plane: plane to find index for From patchwork Fri Jun 14 10:12:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13698508 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09E8CC27C75 for ; Fri, 14 Jun 2024 10:13:28 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.8281.1718360006029977314 for ; Fri, 14 Jun 2024 03:13:26 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.08,237,1712588400"; d="scan'208";a="211895898" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Jun 2024 19:13:25 +0900 Received: from localhost.localdomain (unknown [10.226.92.95]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id B22EF428BB21; Fri, 14 Jun 2024 19:13:23 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 5.10.y-cip 05/14] drm/crtc: add drmm_crtc_alloc_with_planes() Date: Fri, 14 Jun 2024 11:12:59 +0100 Message-Id: <20240614101308.40407-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> References: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 14 Jun 2024 10:13:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16238 From: Philipp Zabel commit 9dbb70fd663770418daab07590f4f534eb7a4931 upstream. Add an alternative to drm_crtc_init_with_planes() that allocates and initializes a crtc and registers drm_crtc_cleanup() with drmm_add_action_or_reset(). Signed-off-by: Philipp Zabel Reviewed-by: Laurent Pinchart Reviewed-by: Daniel Vetter Signed-off-by: Biju Das --- drivers/gpu/drm/drm_crtc.c | 125 ++++++++++++++++++++++++++++--------- include/drm/drm_crtc.h | 33 ++++++++++ 2 files changed, 130 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 4ed3fc28d4da..3d73f69ce044 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include #include @@ -231,30 +232,12 @@ struct dma_fence *drm_crtc_create_fence(struct drm_crtc *crtc) * Setting MODE_ID to 0 will release reserved resources for the CRTC. */ -/** - * drm_crtc_init_with_planes - Initialise a new CRTC object with - * specified primary and cursor planes. - * @dev: DRM device - * @crtc: CRTC object to init - * @primary: Primary plane for CRTC - * @cursor: Cursor plane for CRTC - * @funcs: callbacks for the new CRTC - * @name: printf style format string for the CRTC name, or NULL for default name - * - * Inits a new object created as base part of a driver crtc object. Drivers - * should use this function instead of drm_crtc_init(), which is only provided - * for backwards compatibility with drivers which do not yet support universal - * planes). For really simple hardware which has only 1 plane look at - * drm_simple_display_pipe_init() instead. - * - * Returns: - * Zero on success, error code on failure. - */ -int drm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc *crtc, - struct drm_plane *primary, - struct drm_plane *cursor, - const struct drm_crtc_funcs *funcs, - const char *name, ...) +__printf(6, 0) +static int __drm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc *crtc, + struct drm_plane *primary, + struct drm_plane *cursor, + const struct drm_crtc_funcs *funcs, + const char *name, va_list ap) { struct drm_mode_config *config = &dev->mode_config; int ret; @@ -282,11 +265,7 @@ int drm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc *crtc, return ret; if (name) { - va_list ap; - - va_start(ap, name); crtc->name = kvasprintf(GFP_KERNEL, name, ap); - va_end(ap); } else { crtc->name = kasprintf(GFP_KERNEL, "crtc-%d", drm_num_crtcs(dev)); @@ -330,8 +309,98 @@ int drm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc *crtc, return 0; } + +/** + * drm_crtc_init_with_planes - Initialise a new CRTC object with + * specified primary and cursor planes. + * @dev: DRM device + * @crtc: CRTC object to init + * @primary: Primary plane for CRTC + * @cursor: Cursor plane for CRTC + * @funcs: callbacks for the new CRTC + * @name: printf style format string for the CRTC name, or NULL for default name + * + * Inits a new object created as base part of a driver crtc object. Drivers + * should use this function instead of drm_crtc_init(), which is only provided + * for backwards compatibility with drivers which do not yet support universal + * planes). For really simple hardware which has only 1 plane look at + * drm_simple_display_pipe_init() instead. + * The &drm_crtc_funcs.destroy hook should call drm_crtc_cleanup() and kfree() + * the crtc structure. The crtc structure should not be allocated with + * devm_kzalloc(). + * + * Note: consider using drmm_crtc_alloc_with_planes() instead of + * drm_crtc_init_with_planes() to let the DRM managed resource infrastructure + * take care of cleanup and deallocation. + * + * Returns: + * Zero on success, error code on failure. + */ +int drm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc *crtc, + struct drm_plane *primary, + struct drm_plane *cursor, + const struct drm_crtc_funcs *funcs, + const char *name, ...) +{ + va_list ap; + int ret; + + WARN_ON(!funcs->destroy); + + va_start(ap, name); + ret = __drm_crtc_init_with_planes(dev, crtc, primary, cursor, funcs, + name, ap); + va_end(ap); + + return ret; +} EXPORT_SYMBOL(drm_crtc_init_with_planes); +static void drmm_crtc_alloc_with_planes_cleanup(struct drm_device *dev, + void *ptr) +{ + struct drm_crtc *crtc = ptr; + + drm_crtc_cleanup(crtc); +} + +void *__drmm_crtc_alloc_with_planes(struct drm_device *dev, + size_t size, size_t offset, + struct drm_plane *primary, + struct drm_plane *cursor, + const struct drm_crtc_funcs *funcs, + const char *name, ...) +{ + void *container; + struct drm_crtc *crtc; + va_list ap; + int ret; + + if (WARN_ON(!funcs || funcs->destroy)) + return ERR_PTR(-EINVAL); + + container = drmm_kzalloc(dev, size, GFP_KERNEL); + if (!container) + return ERR_PTR(-ENOMEM); + + crtc = container + offset; + + va_start(ap, name); + ret = __drm_crtc_init_with_planes(dev, crtc, primary, cursor, funcs, + name, ap); + va_end(ap); + if (ret) + return ERR_PTR(ret); + + ret = drmm_add_action_or_reset(dev, drmm_crtc_alloc_with_planes_cleanup, + crtc); + if (ret) + return ERR_PTR(ret); + + return container; +} +EXPORT_SYMBOL(__drmm_crtc_alloc_with_planes); + /** * drm_crtc_cleanup - Clean up the core crtc usage * @crtc: CRTC to cleanup diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 59b51a09cae6..b71c0a3d4126 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -1210,6 +1210,39 @@ int drm_crtc_init_with_planes(struct drm_device *dev, const char *name, ...); void drm_crtc_cleanup(struct drm_crtc *crtc); +__printf(7, 8) +void *__drmm_crtc_alloc_with_planes(struct drm_device *dev, + size_t size, size_t offset, + struct drm_plane *primary, + struct drm_plane *cursor, + const struct drm_crtc_funcs *funcs, + const char *name, ...); + +/** + * drm_crtc_alloc_with_planes - Allocate and initialize a new CRTC object with + * specified primary and cursor planes. + * @dev: DRM device + * @type: the type of the struct which contains struct &drm_crtc + * @member: the name of the &drm_crtc within @type. + * @primary: Primary plane for CRTC + * @cursor: Cursor plane for CRTC + * @funcs: callbacks for the new CRTC + * @name: printf style format string for the CRTC name, or NULL for default name + * + * Allocates and initializes a new crtc object. Cleanup is automatically + * handled through registering drmm_crtc_cleanup() with drmm_add_action(). + * + * The @drm_crtc_funcs.destroy hook must be NULL. + * + * Returns: + * Pointer to new crtc, or ERR_PTR on failure. + */ +#define drmm_crtc_alloc_with_planes(dev, type, member, primary, cursor, funcs, name, ...) \ + ((type *)__drmm_crtc_alloc_with_planes(dev, sizeof(type), \ + offsetof(type, member), \ + primary, cursor, funcs, \ + name, ##__VA_ARGS__)) + /** * drm_crtc_index - find the index of a registered CRTC * @crtc: CRTC to find index for From patchwork Fri Jun 14 10:13:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13698511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03F9EC27C6E for ; Fri, 14 Jun 2024 10:13:38 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.8281.1718360006029977314 for ; Fri, 14 Jun 2024 03:13:28 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.08,237,1712588400"; d="scan'208";a="211895901" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Jun 2024 19:13:27 +0900 Received: from localhost.localdomain (unknown [10.226.92.95]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 18CAC428BB26; Fri, 14 Jun 2024 19:13:25 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 5.10.y-cip 06/14] drm/crtc: Introduce drmm_crtc_init_with_planes Date: Fri, 14 Jun 2024 11:13:00 +0100 Message-Id: <20240614101308.40407-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> References: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 14 Jun 2024 10:13:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16239 From: Maxime Ripard commit 917dd05418148f05d8860b8106da8dcd1d258aaf upstream. The DRM-managed function to register a CRTC is drmm_crtc_alloc_with_planes(), which will allocate the underlying structure and initialisation the CRTC. However, we might want to separate the structure creation and the CRTC initialisation, for example if the structure is shared across multiple DRM entities, for example an encoder and a connector. Let's create an helper to only initialise a CRTC that would be passed as an argument. Acked-by: Thomas Zimmermann Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220711173939.1132294-3-maxime@cerno.tech Signed-off-by: Biju Das --- drivers/gpu/drm/drm_crtc.c | 97 +++++++++++++++++++++++++++++++++----- include/drm/drm_crtc.h | 9 ++++ 2 files changed, 94 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 3d73f69ce044..47d7fb514d01 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -329,9 +329,13 @@ static int __drm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc * * the crtc structure. The crtc structure should not be allocated with * devm_kzalloc(). * - * Note: consider using drmm_crtc_alloc_with_planes() instead of - * drm_crtc_init_with_planes() to let the DRM managed resource infrastructure - * take care of cleanup and deallocation. + * The @primary and @cursor planes are only relevant for legacy uAPI, see + * &drm_crtc.primary and &drm_crtc.cursor. + * + * Note: consider using drmm_crtc_alloc_with_planes() or + * drmm_crtc_init_with_planes() instead of drm_crtc_init_with_planes() + * to let the DRM managed resource infrastructure take care of cleanup + * and deallocation. * * Returns: * Zero on success, error code on failure. @@ -356,14 +360,88 @@ int drm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc *crtc, } EXPORT_SYMBOL(drm_crtc_init_with_planes); -static void drmm_crtc_alloc_with_planes_cleanup(struct drm_device *dev, - void *ptr) +static void drmm_crtc_init_with_planes_cleanup(struct drm_device *dev, + void *ptr) { struct drm_crtc *crtc = ptr; drm_crtc_cleanup(crtc); } +__printf(6, 0) +static int __drmm_crtc_init_with_planes(struct drm_device *dev, + struct drm_crtc *crtc, + struct drm_plane *primary, + struct drm_plane *cursor, + const struct drm_crtc_funcs *funcs, + const char *name, + va_list args) +{ + int ret; + + drm_WARN_ON(dev, funcs && funcs->destroy); + + ret = __drm_crtc_init_with_planes(dev, crtc, primary, cursor, funcs, + name, args); + if (ret) + return ret; + + ret = drmm_add_action_or_reset(dev, drmm_crtc_init_with_planes_cleanup, + crtc); + if (ret) + return ret; + + return 0; +} + +/** + * drmm_crtc_init_with_planes - Initialise a new CRTC object with + * specified primary and cursor planes. + * @dev: DRM device + * @crtc: CRTC object to init + * @primary: Primary plane for CRTC + * @cursor: Cursor plane for CRTC + * @funcs: callbacks for the new CRTC + * @name: printf style format string for the CRTC name, or NULL for default name + * + * Inits a new object created as base part of a driver crtc object. Drivers + * should use this function instead of drm_crtc_init(), which is only provided + * for backwards compatibility with drivers which do not yet support universal + * planes). For really simple hardware which has only 1 plane look at + * drm_simple_display_pipe_init() instead. + * + * Cleanup is automatically handled through registering + * drmm_crtc_cleanup() with drmm_add_action(). The crtc structure should + * be allocated with drmm_kzalloc(). + * + * The @drm_crtc_funcs.destroy hook must be NULL. + * + * The @primary and @cursor planes are only relevant for legacy uAPI, see + * &drm_crtc.primary and &drm_crtc.cursor. + * + * Returns: + * Zero on success, error code on failure. + */ +int drmm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc *crtc, + struct drm_plane *primary, + struct drm_plane *cursor, + const struct drm_crtc_funcs *funcs, + const char *name, ...) +{ + va_list ap; + int ret; + + va_start(ap, name); + ret = __drmm_crtc_init_with_planes(dev, crtc, primary, cursor, funcs, + name, ap); + va_end(ap); + if (ret) + return ret; + + return 0; +} +EXPORT_SYMBOL(drmm_crtc_init_with_planes); + void *__drmm_crtc_alloc_with_planes(struct drm_device *dev, size_t size, size_t offset, struct drm_plane *primary, @@ -386,17 +464,12 @@ void *__drmm_crtc_alloc_with_planes(struct drm_device *dev, crtc = container + offset; va_start(ap, name); - ret = __drm_crtc_init_with_planes(dev, crtc, primary, cursor, funcs, - name, ap); + ret = __drmm_crtc_init_with_planes(dev, crtc, primary, cursor, funcs, + name, ap); va_end(ap); if (ret) return ERR_PTR(ret); - ret = drmm_add_action_or_reset(dev, drmm_crtc_alloc_with_planes_cleanup, - crtc); - if (ret) - return ERR_PTR(ret); - return container; } EXPORT_SYMBOL(__drmm_crtc_alloc_with_planes); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index b71c0a3d4126..15495cf67ac4 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -1208,6 +1208,15 @@ int drm_crtc_init_with_planes(struct drm_device *dev, struct drm_plane *cursor, const struct drm_crtc_funcs *funcs, const char *name, ...); + +__printf(6, 7) +int drmm_crtc_init_with_planes(struct drm_device *dev, + struct drm_crtc *crtc, + struct drm_plane *primary, + struct drm_plane *cursor, + const struct drm_crtc_funcs *funcs, + const char *name, ...); + void drm_crtc_cleanup(struct drm_crtc *crtc); __printf(7, 8) From patchwork Fri Jun 14 10:13:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13698510 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F281C41513 for ; Fri, 14 Jun 2024 10:13:38 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.8281.1718360006029977314 for ; Fri, 14 Jun 2024 03:13:30 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.08,237,1712588400"; d="scan'208";a="211895904" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Jun 2024 19:13:30 +0900 Received: from localhost.localdomain (unknown [10.226.92.95]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 7B2B7428BB26; Fri, 14 Jun 2024 19:13:28 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 5.10.y-cip 07/14] dt-bindings: display: Document Renesas RZ/G2L DU bindings Date: Fri, 14 Jun 2024 11:13:01 +0100 Message-Id: <20240614101308.40407-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> References: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 14 Jun 2024 10:13:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16240 commit c1bb7f9f1e151bb50888666108e66ad2848e030d upstream. The RZ/G2L LCD controller is composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). The DU module supports the following hardware features − Display Parallel Interface (DPI) and MIPI LINK Video Interface − Display timing master − Generates video timings − Selecting the polarity of output DCLK, HSYNC, VSYNC, and DE − Supports Progressive − Input data format (from VSPD): RGB888, RGB666 − Output data format: same as Input data format − Supporting Full HD (1920 pixels x 1080 lines) for MIPI-DSI Output − Supporting WXGA (1280 pixels x 800 lines) for Parallel Output This patch documents the DU module found on RZ/G2L LCDC. Signed-off-by: Biju Das Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20240218164840.57662-2-biju.das.jz@bp.renesas.com Signed-off-by: Maxime Ripard Signed-off-by: Biju Das --- .../bindings/display/renesas,rzg2l-du.yaml | 121 ++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml new file mode 100644 index 000000000000..c0ad194c538d --- /dev/null +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L Display Unit (DU) + +maintainers: + - Biju Das + - Laurent Pinchart + +description: | + These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L + and RZ/V2L SoCs. + +properties: + compatible: + enum: + - renesas,r9a07g044-du # RZ/G2{L,LC} + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Main clock + - description: Register access clock + - description: Video clock + + clock-names: + items: + - const: aclk + - const: pclk + - const: vclk + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + The connections to the DU output video ports are modeled using the OF + graph bindings. The number of ports and their assignment are + model-dependent. Each port shall have a single endpoint. + + patternProperties: + "^port@[0-1]$": + $ref: /schemas/graph.yaml#/properties/port + unevaluatedProperties: false + + required: + - port@0 + + unevaluatedProperties: false + + renesas,vsps: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle to VSP instance that serves the DU channel + - description: Channel index identifying the LIF instance in that VSP + description: + A list of phandle and channel index tuples to the VSPs that handle the + memory interfaces for the DU channels. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - power-domains + - ports + - renesas,vsps + +additionalProperties: false + +examples: + # RZ/G2L DU + - | + #include + #include + + display@10890000 { + compatible = "renesas,r9a07g044-du"; + reg = <0x10890000 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + power-domains = <&cpg>; + + renesas,vsps = <&vspd0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + port@1 { + reg = <1>; + }; + }; + }; + +... From patchwork Fri Jun 14 10:13:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13698513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CA36C27C79 for ; Fri, 14 Jun 2024 10:13:38 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.8281.1718360006029977314 for ; Fri, 14 Jun 2024 03:13:32 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.08,237,1712588400"; d="scan'208";a="211895911" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Jun 2024 19:13:32 +0900 Received: from localhost.localdomain (unknown [10.226.92.95]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id CCE0B428BB2E; Fri, 14 Jun 2024 19:13:30 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 5.10.y-cip 08/14] dt-bindings: display: renesas,rzg2l-du: Document RZ/V2L DU bindings Date: Fri, 14 Jun 2024 11:13:02 +0100 Message-Id: <20240614101308.40407-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> References: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 14 Jun 2024 10:13:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16241 commit ac23216bb1f5caa5ae6f3ac70aa7f78a5b50f88d upstream. Document DU found in RZ/V2L SoC. The DU block is identical to RZ/G2L SoC and therefore use RZ/G2L fallback to avoid any driver changes. Signed-off-by: Biju Das Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240218164840.57662-3-biju.das.jz@bp.renesas.com Signed-off-by: Maxime Ripard Signed-off-by: Biju Das --- .../devicetree/bindings/display/renesas,rzg2l-du.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml index c0ad194c538d..08e5b9478051 100644 --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml @@ -16,8 +16,13 @@ description: | properties: compatible: - enum: - - renesas,r9a07g044-du # RZ/G2{L,LC} + oneOf: + - enum: + - renesas,r9a07g044-du # RZ/G2{L,LC} + - items: + - enum: + - renesas,r9a07g054-du # RZ/V2L + - const: renesas,r9a07g044-du # RZ/G2L fallback reg: maxItems: 1 From patchwork Fri Jun 14 10:13:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13698514 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F8A8C27C75 for ; Fri, 14 Jun 2024 10:13:38 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.8281.1718360006029977314 for ; Fri, 14 Jun 2024 03:13:36 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.08,237,1712588400"; d="scan'208";a="211895915" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Jun 2024 19:13:35 +0900 Received: from localhost.localdomain (unknown [10.226.92.95]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 302A3428BB2E; Fri, 14 Jun 2024 19:13:32 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 5.10.y-cip 09/14] drm: renesas: Add RZ/G2L DU Support Date: Fri, 14 Jun 2024 11:13:03 +0100 Message-Id: <20240614101308.40407-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> References: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 14 Jun 2024 10:13:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16242 commit 768e9e61b3b99191d8fe1aead6e71f551738b5c4 upstream. The LCD controller is composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). It has DPI/DSI interfaces and supports a maximum resolution of 1080p along with 2 RPFs to support the blending of two picture layers and raster operations (ROPs). The DU module is connected to VSPD. Add RZ/G2L DU support for RZ/G2L alike SoCs. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20240218164840.57662-4-biju.das.jz@bp.renesas.com Signed-off-by: Maxime Ripard [Biju: Squashed the commit a3baaca4a876 ("drm: renesas: rz-du: Fix redefinition errors related to rzg2l_du_vsp_*()" to fix the build error. Replaced 'depends on'->'select' VIDEO_RENESAS_VSP1 config option to avoid circular dependency Dropped selecting DRM_GEM_DMA_HELPER and instead selected DRM_KMS_CMA_HELPER and DRM_GEM_CMA_HELPER. Replaced of.h->of_device.h, drm_fbdev_generic.h->drm_fb_helper.h, drm/drm_gem_dma_helper.h-> & , drm_atomic_state->drm_{plane,crtc}_state, container_of.h->kernel.h, DEFINE_DRM_GEM_DMA_FOPS->DEFINE_DRM_GEM_CMA_FOPS, .dumb_create()->DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE, void rzg2l_du_remove()->int rzg2l_du_remove(), remove_new()->remove(), drm_gem_dma_dumb_create_internal()->drm_gem_cma_dumb_create_internal(), drm_gem_dma_object->drm_gem_cma_object and DRM_PLANE_NO_SCALING->DRM_PLANE_HELPER_NO_SCALING to fix build error with 5.10.y kernel ] Signed-off-by: Biju Das --- drivers/gpu/drm/renesas/Kconfig | 1 + drivers/gpu/drm/renesas/Makefile | 1 + drivers/gpu/drm/renesas/rz-du/Kconfig | 13 + drivers/gpu/drm/renesas/rz-du/Makefile | 8 + drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 423 ++++++++++++++++++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h | 89 ++++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 175 ++++++++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 78 ++++ .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 72 +++ .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.h | 32 ++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c | 372 +++++++++++++++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.h | 43 ++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c | 344 ++++++++++++++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.h | 82 ++++ 14 files changed, 1733 insertions(+) create mode 100644 drivers/gpu/drm/renesas/rz-du/Kconfig create mode 100644 drivers/gpu/drm/renesas/rz-du/Makefile create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.h create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.h diff --git a/drivers/gpu/drm/renesas/Kconfig b/drivers/gpu/drm/renesas/Kconfig index 3777dad17f81..21862a8ef710 100644 --- a/drivers/gpu/drm/renesas/Kconfig +++ b/drivers/gpu/drm/renesas/Kconfig @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only source "drivers/gpu/drm/renesas/rcar-du/Kconfig" +source "drivers/gpu/drm/renesas/rz-du/Kconfig" source "drivers/gpu/drm/renesas/shmobile/Kconfig" diff --git a/drivers/gpu/drm/renesas/Makefile b/drivers/gpu/drm/renesas/Makefile index ec0e89e7a592..b8d8bc53967f 100644 --- a/drivers/gpu/drm/renesas/Makefile +++ b/drivers/gpu/drm/renesas/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 obj-y += rcar-du/ +obj-y += rz-du/ obj-$(CONFIG_DRM_SHMOBILE) += shmobile/ diff --git a/drivers/gpu/drm/renesas/rz-du/Kconfig b/drivers/gpu/drm/renesas/rz-du/Kconfig new file mode 100644 index 000000000000..156ff3bcc554 --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 +config DRM_RZG2L_DU + tristate "DRM Support for RZ/G2L Display Unit" + depends on ARCH_RZG2L || COMPILE_TEST + depends on DRM && OF + select VIDEO_RENESAS_VSP1 + select DRM_KMS_HELPER + select DRM_KMS_CMA_HELPER + select DRM_GEM_CMA_HELPER + select VIDEOMODE_HELPERS + help + Choose this option if you have an RZ/G2L alike chipset. + If M is selected the module will be called rzg2l-du-drm. diff --git a/drivers/gpu/drm/renesas/rz-du/Makefile b/drivers/gpu/drm/renesas/rz-du/Makefile new file mode 100644 index 000000000000..663b82a2577f --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +rzg2l-du-drm-y := rzg2l_du_crtc.o \ + rzg2l_du_drv.o \ + rzg2l_du_encoder.o \ + rzg2l_du_kms.o \ + +rzg2l-du-drm-$(CONFIG_VIDEO_RENESAS_VSP1) += rzg2l_du_vsp.o +obj-$(CONFIG_DRM_RZG2L_DU) += rzg2l-du-drm.o diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c new file mode 100644 index 000000000000..95ef31b58e55 --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RZ/G2L Display Unit CRTCs + * + * Copyright (C) 2023 Renesas Electronics Corporation + * + * Based on rcar_du_crtc.c + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rzg2l_du_crtc.h" +#include "rzg2l_du_drv.h" +#include "rzg2l_du_encoder.h" +#include "rzg2l_du_kms.h" +#include "rzg2l_du_vsp.h" + +#define DU_MCR0 0x00 +#define DU_MCR0_DI_EN BIT(8) + +#define DU_DITR0 0x10 +#define DU_DITR0_DEMD_HIGH (BIT(8) | BIT(9)) +#define DU_DITR0_VSPOL BIT(16) +#define DU_DITR0_HSPOL BIT(17) + +#define DU_DITR1 0x14 +#define DU_DITR1_VSA(x) ((x) << 0) +#define DU_DITR1_VACTIVE(x) ((x) << 16) + +#define DU_DITR2 0x18 +#define DU_DITR2_VBP(x) ((x) << 0) +#define DU_DITR2_VFP(x) ((x) << 16) + +#define DU_DITR3 0x1c +#define DU_DITR3_HSA(x) ((x) << 0) +#define DU_DITR3_HACTIVE(x) ((x) << 16) + +#define DU_DITR4 0x20 +#define DU_DITR4_HBP(x) ((x) << 0) +#define DU_DITR4_HFP(x) ((x) << 16) + +#define DU_MCR1 0x40 +#define DU_MCR1_PB_AUTOCLR BIT(16) + +#define DU_PBCR0 0x4c +#define DU_PBCR0_PB_DEP(x) ((x) << 0) + +/* ----------------------------------------------------------------------------- + * Hardware Setup + */ + +static void rzg2l_du_crtc_set_display_timing(struct rzg2l_du_crtc *rcrtc) +{ + const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode; + unsigned long mode_clock = mode->clock * 1000; + u32 ditr0, ditr1, ditr2, ditr3, ditr4, pbcr0; + struct rzg2l_du_device *rcdu = rcrtc->dev; + + clk_prepare_enable(rcrtc->rzg2l_clocks.dclk); + clk_set_rate(rcrtc->rzg2l_clocks.dclk, mode_clock); + + ditr0 = (DU_DITR0_DEMD_HIGH + | ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DU_DITR0_VSPOL : 0) + | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DU_DITR0_HSPOL : 0)); + + ditr1 = DU_DITR1_VSA(mode->vsync_end - mode->vsync_start) + | DU_DITR1_VACTIVE(mode->vdisplay); + + ditr2 = DU_DITR2_VBP(mode->vtotal - mode->vsync_end) + | DU_DITR2_VFP(mode->vsync_start - mode->vdisplay); + + ditr3 = DU_DITR3_HSA(mode->hsync_end - mode->hsync_start) + | DU_DITR3_HACTIVE(mode->hdisplay); + + ditr4 = DU_DITR4_HBP(mode->htotal - mode->hsync_end) + | DU_DITR4_HFP(mode->hsync_start - mode->hdisplay); + + pbcr0 = DU_PBCR0_PB_DEP(0x1f); + + writel(ditr0, rcdu->mmio + DU_DITR0); + writel(ditr1, rcdu->mmio + DU_DITR1); + writel(ditr2, rcdu->mmio + DU_DITR2); + writel(ditr3, rcdu->mmio + DU_DITR3); + writel(ditr4, rcdu->mmio + DU_DITR4); + writel(pbcr0, rcdu->mmio + DU_PBCR0); + + /* Enable auto clear */ + writel(DU_MCR1_PB_AUTOCLR, rcdu->mmio + DU_MCR1); +} + +/* ----------------------------------------------------------------------------- + * Page Flip + */ + +void rzg2l_du_crtc_finish_page_flip(struct rzg2l_du_crtc *rcrtc) +{ + struct drm_pending_vblank_event *event; + struct drm_device *dev = rcrtc->crtc.dev; + unsigned long flags; + + spin_lock_irqsave(&dev->event_lock, flags); + event = rcrtc->event; + rcrtc->event = NULL; + spin_unlock_irqrestore(&dev->event_lock, flags); + + if (!event) + return; + + spin_lock_irqsave(&dev->event_lock, flags); + drm_crtc_send_vblank_event(&rcrtc->crtc, event); + wake_up(&rcrtc->flip_wait); + spin_unlock_irqrestore(&dev->event_lock, flags); + + drm_crtc_vblank_put(&rcrtc->crtc); +} + +static bool rzg2l_du_crtc_page_flip_pending(struct rzg2l_du_crtc *rcrtc) +{ + struct drm_device *dev = rcrtc->crtc.dev; + unsigned long flags; + bool pending; + + spin_lock_irqsave(&dev->event_lock, flags); + pending = rcrtc->event; + spin_unlock_irqrestore(&dev->event_lock, flags); + + return pending; +} + +static void rzg2l_du_crtc_wait_page_flip(struct rzg2l_du_crtc *rcrtc) +{ + struct rzg2l_du_device *rcdu = rcrtc->dev; + + if (wait_event_timeout(rcrtc->flip_wait, + !rzg2l_du_crtc_page_flip_pending(rcrtc), + msecs_to_jiffies(50))) + return; + + dev_warn(rcdu->dev, "page flip timeout\n"); + + rzg2l_du_crtc_finish_page_flip(rcrtc); +} + +/* ----------------------------------------------------------------------------- + * Start/Stop and Suspend/Resume + */ + +static void rzg2l_du_crtc_setup(struct rzg2l_du_crtc *rcrtc) +{ + /* Configure display timings and output routing */ + rzg2l_du_crtc_set_display_timing(rcrtc); + + /* Enable the VSP compositor. */ + rzg2l_du_vsp_enable(rcrtc); + + /* Turn vertical blanking interrupt reporting on. */ + drm_crtc_vblank_on(&rcrtc->crtc); +} + +static int rzg2l_du_crtc_get(struct rzg2l_du_crtc *rcrtc) +{ + int ret; + + /* + * Guard against double-get, as the function is called from both the + * .atomic_enable() and .atomic_flush() handlers. + */ + if (rcrtc->initialized) + return 0; + + ret = clk_prepare_enable(rcrtc->rzg2l_clocks.aclk); + if (ret < 0) + return ret; + + ret = clk_prepare_enable(rcrtc->rzg2l_clocks.pclk); + if (ret < 0) + goto error_bus_clock; + + ret = reset_control_deassert(rcrtc->rstc); + if (ret < 0) + goto error_peri_clock; + + rzg2l_du_crtc_setup(rcrtc); + rcrtc->initialized = true; + + return 0; + +error_peri_clock: + clk_disable_unprepare(rcrtc->rzg2l_clocks.pclk); +error_bus_clock: + clk_disable_unprepare(rcrtc->rzg2l_clocks.aclk); + return ret; +} + +static void rzg2l_du_crtc_put(struct rzg2l_du_crtc *rcrtc) +{ + clk_disable_unprepare(rcrtc->rzg2l_clocks.dclk); + reset_control_assert(rcrtc->rstc); + clk_disable_unprepare(rcrtc->rzg2l_clocks.pclk); + clk_disable_unprepare(rcrtc->rzg2l_clocks.aclk); + + rcrtc->initialized = false; +} + +static void rzg2l_du_start_stop(struct rzg2l_du_crtc *rcrtc, bool start) +{ + struct rzg2l_du_device *rcdu = rcrtc->dev; + + writel(start ? DU_MCR0_DI_EN : 0, rcdu->mmio + DU_MCR0); +} + +static void rzg2l_du_crtc_start(struct rzg2l_du_crtc *rcrtc) +{ + rzg2l_du_start_stop(rcrtc, true); +} + +static void rzg2l_du_crtc_stop(struct rzg2l_du_crtc *rcrtc) +{ + struct drm_crtc *crtc = &rcrtc->crtc; + + /* + * Disable vertical blanking interrupt reporting. We first need to wait + * for page flip completion before stopping the CRTC as userspace + * expects page flips to eventually complete. + */ + rzg2l_du_crtc_wait_page_flip(rcrtc); + drm_crtc_vblank_off(crtc); + + /* Disable the VSP compositor. */ + rzg2l_du_vsp_disable(rcrtc); + + rzg2l_du_start_stop(rcrtc, false); +} + +/* ----------------------------------------------------------------------------- + * CRTC Functions + */ + +static void rzg2l_du_crtc_atomic_enable(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc); + + rzg2l_du_crtc_get(rcrtc); + + rzg2l_du_crtc_start(rcrtc); +} + +static void rzg2l_du_crtc_atomic_disable(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc); + + rzg2l_du_crtc_stop(rcrtc); + rzg2l_du_crtc_put(rcrtc); + + spin_lock_irq(&crtc->dev->event_lock); + if (crtc->state->event) { + drm_crtc_send_vblank_event(crtc, crtc->state->event); + crtc->state->event = NULL; + } + spin_unlock_irq(&crtc->dev->event_lock); +} + +static void rzg2l_du_crtc_atomic_flush(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc); + struct drm_device *dev = rcrtc->crtc.dev; + unsigned long flags; + + WARN_ON(!crtc->state->enable); + + if (crtc->state->event) { + WARN_ON(drm_crtc_vblank_get(crtc) != 0); + + spin_lock_irqsave(&dev->event_lock, flags); + rcrtc->event = crtc->state->event; + crtc->state->event = NULL; + spin_unlock_irqrestore(&dev->event_lock, flags); + } + + rzg2l_du_vsp_atomic_flush(rcrtc); +} + +static const struct drm_crtc_helper_funcs crtc_helper_funcs = { + .atomic_flush = rzg2l_du_crtc_atomic_flush, + .atomic_enable = rzg2l_du_crtc_atomic_enable, + .atomic_disable = rzg2l_du_crtc_atomic_disable, +}; + +static struct drm_crtc_state * +rzg2l_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc) +{ + struct rzg2l_du_crtc_state *state; + struct rzg2l_du_crtc_state *copy; + + if (WARN_ON(!crtc->state)) + return NULL; + + state = to_rzg2l_crtc_state(crtc->state); + copy = kmemdup(state, sizeof(*state), GFP_KERNEL); + if (!copy) + return NULL; + + __drm_atomic_helper_crtc_duplicate_state(crtc, ©->state); + + return ©->state; +} + +static void rzg2l_du_crtc_atomic_destroy_state(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + __drm_atomic_helper_crtc_destroy_state(state); + kfree(to_rzg2l_crtc_state(state)); +} + +static void rzg2l_du_crtc_reset(struct drm_crtc *crtc) +{ + struct rzg2l_du_crtc_state *state; + + if (crtc->state) { + rzg2l_du_crtc_atomic_destroy_state(crtc, crtc->state); + crtc->state = NULL; + } + + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (!state) + return; + + __drm_atomic_helper_crtc_reset(crtc, &state->state); +} + +static int rzg2l_du_crtc_enable_vblank(struct drm_crtc *crtc) +{ + struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc); + + rcrtc->vblank_enable = true; + + return 0; +} + +static void rzg2l_du_crtc_disable_vblank(struct drm_crtc *crtc) +{ + struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc); + + rcrtc->vblank_enable = false; +} + +static const struct drm_crtc_funcs crtc_funcs_rz = { + .reset = rzg2l_du_crtc_reset, + .set_config = drm_atomic_helper_set_config, + .page_flip = drm_atomic_helper_page_flip, + .atomic_duplicate_state = rzg2l_du_crtc_atomic_duplicate_state, + .atomic_destroy_state = rzg2l_du_crtc_atomic_destroy_state, + .enable_vblank = rzg2l_du_crtc_enable_vblank, + .disable_vblank = rzg2l_du_crtc_disable_vblank, +}; + +/* ----------------------------------------------------------------------------- + * Initialization + */ + +int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu) +{ + struct rzg2l_du_crtc *rcrtc = &rcdu->crtcs[0]; + struct drm_crtc *crtc = &rcrtc->crtc; + struct drm_plane *primary; + int ret; + + rcrtc->rstc = devm_reset_control_get_shared(rcdu->dev, NULL); + if (IS_ERR(rcrtc->rstc)) { + dev_err(rcdu->dev, "can't get cpg reset\n"); + return PTR_ERR(rcrtc->rstc); + } + + rcrtc->rzg2l_clocks.aclk = devm_clk_get(rcdu->dev, "aclk"); + if (IS_ERR(rcrtc->rzg2l_clocks.aclk)) { + dev_err(rcdu->dev, "no axi clock for DU\n"); + return PTR_ERR(rcrtc->rzg2l_clocks.aclk); + } + + rcrtc->rzg2l_clocks.pclk = devm_clk_get(rcdu->dev, "pclk"); + if (IS_ERR(rcrtc->rzg2l_clocks.pclk)) { + dev_err(rcdu->dev, "no peripheral clock for DU\n"); + return PTR_ERR(rcrtc->rzg2l_clocks.pclk); + } + + rcrtc->rzg2l_clocks.dclk = devm_clk_get(rcdu->dev, "vclk"); + if (IS_ERR(rcrtc->rzg2l_clocks.dclk)) { + dev_err(rcdu->dev, "no video clock for DU\n"); + return PTR_ERR(rcrtc->rzg2l_clocks.dclk); + } + + init_waitqueue_head(&rcrtc->flip_wait); + rcrtc->dev = rcdu; + + primary = rzg2l_du_vsp_get_drm_plane(rcrtc, rcrtc->vsp_pipe); + if (IS_ERR(primary)) + return PTR_ERR(primary); + + ret = drmm_crtc_init_with_planes(&rcdu->ddev, crtc, primary, NULL, + &crtc_funcs_rz, NULL); + if (ret < 0) + return ret; + + drm_crtc_helper_add(crtc, &crtc_helper_funcs); + + return 0; +} diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h new file mode 100644 index 000000000000..f557efc604c5 --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * RZ/G2L Display Unit CRTCs + * + * Copyright (C) 2023 Renesas Electronics Corporation + * + * Based on rcar_du_crtc.h + */ + +#ifndef __RZG2L_DU_CRTC_H__ +#define __RZG2L_DU_CRTC_H__ + +#include +#include +#include +#include + +#include +#include + +#include + +struct clk; +struct reset_control; +struct rzg2l_du_vsp; +struct rzg2l_du_format_info; + +/** + * struct rzg2l_du_crtc - the CRTC, representing a DU superposition processor + * @crtc: base DRM CRTC + * @dev: the DU device + * @initialized: whether the CRTC has been initialized and clocks enabled + * @vblank_enable: whether vblank events are enabled on this CRTC + * @event: event to post when the pending page flip completes + * @flip_wait: wait queue used to signal page flip completion + * @vsp: VSP feeding video to this CRTC + * @vsp_pipe: index of the VSP pipeline feeding video to this CRTC + * @rstc: reset controller + * @rzg2l_clocks: the bus, main and video clock + */ +struct rzg2l_du_crtc { + struct drm_crtc crtc; + + struct rzg2l_du_device *dev; + bool initialized; + + bool vblank_enable; + struct drm_pending_vblank_event *event; + wait_queue_head_t flip_wait; + + struct rzg2l_du_vsp *vsp; + unsigned int vsp_pipe; + + const char *const *sources; + unsigned int sources_count; + + struct reset_control *rstc; + struct { + struct clk *aclk; + struct clk *pclk; + struct clk *dclk; + } rzg2l_clocks; +}; + +static inline struct rzg2l_du_crtc *to_rzg2l_crtc(struct drm_crtc *c) +{ + return container_of(c, struct rzg2l_du_crtc, crtc); +} + +/** + * struct rzg2l_du_crtc_state - Driver-specific CRTC state + * @state: base DRM CRTC state + * @outputs: bitmask of the outputs (enum rzg2l_du_output) driven by this CRTC + */ +struct rzg2l_du_crtc_state { + struct drm_crtc_state state; + unsigned int outputs; +}; + +static inline struct rzg2l_du_crtc_state *to_rzg2l_crtc_state(struct drm_crtc_state *s) +{ + return container_of(s, struct rzg2l_du_crtc_state, state); +} + +int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu); + +void rzg2l_du_crtc_finish_page_flip(struct rzg2l_du_crtc *rcrtc); + +#endif /* __RZG2L_DU_CRTC_H__ */ diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c new file mode 100644 index 000000000000..01ae5a5dffde --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RZ/G2L Display Unit DRM driver + * + * Copyright (C) 2023 Renesas Electronics Corporation + * + * Based on rcar_du_drv.c + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "rzg2l_du_drv.h" +#include "rzg2l_du_kms.h" + +/* ----------------------------------------------------------------------------- + * Device Information + */ + +static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = { + .channels_mask = BIT(0), + .routes = { + [RZG2L_DU_OUTPUT_DSI0] = { + .possible_outputs = BIT(0), + .port = 0, + }, + [RZG2L_DU_OUTPUT_DPAD0] = { + .possible_outputs = BIT(0), + .port = 1, + } + } +}; + +static const struct of_device_id rzg2l_du_of_table[] = { + { .compatible = "renesas,r9a07g044-du", .data = &rzg2l_du_r9a07g044_info }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, rzg2l_du_of_table); + +const char *rzg2l_du_output_name(enum rzg2l_du_output output) +{ + static const char * const names[] = { + [RZG2L_DU_OUTPUT_DSI0] = "DSI0", + [RZG2L_DU_OUTPUT_DPAD0] = "DPAD0" + }; + + if (output >= ARRAY_SIZE(names)) + return "UNKNOWN"; + + return names[output]; +} + +/* ----------------------------------------------------------------------------- + * DRM operations + */ + +DEFINE_DRM_GEM_CMA_FOPS(rzg2l_du_fops); + +static const struct drm_driver rzg2l_du_driver = { + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, + DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(rzg2l_du_dumb_create), + .fops = &rzg2l_du_fops, + .name = "rzg2l-du", + .desc = "Renesas RZ/G2L Display Unit", + .date = "20230410", + .major = 1, + .minor = 0, +}; + +/* ----------------------------------------------------------------------------- + * Platform driver + */ + +static int rzg2l_du_remove(struct platform_device *pdev) +{ + struct rzg2l_du_device *rcdu = platform_get_drvdata(pdev); + struct drm_device *ddev = &rcdu->ddev; + + drm_dev_unregister(ddev); + drm_atomic_helper_shutdown(ddev); + + drm_kms_helper_poll_fini(ddev); + + return 0; +} + +static void rzg2l_du_shutdown(struct platform_device *pdev) +{ + struct rzg2l_du_device *rcdu = platform_get_drvdata(pdev); + + drm_atomic_helper_shutdown(&rcdu->ddev); +} + +static int rzg2l_du_probe(struct platform_device *pdev) +{ + struct rzg2l_du_device *rcdu; + int ret; + + /* Allocate and initialize the RZ/G2L device structure. */ + rcdu = devm_drm_dev_alloc(&pdev->dev, &rzg2l_du_driver, + struct rzg2l_du_device, ddev); + if (IS_ERR(rcdu)) + return PTR_ERR(rcdu); + + rcdu->dev = &pdev->dev; + rcdu->info = of_device_get_match_data(rcdu->dev); + + platform_set_drvdata(pdev, rcdu); + + /* I/O resources */ + rcdu->mmio = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rcdu->mmio)) + return PTR_ERR(rcdu->mmio); + + ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (ret) + return ret; + + /* DRM/KMS objects */ + ret = rzg2l_du_modeset_init(rcdu); + if (ret < 0) { + /* + * Don't use dev_err_probe(), as it would overwrite the probe + * deferral reason recorded in rzg2l_du_modeset_init(). + */ + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, + "failed to initialize DRM/KMS (%d)\n", ret); + goto error; + } + + /* + * Register the DRM device with the core and the connectors with + * sysfs. + */ + ret = drm_dev_register(&rcdu->ddev, 0); + if (ret) + goto error; + + drm_info(&rcdu->ddev, "Device %s probed\n", dev_name(&pdev->dev)); + + drm_fbdev_generic_setup(&rcdu->ddev, 32); + + return 0; + +error: + drm_kms_helper_poll_fini(&rcdu->ddev); + return ret; +} + +static struct platform_driver rzg2l_du_platform_driver = { + .probe = rzg2l_du_probe, + .remove = rzg2l_du_remove, + .shutdown = rzg2l_du_shutdown, + .driver = { + .name = "rzg2l-du", + .of_match_table = rzg2l_du_of_table, + }, +}; + +module_platform_driver(rzg2l_du_platform_driver); + +MODULE_AUTHOR("Biju Das "); +MODULE_DESCRIPTION("Renesas RZ/G2L Display Unit DRM Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h new file mode 100644 index 000000000000..58806c2a8f2b --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * RZ/G2L Display Unit DRM driver + * + * Copyright (C) 2023 Renesas Electronics Corporation + * + * Based on rcar_du_drv.h + */ + +#ifndef __RZG2L_DU_DRV_H__ +#define __RZG2L_DU_DRV_H__ + +#include + +#include + +#include "rzg2l_du_crtc.h" +#include "rzg2l_du_vsp.h" + +struct device; +struct drm_property; + +enum rzg2l_du_output { + RZG2L_DU_OUTPUT_DSI0, + RZG2L_DU_OUTPUT_DPAD0, + RZG2L_DU_OUTPUT_MAX, +}; + +/* + * struct rzg2l_du_output_routing - Output routing specification + * @possible_outputs: bitmask of possible outputs + * @port: device tree port number corresponding to this output route + * + * The DU has 2 possible outputs (DPAD0, DSI0). Output routing data + * specify the valid SoC outputs, which CRTC can drive the output, and the type + * of in-SoC encoder for the output. + */ +struct rzg2l_du_output_routing { + unsigned int possible_outputs; + unsigned int port; +}; + +/* + * struct rzg2l_du_device_info - DU model-specific information + * @channels_mask: bit mask of available DU channels + * @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_OUTPUT_*) + */ +struct rzg2l_du_device_info { + unsigned int channels_mask; + struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX]; +}; + +#define RZG2L_DU_MAX_CRTCS 1 +#define RZG2L_DU_MAX_VSPS 1 +#define RZG2L_DU_MAX_DSI 1 + +struct rzg2l_du_device { + struct device *dev; + const struct rzg2l_du_device_info *info; + + void __iomem *mmio; + + struct drm_device ddev; + + struct rzg2l_du_crtc crtcs[RZG2L_DU_MAX_CRTCS]; + unsigned int num_crtcs; + + struct rzg2l_du_vsp vsps[RZG2L_DU_MAX_VSPS]; +}; + +static inline struct rzg2l_du_device *to_rzg2l_du_device(struct drm_device *dev) +{ + return container_of(dev, struct rzg2l_du_device, ddev); +} + +const char *rzg2l_du_output_name(enum rzg2l_du_output output); + +#endif /* __RZG2L_DU_DRV_H__ */ diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c new file mode 100644 index 000000000000..339cbaaea0b5 --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RZ/G2L Display Unit Encoder + * + * Copyright (C) 2023 Renesas Electronics Corporation + * + * Based on rcar_du_encoder.c + */ + +#include +#include + +#include +#include +#include + +#include "rzg2l_du_drv.h" +#include "rzg2l_du_encoder.h" + +/* ----------------------------------------------------------------------------- + * Encoder + */ + +static const struct drm_encoder_funcs rzg2l_du_encoder_funcs = { +}; + +int rzg2l_du_encoder_init(struct rzg2l_du_device *rcdu, + enum rzg2l_du_output output, + struct device_node *enc_node) +{ + struct rzg2l_du_encoder *renc; + struct drm_connector *connector; + struct drm_bridge *bridge; + int ret; + + /* Locate the DRM bridge from the DT node. */ + bridge = of_drm_find_bridge(enc_node); + if (!bridge) + return -EPROBE_DEFER; + + dev_dbg(rcdu->dev, "initializing encoder %pOF for output %s\n", + enc_node, rzg2l_du_output_name(output)); + + renc = drmm_encoder_alloc(&rcdu->ddev, struct rzg2l_du_encoder, base, + &rzg2l_du_encoder_funcs, DRM_MODE_ENCODER_NONE, + NULL); + if (IS_ERR(renc)) + return PTR_ERR(renc); + + renc->output = output; + + /* Attach the bridge to the encoder. */ + ret = drm_bridge_attach(&renc->base, bridge, NULL, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); + if (ret) { + dev_err(rcdu->dev, + "failed to attach bridge %pOF for output %s (%d)\n", + bridge->of_node, rzg2l_du_output_name(output), ret); + return ret; + } + + /* Create the connector for the chain of bridges. */ + connector = drm_bridge_connector_init(&rcdu->ddev, &renc->base); + if (IS_ERR(connector)) { + dev_err(rcdu->dev, + "failed to created connector for output %s (%ld)\n", + rzg2l_du_output_name(output), PTR_ERR(connector)); + return PTR_ERR(connector); + } + + return drm_connector_attach_encoder(connector, &renc->base); +} diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h new file mode 100644 index 000000000000..a2d38288456a --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * RZ/G2L Display Unit Encoder + * + * Copyright (C) 2023 Renesas Electronics Corporation + * + * Based on rcar_du_encoder.h + */ + +#ifndef __RZG2L_DU_ENCODER_H__ +#define __RZG2L_DU_ENCODER_H__ + +#include +#include + +struct rzg2l_du_device; + +struct rzg2l_du_encoder { + struct drm_encoder base; + enum rzg2l_du_output output; +}; + +static inline struct rzg2l_du_encoder *to_rzg2l_encoder(struct drm_encoder *e) +{ + return container_of(e, struct rzg2l_du_encoder, base); +} + +int rzg2l_du_encoder_init(struct rzg2l_du_device *rcdu, + enum rzg2l_du_output output, + struct device_node *enc_node); + +#endif /* __RZG2L_DU_ENCODER_H__ */ diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c new file mode 100644 index 000000000000..3c32ecfbe56a --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RZ/G2L Display Unit Mode Setting + * + * Copyright (C) 2023 Renesas Electronics Corporation + * + * Based on rcar_du_kms.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "rzg2l_du_crtc.h" +#include "rzg2l_du_drv.h" +#include "rzg2l_du_encoder.h" +#include "rzg2l_du_kms.h" +#include "rzg2l_du_vsp.h" + +/* ----------------------------------------------------------------------------- + * Format helpers + */ + +static const struct rzg2l_du_format_info rzg2l_du_format_infos[] = { + { + .fourcc = DRM_FORMAT_XRGB8888, + .v4l2 = V4L2_PIX_FMT_XBGR32, + .bpp = 32, + .planes = 1, + .hsub = 1, + }, { + .fourcc = DRM_FORMAT_ARGB8888, + .v4l2 = V4L2_PIX_FMT_ABGR32, + .bpp = 32, + .planes = 1, + .hsub = 1, + }, { + .fourcc = DRM_FORMAT_RGB888, + .v4l2 = V4L2_PIX_FMT_BGR24, + .bpp = 24, + .planes = 1, + .hsub = 1, + } +}; + +const struct rzg2l_du_format_info *rzg2l_du_format_info(u32 fourcc) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(rzg2l_du_format_infos); ++i) { + if (rzg2l_du_format_infos[i].fourcc == fourcc) + return &rzg2l_du_format_infos[i]; + } + + return NULL; +} + +/* ----------------------------------------------------------------------------- + * Frame buffer + */ + +int rzg2l_du_dumb_create(struct drm_file *file, struct drm_device *dev, + struct drm_mode_create_dumb *args) +{ + unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8); + unsigned int align = 16 * args->bpp / 8; + + args->pitch = roundup(min_pitch, align); + + return drm_gem_cma_dumb_create_internal(file, dev, args); +} + +static struct drm_framebuffer * +rzg2l_du_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_mode_fb_cmd2 *mode_cmd) +{ + const struct rzg2l_du_format_info *format; + unsigned int max_pitch; + + format = rzg2l_du_format_info(mode_cmd->pixel_format); + if (!format) { + dev_dbg(dev->dev, "unsupported pixel format %p4cc\n", + &mode_cmd->pixel_format); + return ERR_PTR(-EINVAL); + } + + /* + * On RZ/G2L the memory interface is handled by the VSP that limits the + * pitch to 65535 bytes. + */ + max_pitch = 65535; + if (mode_cmd->pitches[0] > max_pitch) { + dev_dbg(dev->dev, "invalid pitch value %u\n", + mode_cmd->pitches[0]); + return ERR_PTR(-EINVAL); + } + + return drm_gem_fb_create(dev, file_priv, mode_cmd); +} + +/* ----------------------------------------------------------------------------- + * Initialization + */ + +static const struct drm_mode_config_helper_funcs rzg2l_du_mode_config_helper = { + .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, +}; + +static const struct drm_mode_config_funcs rzg2l_du_mode_config_funcs = { + .fb_create = rzg2l_du_fb_create, + .atomic_check = drm_atomic_helper_check, + .atomic_commit = drm_atomic_helper_commit, +}; + +static int rzg2l_du_encoders_init_one(struct rzg2l_du_device *rcdu, + enum rzg2l_du_output output, + struct of_endpoint *ep) +{ + struct device_node *entity; + int ret; + + /* Locate the connected entity and initialize the encoder. */ + entity = of_graph_get_remote_port_parent(ep->local_node); + if (!entity) { + dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n", + ep->local_node); + return -ENODEV; + } + + if (!of_device_is_available(entity)) { + dev_dbg(rcdu->dev, + "connected entity %pOF is disabled, skipping\n", + entity); + of_node_put(entity); + return -ENODEV; + } + + ret = rzg2l_du_encoder_init(rcdu, output, entity); + if (ret && ret != -EPROBE_DEFER && ret != -ENOLINK) + dev_warn(rcdu->dev, + "failed to initialize encoder %pOF on output %s (%d), skipping\n", + entity, rzg2l_du_output_name(output), ret); + + of_node_put(entity); + + return ret; +} + +static int rzg2l_du_encoders_init(struct rzg2l_du_device *rcdu) +{ + struct device_node *np = rcdu->dev->of_node; + struct device_node *ep_node; + unsigned int num_encoders = 0; + + /* + * Iterate over the endpoints and create one encoder for each output + * pipeline. + */ + for_each_endpoint_of_node(np, ep_node) { + enum rzg2l_du_output output; + struct of_endpoint ep; + unsigned int i; + int ret; + + ret = of_graph_parse_endpoint(ep_node, &ep); + if (ret < 0) { + of_node_put(ep_node); + return ret; + } + + /* Find the output route corresponding to the port number. */ + for (i = 0; i < RZG2L_DU_OUTPUT_MAX; ++i) { + if (rcdu->info->routes[i].port == ep.port) { + output = i; + break; + } + } + + if (i == RZG2L_DU_OUTPUT_MAX) { + dev_warn(rcdu->dev, + "port %u references unexisting output, skipping\n", + ep.port); + continue; + } + + /* Process the output pipeline. */ + ret = rzg2l_du_encoders_init_one(rcdu, output, &ep); + if (ret < 0) { + if (ret == -EPROBE_DEFER) { + of_node_put(ep_node); + return ret; + } + + continue; + } + + num_encoders++; + } + + return num_encoders; +} + +static int rzg2l_du_vsps_init(struct rzg2l_du_device *rcdu) +{ + const struct device_node *np = rcdu->dev->of_node; + const char *vsps_prop_name = "renesas,vsps"; + struct of_phandle_args args; + struct { + struct device_node *np; + unsigned int crtcs_mask; + } vsps[RZG2L_DU_MAX_VSPS] = { { NULL, }, }; + unsigned int vsps_count = 0; + unsigned int cells; + unsigned int i; + int ret; + + /* + * First parse the DT vsps property to populate the list of VSPs. Each + * entry contains a pointer to the VSP DT node and a bitmask of the + * connected DU CRTCs. + */ + ret = of_property_count_u32_elems(np, vsps_prop_name); + cells = ret / rcdu->num_crtcs - 1; + if (cells != 1) + return -EINVAL; + + for (i = 0; i < rcdu->num_crtcs; ++i) { + unsigned int j; + + ret = of_parse_phandle_with_fixed_args(np, vsps_prop_name, + cells, i, &args); + if (ret < 0) + goto done; + + /* + * Add the VSP to the list or update the corresponding existing + * entry if the VSP has already been added. + */ + for (j = 0; j < vsps_count; ++j) { + if (vsps[j].np == args.np) + break; + } + + if (j < vsps_count) + of_node_put(args.np); + else + vsps[vsps_count++].np = args.np; + + vsps[j].crtcs_mask |= BIT(i); + + /* + * Store the VSP pointer and pipe index in the CRTC. If the + * second cell of the 'renesas,vsps' specifier isn't present, + * default to 0. + */ + rcdu->crtcs[i].vsp = &rcdu->vsps[j]; + rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0; + } + + /* + * Then initialize all the VSPs from the node pointers and CRTCs bitmask + * computed previously. + */ + for (i = 0; i < vsps_count; ++i) { + struct rzg2l_du_vsp *vsp = &rcdu->vsps[i]; + + vsp->index = i; + vsp->dev = rcdu; + + ret = rzg2l_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask); + if (ret) + goto done; + } + +done: + for (i = 0; i < ARRAY_SIZE(vsps); ++i) + of_node_put(vsps[i].np); + + return ret; +} + +int rzg2l_du_modeset_init(struct rzg2l_du_device *rcdu) +{ + struct drm_device *dev = &rcdu->ddev; + struct drm_encoder *encoder; + unsigned int num_encoders; + int ret; + + ret = drmm_mode_config_init(dev); + if (ret) + return ret; + + dev->mode_config.min_width = 0; + dev->mode_config.min_height = 0; + dev->mode_config.normalize_zpos = true; + dev->mode_config.funcs = &rzg2l_du_mode_config_funcs; + dev->mode_config.helper_private = &rzg2l_du_mode_config_helper; + + /* + * The RZ DU uses the VSP1 for memory access, and is limited + * to frame sizes of 1920x1080. + */ + dev->mode_config.max_width = 1920; + dev->mode_config.max_height = 1080; + + rcdu->num_crtcs = hweight8(rcdu->info->channels_mask); + + /* + * Initialize vertical blanking interrupts handling. Start with vblank + * disabled for all CRTCs. + */ + ret = drm_vblank_init(dev, rcdu->num_crtcs); + if (ret < 0) + return ret; + + /* Initialize the compositors. */ + ret = rzg2l_du_vsps_init(rcdu); + if (ret < 0) + return ret; + + /* Create the CRTCs. */ + ret = rzg2l_du_crtc_create(rcdu); + if (ret < 0) + return ret; + + /* Initialize the encoders. */ + ret = rzg2l_du_encoders_init(rcdu); + if (ret < 0) + return dev_err_probe(rcdu->dev, ret, + "failed to initialize encoders\n"); + + if (ret == 0) { + dev_err(rcdu->dev, "error: no encoder could be initialized\n"); + return -EINVAL; + } + + num_encoders = ret; + + /* + * Set the possible CRTCs and possible clones. There's always at least + * one way for all encoders to clone each other, set all bits in the + * possible clones field. + */ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder); + const struct rzg2l_du_output_routing *route = + &rcdu->info->routes[renc->output]; + + encoder->possible_crtcs = route->possible_outputs; + encoder->possible_clones = (1 << num_encoders) - 1; + } + + drm_mode_config_reset(dev); + + drm_kms_helper_poll_init(dev); + + return 0; +} diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.h new file mode 100644 index 000000000000..876e97cfbf45 --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * RZ/G2L Display Unit Mode Setting + * + * Copyright (C) 2023 Renesas Electronics Corporation + * + * Based on rcar_du_kms.h + */ + +#ifndef __RZG2L_DU_KMS_H__ +#define __RZG2L_DU_KMS_H__ + +#include + +struct dma_buf_attachment; +struct drm_file; +struct drm_device; +struct drm_gem_object; +struct drm_mode_create_dumb; +struct rzg2l_du_device; +struct sg_table; + +struct rzg2l_du_format_info { + u32 fourcc; + u32 v4l2; + unsigned int bpp; + unsigned int planes; + unsigned int hsub; +}; + +const struct rzg2l_du_format_info *rzg2l_du_format_info(u32 fourcc); + +int rzg2l_du_modeset_init(struct rzg2l_du_device *rcdu); + +int rzg2l_du_dumb_create(struct drm_file *file, struct drm_device *dev, + struct drm_mode_create_dumb *args); + +struct drm_gem_object * +rzg2l_du_gem_prime_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, + struct sg_table *sgt); + +#endif /* __RZG2L_DU_KMS_H__ */ diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c new file mode 100644 index 000000000000..8cf7b7a9bef6 --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RZ/G2L Display Unit VSP-Based Compositor + * + * Copyright (C) 2023 Renesas Electronics Corporation + * + * Based on rcar_du_vsp.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "rzg2l_du_drv.h" +#include "rzg2l_du_kms.h" +#include "rzg2l_du_vsp.h" + +static void rzg2l_du_vsp_complete(void *private, unsigned int status, u32 crc) +{ + struct rzg2l_du_crtc *crtc = private; + + if (crtc->vblank_enable) + drm_crtc_handle_vblank(&crtc->crtc); + + if (status & VSP1_DU_STATUS_COMPLETE) + rzg2l_du_crtc_finish_page_flip(crtc); + + drm_crtc_add_crc_entry(&crtc->crtc, false, 0, &crc); +} + +void rzg2l_du_vsp_enable(struct rzg2l_du_crtc *crtc) +{ + const struct drm_display_mode *mode = &crtc->crtc.state->adjusted_mode; + struct vsp1_du_lif_config cfg = { + .width = mode->hdisplay, + .height = mode->vdisplay, + .interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE, + .callback = rzg2l_du_vsp_complete, + .callback_data = crtc, + }; + + vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, &cfg); +} + +void rzg2l_du_vsp_disable(struct rzg2l_du_crtc *crtc) +{ + vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, NULL); +} + +void rzg2l_du_vsp_atomic_flush(struct rzg2l_du_crtc *crtc) +{ + struct vsp1_du_atomic_pipe_config cfg = { { 0, } }; + struct rzg2l_du_crtc_state *state; + + state = to_rzg2l_crtc_state(crtc->crtc.state); + + vsp1_du_atomic_flush(crtc->vsp->vsp, crtc->vsp_pipe, &cfg); +} + +struct drm_plane *rzg2l_du_vsp_get_drm_plane(struct rzg2l_du_crtc *crtc, + unsigned int pipe_index) +{ + struct rzg2l_du_device *rcdu = crtc->vsp->dev; + struct drm_plane *plane = NULL; + + drm_for_each_plane(plane, &rcdu->ddev) { + struct rzg2l_du_vsp_plane *vsp_plane = to_rzg2l_vsp_plane(plane); + + if (vsp_plane->index == pipe_index) + break; + } + + return plane ? plane : ERR_PTR(-EINVAL); +} + +static const u32 rzg2l_du_vsp_formats[] = { + DRM_FORMAT_RGB332, + DRM_FORMAT_ARGB4444, + DRM_FORMAT_XRGB4444, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_XRGB1555, + DRM_FORMAT_RGB565, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, + DRM_FORMAT_YVYU, + DRM_FORMAT_NV12, + DRM_FORMAT_NV21, + DRM_FORMAT_NV16, + DRM_FORMAT_NV61, + DRM_FORMAT_YUV420, + DRM_FORMAT_YVU420, + DRM_FORMAT_YUV422, + DRM_FORMAT_YVU422, + DRM_FORMAT_YUV444, + DRM_FORMAT_YVU444, +}; + +static void rzg2l_du_vsp_plane_setup(struct rzg2l_du_vsp_plane *plane) +{ + struct rzg2l_du_vsp_plane_state *state = + to_rzg2l_vsp_plane_state(plane->plane.state); + struct rzg2l_du_crtc *crtc = to_rzg2l_crtc(state->state.crtc); + struct drm_framebuffer *fb = plane->plane.state->fb; + const struct rzg2l_du_format_info *format; + struct vsp1_du_atomic_config cfg = { + .pixelformat = 0, + .pitch = fb->pitches[0], + .alpha = state->state.alpha >> 8, + .zpos = state->state.zpos, + }; + u32 fourcc = state->format->fourcc; + unsigned int i; + + cfg.src.left = state->state.src.x1 >> 16; + cfg.src.top = state->state.src.y1 >> 16; + cfg.src.width = drm_rect_width(&state->state.src) >> 16; + cfg.src.height = drm_rect_height(&state->state.src) >> 16; + + cfg.dst.left = state->state.dst.x1; + cfg.dst.top = state->state.dst.y1; + cfg.dst.width = drm_rect_width(&state->state.dst); + cfg.dst.height = drm_rect_height(&state->state.dst); + + for (i = 0; i < state->format->planes; ++i) { + struct drm_gem_cma_object *gem; + + gem = drm_fb_cma_get_gem_obj(fb, i); + cfg.mem[i] = gem->paddr + fb->offsets[i]; + } + + if (state->state.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) { + switch (fourcc) { + case DRM_FORMAT_ARGB1555: + fourcc = DRM_FORMAT_XRGB1555; + break; + + case DRM_FORMAT_ARGB4444: + fourcc = DRM_FORMAT_XRGB4444; + break; + + case DRM_FORMAT_ARGB8888: + fourcc = DRM_FORMAT_XRGB8888; + break; + } + } + + format = rzg2l_du_format_info(fourcc); + cfg.pixelformat = format->v4l2; + + vsp1_du_atomic_update(plane->vsp->vsp, crtc->vsp_pipe, + plane->index, &cfg); +} + +static int __rzg2l_du_vsp_plane_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state, + const struct rzg2l_du_format_info **format) +{ + struct drm_crtc_state *crtc_state; + int ret; + + if (!state->crtc) { + /* + * The visible field is not reset by the DRM core but only + * updated by drm_atomic_helper_check_plane_state, set it + * manually. + */ + state->visible = false; + *format = NULL; + return 0; + } + + crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + + ret = drm_atomic_helper_check_plane_state(state, crtc_state, + DRM_PLANE_HELPER_NO_SCALING, + DRM_PLANE_HELPER_NO_SCALING, + true, true); + if (ret < 0) + return ret; + + if (!state->visible) { + *format = NULL; + return 0; + } + + *format = rzg2l_du_format_info(state->fb->format->format); + + return 0; +} + +static int rzg2l_du_vsp_plane_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct rzg2l_du_vsp_plane_state *rstate = to_rzg2l_vsp_plane_state(state); + + return __rzg2l_du_vsp_plane_atomic_check(plane, state, &rstate->format); +} + +static void rzg2l_du_vsp_plane_atomic_update(struct drm_plane *plane, + struct drm_plane_state *old_state) +{ + struct rzg2l_du_vsp_plane *rplane = to_rzg2l_vsp_plane(plane); + struct rzg2l_du_crtc *crtc = to_rzg2l_crtc(old_state->crtc); + + if (plane->state->visible) + rzg2l_du_vsp_plane_setup(rplane); + else if (old_state->crtc) + vsp1_du_atomic_update(rplane->vsp->vsp, crtc->vsp_pipe, + rplane->index, NULL); +} + +static const struct drm_plane_helper_funcs rzg2l_du_vsp_plane_helper_funcs = { + .atomic_check = rzg2l_du_vsp_plane_atomic_check, + .atomic_update = rzg2l_du_vsp_plane_atomic_update, +}; + +static struct drm_plane_state * +rzg2l_du_vsp_plane_atomic_duplicate_state(struct drm_plane *plane) +{ + struct rzg2l_du_vsp_plane_state *copy; + + if (WARN_ON(!plane->state)) + return NULL; + + copy = kzalloc(sizeof(*copy), GFP_KERNEL); + if (!copy) + return NULL; + + __drm_atomic_helper_plane_duplicate_state(plane, ©->state); + + return ©->state; +} + +static void rzg2l_du_vsp_plane_atomic_destroy_state(struct drm_plane *plane, + struct drm_plane_state *state) +{ + __drm_atomic_helper_plane_destroy_state(state); + kfree(to_rzg2l_vsp_plane_state(state)); +} + +static void rzg2l_du_vsp_plane_reset(struct drm_plane *plane) +{ + struct rzg2l_du_vsp_plane_state *state; + + if (plane->state) { + rzg2l_du_vsp_plane_atomic_destroy_state(plane, plane->state); + plane->state = NULL; + } + + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (!state) + return; + + __drm_atomic_helper_plane_reset(plane, &state->state); +} + +static const struct drm_plane_funcs rzg2l_du_vsp_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .reset = rzg2l_du_vsp_plane_reset, + .atomic_duplicate_state = rzg2l_du_vsp_plane_atomic_duplicate_state, + .atomic_destroy_state = rzg2l_du_vsp_plane_atomic_destroy_state, +}; + +static void rzg2l_du_vsp_cleanup(struct drm_device *dev, void *res) +{ + struct rzg2l_du_vsp *vsp = res; + + put_device(vsp->vsp); +} + +int rzg2l_du_vsp_init(struct rzg2l_du_vsp *vsp, struct device_node *np, + unsigned int crtcs) +{ + struct rzg2l_du_device *rcdu = vsp->dev; + struct platform_device *pdev; + unsigned int num_crtcs = hweight32(crtcs); + unsigned int num_planes = 2; + unsigned int i; + int ret; + + /* Find the VSP device and initialize it. */ + pdev = of_find_device_by_node(np); + if (!pdev) + return -ENXIO; + + vsp->vsp = &pdev->dev; + + ret = drmm_add_action_or_reset(&rcdu->ddev, rzg2l_du_vsp_cleanup, vsp); + if (ret < 0) + return ret; + + ret = vsp1_du_init(vsp->vsp); + if (ret < 0) + return ret; + + for (i = 0; i < num_planes; ++i) { + enum drm_plane_type type = i < num_crtcs + ? DRM_PLANE_TYPE_PRIMARY + : DRM_PLANE_TYPE_OVERLAY; + struct rzg2l_du_vsp_plane *plane; + + plane = drmm_universal_plane_alloc(&rcdu->ddev, struct rzg2l_du_vsp_plane, + plane, crtcs, &rzg2l_du_vsp_plane_funcs, + rzg2l_du_vsp_formats, + ARRAY_SIZE(rzg2l_du_vsp_formats), + NULL, type, NULL); + if (IS_ERR(plane)) + return PTR_ERR(plane); + + plane->vsp = vsp; + plane->index = i; + + drm_plane_helper_add(&plane->plane, + &rzg2l_du_vsp_plane_helper_funcs); + } + + return 0; +} diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.h new file mode 100644 index 000000000000..566010e4328d --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * RZ/G2L Display Unit VSP-Based Compositor + * + * Copyright (C) 2023 Renesas Electronics Corporation + * + * Based on rcar_du_vsp.h + */ + +#ifndef __RZG2L_DU_VSP_H__ +#define __RZG2L_DU_VSP_H__ + +#include +#include +#include + +struct device; +struct drm_framebuffer; +struct rzg2l_du_device; +struct rzg2l_du_format_info; +struct rzg2l_du_vsp; + +struct rzg2l_du_vsp_plane { + struct drm_plane plane; + struct rzg2l_du_vsp *vsp; + unsigned int index; +}; + +struct rzg2l_du_vsp { + unsigned int index; + struct device *vsp; + struct rzg2l_du_device *dev; +}; + +static inline struct rzg2l_du_vsp_plane *to_rzg2l_vsp_plane(struct drm_plane *p) +{ + return container_of(p, struct rzg2l_du_vsp_plane, plane); +} + +/** + * struct rzg2l_du_vsp_plane_state - Driver-specific plane state + * @state: base DRM plane state + * @format: information about the pixel format used by the plane + */ +struct rzg2l_du_vsp_plane_state { + struct drm_plane_state state; + + const struct rzg2l_du_format_info *format; +}; + +static inline struct rzg2l_du_vsp_plane_state * +to_rzg2l_vsp_plane_state(struct drm_plane_state *state) +{ + return container_of(state, struct rzg2l_du_vsp_plane_state, state); +} + +#if IS_ENABLED(CONFIG_VIDEO_RENESAS_VSP1) +int rzg2l_du_vsp_init(struct rzg2l_du_vsp *vsp, struct device_node *np, + unsigned int crtcs); +void rzg2l_du_vsp_enable(struct rzg2l_du_crtc *crtc); +void rzg2l_du_vsp_disable(struct rzg2l_du_crtc *crtc); +void rzg2l_du_vsp_atomic_flush(struct rzg2l_du_crtc *crtc); +struct drm_plane *rzg2l_du_vsp_get_drm_plane(struct rzg2l_du_crtc *crtc, + unsigned int pipe_index); +#else +static inline int rzg2l_du_vsp_init(struct rzg2l_du_vsp *vsp, struct device_node *np, + unsigned int crtcs) +{ + return -ENXIO; +} + +static inline void rzg2l_du_vsp_enable(struct rzg2l_du_crtc *crtc) { }; +static inline void rzg2l_du_vsp_disable(struct rzg2l_du_crtc *crtc) { }; +static inline void rzg2l_du_vsp_atomic_flush(struct rzg2l_du_crtc *crtc) { }; +static inline struct drm_plane *rzg2l_du_vsp_get_drm_plane(struct rzg2l_du_crtc *crtc, + unsigned int pipe_index) +{ + return ERR_PTR(-ENXIO); +} +#endif + +#endif /* __RZG2L_DU_VSP_H__ */ From patchwork Fri Jun 14 10:13:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13698512 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 438CFC2BA16 for ; Fri, 14 Jun 2024 10:13:38 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.8281.1718360006029977314 for ; Fri, 14 Jun 2024 03:13:38 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.08,237,1712588400"; d="scan'208";a="211895923" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Jun 2024 19:13:37 +0900 Received: from localhost.localdomain (unknown [10.226.92.95]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id D8C63428BB2F; Fri, 14 Jun 2024 19:13:35 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 5.10.y-cip 10/14] arm64: dts: renesas: r9a07g044: Add DU node Date: Fri, 14 Jun 2024 11:13:04 +0100 Message-Id: <20240614101308.40407-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> References: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 14 Jun 2024 10:13:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16243 commit 4b15a38590f66da7e238a919242b69a235a261ec upstream. Add DU node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240222132117.137729-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 1ec12470c171..6049e4f754fa 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -740,6 +740,33 @@ fcpvd: fcp@10880000 { resets = <&cpg R9A07G044_LCDC_RESET_N>; }; + du: display@10890000 { + compatible = "renesas,r9a07g044-du"; + reg = <0 0x10890000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>; From patchwork Fri Jun 14 10:13:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13698517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46807C41513 for ; Fri, 14 Jun 2024 10:13:48 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.8281.1718360006029977314 for ; Fri, 14 Jun 2024 03:13:40 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.08,237,1712588400"; d="scan'208";a="211895928" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Jun 2024 19:13:39 +0900 Received: from localhost.localdomain (unknown [10.226.92.95]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 3E9C5428BB2E; Fri, 14 Jun 2024 19:13:37 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 5.10.y-cip 11/14] arm64: dts: renesas: r9a07g054: Add DU node Date: Fri, 14 Jun 2024 11:13:05 +0100 Message-Id: <20240614101308.40407-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> References: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 14 Jun 2024 10:13:48 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16244 commit c1a046466f43e06afc438e22ffc8e72faca85bdc upstream. Add DU node to RZ/V2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240222132117.137729-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index ea1aba78335d..171b4032d58d 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -746,6 +746,34 @@ fcpvd: fcp@10880000 { resets = <&cpg R9A07G054_LCDC_RESET_N>; }; + du: display@10890000 { + compatible = "renesas,r9a07g054-du", + "renesas,r9a07g044-du"; + reg = <0 0x10890000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_LCDC_RESET_N>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g054-cpg"; reg = <0 0x11010000 0 0x10000>; From patchwork Fri Jun 14 10:13:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13698516 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AC59C27C6E for ; Fri, 14 Jun 2024 10:13:48 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.8057.1718360022965805988 for ; Fri, 14 Jun 2024 03:13:43 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.08,237,1712588400"; d="scan'208";a="207938201" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 14 Jun 2024 19:13:42 +0900 Received: from localhost.localdomain (unknown [10.226.92.95]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id A003F428BB2E; Fri, 14 Jun 2024 19:13:40 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 5.10.y-cip 12/14] Revert "arm64: dts: renesas: Drop ADV7535 IRQ" Date: Fri, 14 Jun 2024 11:13:06 +0100 Message-Id: <20240614101308.40407-13-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> References: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 14 Jun 2024 10:13:48 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16245 This reverts commit fdfe1fbf93bc6fe6ed2708f11c2613bef556fdeb. Now we have IRQ support available, so reverting the commit will enable the IRQ. Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 2 ++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index d705501e162b..37807f1bda4d 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -64,6 +64,8 @@ adv7535: hdmi@3d { compatible = "adi,adv7535"; reg = <0x3d>; + interrupt-parent = <&pinctrl>; + interrupts = ; clocks = <&osc1>; clock-names = "cec"; avdd-supply = <®_1p8v>; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 1412df9a5786..859bc8745e66 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -80,6 +80,8 @@ adv7535: hdmi@3d { compatible = "adi,adv7535"; reg = <0x3d>; + interrupt-parent = <&pinctrl>; + interrupts = ; clocks = <&osc1>; clock-names = "cec"; avdd-supply = <®_1p8v>; From patchwork Fri Jun 14 10:13:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13698515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 465FBC27C79 for ; Fri, 14 Jun 2024 10:13:48 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.8281.1718360006029977314 for ; Fri, 14 Jun 2024 03:13:45 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.08,237,1712588400"; d="scan'208";a="211895938" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Jun 2024 19:13:44 +0900 Received: from localhost.localdomain (unknown [10.226.92.95]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 0A4D8428BB32; Fri, 14 Jun 2024 19:13:42 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 5.10.y-cip 13/14] arm64: dts: renesas: rzg2l-smarc: Enable DU and link with DSI Date: Fri, 14 Jun 2024 11:13:07 +0100 Message-Id: <20240614101308.40407-14-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> References: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 14 Jun 2024 10:13:48 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16246 commit eaa5907bcc7611c7a07e994a69a905deca34a9b6 upstream. Enable DU and link with DSI on RZ/{G2L,G2LC,V2L} SMARC EVK. Move DSI port properties from board dtsi to SoC dtsi and then link with DU and after that enable DU on the board dtsi. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240222132117.137729-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 19 +++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 19 +++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 14 ++++---------- arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 14 ++++---------- 4 files changed, 46 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 6049e4f754fa..f05e27a90979 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -713,6 +713,22 @@ dsi: dsi@10850000 { reset-names = "rst", "arst", "prst"; power-domains = <&cpg>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + }; + }; }; vspd: vsp@10870000 { @@ -759,6 +775,9 @@ ports { port@0 { reg = <0>; + du_out_dsi: endpoint { + remote-endpoint = <&dsi0_in>; + }; }; port@1 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 171b4032d58d..994cc88e6e3e 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -718,6 +718,22 @@ dsi: dsi@10850000 { reset-names = "rst", "arst", "prst"; power-domains = <&cpg>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + }; + }; }; vspd: vsp@10870000 { @@ -766,6 +782,9 @@ ports { port@0 { reg = <0>; + du_out_dsi: endpoint { + remote-endpoint = <&dsi0_in>; + }; }; port@1 { diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 37807f1bda4d..887dffe14910 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -40,17 +40,7 @@ &dsi { status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - }; - }; - port@1 { - reg = <1>; dsi0_out: endpoint { data-lanes = <1 2 3 4>; remote-endpoint = <&adv7535_in>; @@ -59,6 +49,10 @@ dsi0_out: endpoint { }; }; +&du { + status = "okay"; +}; + &i2c1 { adv7535: hdmi@3d { compatible = "adi,adv7535"; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 859bc8745e66..f21508640b6e 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -56,17 +56,7 @@ &dsi { status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - }; - }; - port@1 { - reg = <1>; dsi0_out: endpoint { data-lanes = <1 2 3 4>; remote-endpoint = <&adv7535_in>; @@ -75,6 +65,10 @@ dsi0_out: endpoint { }; }; +&du { + status = "okay"; +}; + &i2c1 { adv7535: hdmi@3d { compatible = "adi,adv7535"; From patchwork Fri Jun 14 10:13:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13698518 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 771A5C2BA12 for ; Fri, 14 Jun 2024 10:13:48 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.8057.1718360022965805988 for ; Fri, 14 Jun 2024 03:13:47 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.08,237,1712588400"; d="scan'208";a="207938212" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 14 Jun 2024 19:13:47 +0900 Received: from localhost.localdomain (unknown [10.226.92.95]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 5DB81428BB34; Fri, 14 Jun 2024 19:13:45 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 5.10.y-cip 14/14] arm64: defconfig: Enable Renesas RZ/G2L display unit DRM driver Date: Fri, 14 Jun 2024 11:13:08 +0100 Message-Id: <20240614101308.40407-15-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> References: <20240614101308.40407-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 14 Jun 2024 10:13:48 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16247 commit 8ea517c014ad4956ab7536277dd3f89bfad39069 upstream. Enable the RZ/G2L display unit DRM drivers used on the RZ/{G2L,G2LC,V2L} SMARC EVK development boards. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240223123646.245655-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 25228f0a5c7b..a26ae513bb72 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -657,6 +657,7 @@ CONFIG_ROCKCHIP_INNO_HDMI=y CONFIG_DRM_RCAR_DU=m CONFIG_DRM_RCAR_DW_HDMI=m CONFIG_DRM_RZG2L_MIPI_DSI=m +CONFIG_DRM_RZG2L_DU=m CONFIG_DRM_SUN4I=m CONFIG_DRM_SUN6I_DSI=m CONFIG_DRM_SUN8I_DW_HDMI=m