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X-Microsoft-Antispam-Message-Info: byHQT34duPoKCajuIixAUuUEAHy9C8DcA/fIuHKwQuK4gmtb87Gze8AKfBoSYpidVU5JMkfgS1520kmPoghYNi1LaYsmJUNbyxCTP3Fq2eNX9oDSwl27cxmWBGUrWi7DOnPATbCMKMs3bY8O/947C3snxeQ0TogiMa7qwys1Yz4t/SzfcvQixBKfw6rER9v8GzC4V8Zd4xJTDXXSZaS1nSCFxpuxQTVeLqd7DXjFQVhLIOt+imzINNXk5QRAqORCOZ0M3MA4DLQ8kZdzzUpfBiumdrYHfuxqtt+7U6hu15VHgkn7ZpakgJsN9qqw/Iue/llRM34hxQltxdyb8wY+f9AVto3w6MSj95T9TSnOaKcFn5/Kz7I8oXTLC94HAH9rt+UFAHp35zshlF3sVsOqf46PHo/OLwB0BtnKXasdZAG0GHsTcrcpaTWfTT/FIQReVLwqs5OOOxtaV3qo043AMEqgGBMXYH01JGOQ/27DMeyG94+I05lNfB9MNf1DaWiKsKByvVroAOPQAbXoJNJk9ZcZ43666MJ/RS3mYQDsUC4afyjFk0VT7NXcR5WTyAHzjPkWE9hIBppRCnFz775eF/C4/F3jpsJ8Oa48LtTmqtBmJcbOavYEEXLK9HepEGb+DTxmLsWMQMPgJX3+KMA1MjWIwtMI8WgUlAFxJcn7KmT6PwuoiBpKymnzPxbVzXaenMIkRPhzApJqv8kSelqPABLTkLmw+PfjgjeCifJEvdZhXOhmxpBALSlV/VzkazcGW6dtQZBfBum2CN3vn28xyTZlP1ik9IdzljUwiHsaGnh8LIxGSr6kWbyPqDCh7JRPgxr/MtL6ACIZW5vUZq2q0yh5kLqEVLSti9I5pvdRFN+y2WmZgnd4E57hkrDhomndNL79U4vP7h/pf7Coiv6f1gkI+di+iAhrYwDPKqwGUdk8110BrSezK+JyiTAvYexn0m3njx9FyT45xgpifFuRDOFakk9OSxJA1A/Hj1HKkc/C4b8uzJFrs+D71upUT0tdy97qfjMXepVWlOz5RzOQyQgPIz+xZVilS6XpQ7H6fPAu9dnLFO2gLi2zHpj4orhB4d+a/Yv0s8BcodmvYftMiLRNo3HxWctUzPzejYhh1/3QjfOVHQqoPKHc8pj2znSyBZ7AbjLWOgBzQX8I6DNV3INacp/P/vzPxRYVNqdr+D+nlo12WuAIp+j3ARP1KzHxLbR9Vc5oHr3lXl3/7HIPngvPEw3ptmJ/AIH9ADDlBglw43GrspIhgA+RCYjp3UaS/CTBJAtSHOkMqKOxDOR9hrIVNvAPPo4qDyakwzNCqzEsyqA7LPoTU2alavPT0eXTOkkPrOJBuYgv4uQffwwvlMQ05mU7YEBVnFKKLK5e68lJjbIjIAd9D0BYC9Sy0oY5Kp/RGI0Pjjoo7gRogO2eFg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(376011)(82310400023)(1800799021)(36860700010);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 07:00:18.0842 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 65b5a677-807b-47ee-5ac6-08dc8e9b259b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003439.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5613 To enhance the debugging capability of the driver loading failure for broken CPPC ACPI tables, it can optimize the expression by moving the verification of `min_freq`, `nominal_freq`, and other dependency values to the `amd_pstate_init_freq()` function where they are initialized. If any of these values are incorrect, the `amd-pstate` driver will not be registered. By ensuring that these values are correct before they are used, it will facilitate the debugging process when encountering driver loading failures due to faulty CPPC ACPI tables from BIOS Signed-off-by: Perry Yuan Acked-by: Gautham R. Shenoy Acked-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 5bdcdd3ea163..d4d7b7cdc4eb 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -924,6 +924,24 @@ static int amd_pstate_init_freq(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->nominal_freq, nominal_freq); WRITE_ONCE(cpudata->max_freq, max_freq); + /** + * Below values need to be initialized correctly, otherwise driver will fail to load + * max_freq is calculated according to (nominal_freq * highest_perf)/nominal_perf + * lowest_nonlinear_freq is a value between [min_freq, nominal_freq] + * Check _CPC in ACPI table objects if any values are incorrect + */ + if (min_freq <= 0 || max_freq <= 0 || nominal_freq <= 0 || min_freq > max_freq) { + pr_err("min_freq(%d) or max_freq(%d) or nominal_freq(%d) value is incorrect\n", + min_freq, max_freq, nominal_freq * 1000); + return -EINVAL; + } + + if (lowest_nonlinear_freq <= min_freq || lowest_nonlinear_freq > nominal_freq * 1000) { + pr_err("lowest_nonlinear_freq(%d) value is out of range [min_freq(%d), nominal_freq(%d)]\n", + lowest_nonlinear_freq, min_freq, nominal_freq * 1000); + return -EINVAL; + } + return 0; } @@ -962,15 +980,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) max_freq = READ_ONCE(cpudata->max_freq); nominal_freq = READ_ONCE(cpudata->nominal_freq); - if (min_freq <= 0 || max_freq <= 0 || - nominal_freq <= 0 || min_freq > max_freq) { - dev_err(dev, - "min_freq(%d) or max_freq(%d) or nominal_freq (%d) value is incorrect, check _CPC in ACPI tables\n", - min_freq, max_freq, nominal_freq); - ret = -EINVAL; - goto free_cpudata1; - } - policy->cpuinfo.transition_latency = amd_pstate_get_transition_latency(policy->cpu); policy->transition_delay_us = amd_pstate_get_transition_delay_us(policy->cpu); @@ -1423,14 +1432,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) min_freq = READ_ONCE(cpudata->min_freq); max_freq = READ_ONCE(cpudata->max_freq); nominal_freq = READ_ONCE(cpudata->nominal_freq); - if (min_freq <= 0 || max_freq <= 0 || - nominal_freq <= 0 || min_freq > max_freq) { - dev_err(dev, - "min_freq(%d) or max_freq(%d) or nominal_freq(%d) value is incorrect, check _CPC in ACPI tables\n", - min_freq, max_freq, nominal_freq); - ret = -EINVAL; - goto free_cpudata1; - } policy->cpuinfo.min_freq = min_freq; policy->cpuinfo.max_freq = max_freq; From patchwork Mon Jun 17 06:59:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 13700209 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2058.outbound.protection.outlook.com [40.107.236.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13D79188CB6; Mon, 17 Jun 2024 07:00:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 17 Jun 2024 02:00:17 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v4 02/11] cpufreq: amd-pstate: remove unused variable nominal_freq Date: Mon, 17 Jun 2024 14:59:04 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343E:EE_|DM6PR12MB4403:EE_ X-MS-Office365-Filtering-Correlation-Id: b16d65a1-f0ef-4674-eb5d-08dc8e9b277d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|376011|82310400023|1800799021; X-Microsoft-Antispam-Message-Info: QExYB642lfv1qppoZtRgTOC5A+W/2Nledp7kDh9dzHGhSADNxHqZT2sBKOx4fm4Sxumg7tU9LkObnnuJSJMJrVJSJHUg0yYknaco7LD5+28d6U1lbK1Xp7ISnevmVDJ37GTl5gRJF0vrBCV9M27l3TrdUh/pQZkeQ5dG5hCu0VVQwSZiy+p4mh8ZTMe3ioJkmtkL//B+wo2ctRONXFWlNA6K3kP7Oji/PZsN8xYrJB9VqAVPcIm4e9OSinDOvmLW2lGmB6EraKOqLrGNw90svzP7Q98flvbwp1hvcQEgc6O0dEgsl52hyJsKXYj0rc6xYvMAfNYZqw95j4lWvPuDE0EXRBZihkJualqIUn3g8yxzJYnrMaaHEkIS6gUPKNYIbG68X+z4Nae5PSdEGwmd7ksg14oa1AtL9l7vkkKxTz/yzTqHqESkgymJtG2Ny89n7dp3KoK4Y3bTpVpDIoyc4oi2GUtM97T764rKet3ZxToE4+qFvSdDyUTtbv5YYeezplHD0fvw2blXseY36tdPk/SmaTJyO4lEaY5E/Z1YEXMJokfQiViM2Vvv+z3z54MJvj7m/gFfNe6+9KY7xeF2IamASIamuZM+YVbGyAQ+PbuB+aWjVaaRue42Nu9Z1IWZ6YqjtXxERV+Ojmd4DLvRAAtuJwapIHoXfdHI9Xp/ShZak07xzpGWpjeia4mLyVcUW7iEbEajlNTgRmygsMskCIzhvpghxV/+2X2vMX3hbwBPVF1ft7+JYqVgaxNzbCES2cwqLoP6fClagxhr7GLjGQUEw0b35HQ7msVZAa4gpCgJMH373kOZb7YK99/8fYptCwwIYEUKtflMgj3wB4mu+qjZlTUtSCzOOeCPiHadOOYzvBsq3JikG5xu0vMCLSN6GwotbNB94VFmAuglTALAAKzs5kz5b+f9mzQ2u/V+SZAUH4kdEVfe3ZnYa7jKf4N3ZWmby7hEF+IDXN89qxyBLGAgWmXs1lvkrVO3nj1qlGdZq4aAL+R5KEkp8mf5ITUZjSnDHLm2sPkVG14NHJ4J34IS9YugHp0u+d3Z/+mDvWYa17qcLDJCm9o2A4rzdaNhgFXf2Xb0eWc54mNGeQBQQvwFbbgE2cCLCdfJLXO+mkU051lSGYLhGu2JdH4RYoNN4T2mowXj+8aXh1H5C7kZvmEV5ftRQCKq38kXz3xMXF4wzVZTUN6aucw8svuPDKPAOJyGYdbvNvETUuhMkVl2ImsKae3FmbrxNQfCTPijb87i7vvMnmO72sCeOj9IRu2lhQDU7tnAp+hzR4DXYeoM8KKpJ7UKh51rr0u7UylI5PhW3OIgur9LewOEp0ZB1shy2Pl3ODr0fGeOp8+oLc7094+H2gTJB3qOG1sOl7aoXRg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(36860700010)(376011)(82310400023)(1800799021);DIR:OUT;SFP:1101; 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This variable was defined and assigned a value in the previous code, but it was not used in the subsequent code. Closes: https://lore.kernel.org/oe-kbuild-all/202405080431.BPU6Yg9s-lkp@intel.com/ Reported-by: kernel test robot Signed-off-by: Perry Yuan Reviewed-by: Gautham R. Shenoy Acked-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index d4d7b7cdc4eb..1ce063a22214 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -947,7 +947,7 @@ static int amd_pstate_init_freq(struct amd_cpudata *cpudata) static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { - int min_freq, max_freq, nominal_freq, ret; + int min_freq, max_freq, ret; struct device *dev; struct amd_cpudata *cpudata; @@ -978,7 +978,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) min_freq = READ_ONCE(cpudata->min_freq); max_freq = READ_ONCE(cpudata->max_freq); - nominal_freq = READ_ONCE(cpudata->nominal_freq); policy->cpuinfo.transition_latency = amd_pstate_get_transition_latency(policy->cpu); policy->transition_delay_us = amd_pstate_get_transition_delay_us(policy->cpu); @@ -1398,7 +1397,7 @@ static bool amd_pstate_acpi_pm_profile_undefined(void) static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) { - int min_freq, max_freq, nominal_freq, ret; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 07:00:24.7642 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a0ad955-ee54-4855-0350-08dc8e9b2999 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003440.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6279 Add CPU ID checking in case the driver attempt to load on systems where CPPC functionality is unavailable. And the warning message will not be shown if CPPC is not supported. It will also print debug message if the CPU has no CPPC support that helps to debug the driver loading failure issue. Reported-by: Paul Menzel Closes: https://lore.kernel.org/linux-pm/CYYPR12MB8655D32EA18574C9497E888A9C122@CYYPR12MB8655.namprd12.prod.outlook.com/T/#t Signed-off-by: Perry Yuan Reviewed-by: Gautham R. Shenoy Acked-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 1ce063a22214..76419762c04f 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1743,6 +1743,20 @@ static int __init amd_pstate_set_driver(int mode_idx) return -EINVAL; } +/** + * CPPC function is not supported for family ID 17H with model_ID ranging from 0x10 to 0x2F. + * show the debug message that helps to check if the CPU has CPPC support for loading issue. + */ +static bool amd_cppc_supported(void) +{ + if ((boot_cpu_data.x86 == 0x17) && (boot_cpu_data.x86_model < 0x30)) { + pr_debug_once("CPPC feature is not supported by the processor\n"); + return false; + } + + return true; +} + static int __init amd_pstate_init(void) { struct device *dev_root; @@ -1751,6 +1765,11 @@ static int __init amd_pstate_init(void) if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) return -ENODEV; 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Mon, 17 Jun 2024 07:00:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS2PEPF0000343F.mail.protection.outlook.com (10.167.18.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Mon, 17 Jun 2024 07:00:28 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 17 Jun 2024 02:00:24 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v4 04/11] cpufreq: amd-pstate: add debug message while CPPC is supported and disabled by SBIOS Date: Mon, 17 Jun 2024 14:59:06 +0800 Message-ID: <2f5dc55e0537b089e1f4d31914c0b5c5c12792ac.1718606975.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343F:EE_|IA1PR12MB8309:EE_ X-MS-Office365-Filtering-Correlation-Id: 3604f03a-38d4-4639-a1ff-08dc8e9b2ba4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|376011|82310400023|1800799021; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 07:00:28.1958 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3604f03a-38d4-4639-a1ff-08dc8e9b2ba4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8309 If CPPC feature is supported by the CPU however the CPUID flag bit is not set by SBIOS, the `amd_pstate` will be failed to load while system booting. So adding one more debug message to inform user to check the SBIOS setting, The change also can help maintainers to debug why amd_pstate driver failed to be loaded at system booting if the processor support CPPC. Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218686 Signed-off-by: Perry Yuan Reviewed-by: Gautham R. Shenoy Acked-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 76419762c04f..9aa220a0e3fe 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1749,11 +1749,37 @@ static int __init amd_pstate_set_driver(int mode_idx) */ static bool amd_cppc_supported(void) { + struct cpuinfo_x86 *c = &cpu_data(0); + bool warn = false; + if ((boot_cpu_data.x86 == 0x17) && (boot_cpu_data.x86_model < 0x30)) { pr_debug_once("CPPC feature is not supported by the processor\n"); return false; } + /* + * If the CPPC feature is disabled in the BIOS for processors that support MSR-based CPPC, + * the AMD Pstate driver may not function correctly. + * Check the CPPC flag and display a warning message if the platform supports CPPC. + * Note: below checking code will not abort the driver registeration process because of + * the code is added for debugging purposes. + */ + if (!cpu_feature_enabled(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_ZEN1) || cpu_feature_enabled(X86_FEATURE_ZEN2)) { + if (c->x86_model > 0x60 && c->x86_model < 0xaf) + warn = true; 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Mon, 17 Jun 2024 02:00:27 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v4 05/11] Documentation: PM: amd-pstate: add debugging section for driver loading failure Date: Mon, 17 Jun 2024 14:59:07 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003440:EE_|CY5PR12MB6527:EE_ X-MS-Office365-Filtering-Correlation-Id: f3121d03-f822-441b-fbe6-08dc8e9b2d9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|376011|1800799021|82310400023; X-Microsoft-Antispam-Message-Info: 1AuwBdwDPCH0Z6HZRvLr8GLNq+d7AqvhekpsYJd2crizASxmuBCXmclhR77DE/xvDnVXlbq2LjhvXfCWVu1jcxDD3qOh4Z0B92eA5mYzbxt0Y9CF7ZpptXmoV6XMvyCOTIrTP+UbSOscPp4lIYLq2Ohdt8Aub/W9if3qOlxXQNPcI/DYU1Z/hRF63zMm1dnI3g3CTL6I0/ypdrTW9pcmlhrqZcpvaIWAzw9sXCekQwuknTJ7UerdP/Ad/WT0XyVKN1GapZH8wPtzKy5KtWxW/iRX3bWSwU6xB+YMwjtlH0mCgYboJtqRJoXtTCIqI2F5FZ6hI5+Y+n37CKRvQVR2i+3mfETrH1pYHAR2kQbCWpmL9TeCSpyV581dycatnf2WyF1to+mvy6cWg9pe+JZNdhlDj76CNqwwj/rN6fz0H3SmZVIpfjvwYnHjmqLGvC8LJAQSLxpHoY0pQWbZ1g+Ydfo/odlVzYAz+fHmH5Pkpdy/vD7gWac9AUA4NCKtmCv/93flUXL8NVcfdRLhRiVK28lMdqvvS/lG9haT4svQjb69gZUXpSla9FhgdrFgrXQs8FoPPsH0ZD+nP/qSEZYs95cjxv16/N1BoEeJwxozFMKSw7ej/NE6c6ZEVKJbdP/EFSW3SRuNJ+kgN/bQ1v2SsX0QpGdRBHhzTg+QyOB00BHD/Ao2Jz5XjKzxG8BQ6kSuQf3RqAOievl/2hKscppak/JISLEObY3792QzJ3ke2k7je7XWJ0SeoXhd8WuL6npMl5F0/oXM03VHNxruYROYR6VklA8o+GoH7UxBi8JyX5vfDJNPGaA2AhcLBrxdxp+ZPH9RNonBcnjYY+QXsCbLFl8taykHlKYRocFi4uqUOemy8Z0s7z1CSkp5/pELlUfmlyd9hBST1xOapGR/QjFkR4QZTe44N0yxW+7HSsuZz4VIjT+fsTEEFZOvHmXAhoUqbaL3EktXYUiJ2yq02L4HjrsJFq5wha5DW6J1vcC+XYf6isWDX6MtUWMuHTPaaFbJAokm9EJrX3Susu8EANTx6zyH269MbT7xn2t1xy/z6uizGqpILCulqkbdTgWR6yq6OZe5Rt1eGepWNWDrk1KUzkmVAAcAIbnuAzzhZq4xmTIA70Ww5vTgBNwlYguY4HS+HeX4gJvRi2iESM9kk/9jzXoEB20xA2kZy6ofiNbD8iHlUMA2f6ggxgD/KHmuAO/UyoicWEHGO/QPJFzcS2fZvpXRoOYqitdr8mIQHvjK5LJTtg6LbSQ+8SQZKrFB+OgXvAx/BUuDUH8etnnTJkja03h3Fs9forJWNADPvlnaUl2yLvN8oKQInnf4pGNQLv5XOdF6+D5jB3y7BwQ0xfVDuffZ4O0EzvofNd28ddR+XXvbGb2yu1gA89nkRUZ6FXlcCRV6lQ/3UXX49qtC+wyKPg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(36860700010)(376011)(1800799021)(82310400023);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 07:00:31.5299 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f3121d03-f822-441b-fbe6-08dc8e9b2d9e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003440.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6527 To address issues with the loading of the amd-pstate driver on certain platforms, It needs to enable dynamic debugging to capture debug messages during the driver loading process. By adding "amd_pstate.dyndbg=+p cppc_acpi.dyndbg=+p debug amd_pstate=active" and loglevel to the kernel command line, then driver debug logging is enabled. Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1e0d101b020a..ceeb073c9ada 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -472,6 +472,20 @@ operations for the new ``amd-pstate`` module with this tool. :: Diagnostics and Tuning ======================= +Debugging AMD P-State Driver Loading Issues +------------------------------------------ + +If the amd-pstate driver fails to load, additional debug information +may be necessary. +To capture debug messages for issue analysis, users can add below parameter, +"amd_pstate.dyndbg=+p cppc_acpi.dyndbg=+p debug" +to the kernel command line. This will enable dynamic debugging and allow better +analysis and troubleshooting of the driver loading process. + +Please note that adding this parameter will only enable debug logging during the +driver loading phase and may affect system behavior. Use this option with caution +and only for debugging purposes. + Trace Events -------------- From patchwork Mon Jun 17 06:59:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 13700213 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2058.outbound.protection.outlook.com [40.107.236.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31F2E18FDCD; Mon, 17 Jun 2024 07:00:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.236.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718607642; cv=fail; b=AuR2Ce7/tMQLyOIukM7DSLgpeHCv+XV99W623B+xkj3U4PolhOUU6xSpzGVGV06d8s4iOsMF36iMDd9p1i32MmrsPyDP+lfJsIUVZ82D9KFfTGoE1s/J33EwaUFTHg5ISWpuVtEauP0ZuNxMY0BHK4jNKLAnZjWLwpaUiq9Cb+w= ARC-Message-Signature: i=2; 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Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan Reviewed-by: Gautham R. Shenoy --- Documentation/admin-guide/pm/amd-pstate.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index ceeb073c9ada..3e2d085a6999 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -406,7 +406,7 @@ control its functionality at the system level. They are located in the ``/sys/devices/system/cpu/amd_pstate/`` directory and affect all CPUs. ``status`` - Operation mode of the driver: "active", "passive" or "disable". + Operation mode of the driver: "active", "passive", "guided" or "disable". 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The switch to cpu_feature_enabled() ensures compatibility with the latest CPU feature detection mechanisms and improves code maintainability. Acked-by: Mario Limonciello Suggested-by: Borislav Petkov (AMD) Signed-off-by: Perry Yuan Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9aa220a0e3fe..cb750ef305fe 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -158,7 +158,7 @@ static int __init dmi_matched_7k62_bios_bug(const struct dmi_system_id *dmi) * broken BIOS lack of nominal_freq and lowest_freq capabilities * definition in ACPI tables */ - if (boot_cpu_has(X86_FEATURE_ZEN2)) { + if (cpu_feature_enabled(X86_FEATURE_ZEN2)) { quirks = dmi->driver_data; pr_info("Overriding nominal and lowest frequencies for %s\n", dmi->ident); return 1; @@ -200,7 +200,7 @@ static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) u64 epp; int ret; - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { if (!cppc_req_cached) { epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req_cached); @@ -253,7 +253,7 @@ static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp) int ret; struct cppc_perf_ctrls perf_ctrls; - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { u64 value = READ_ONCE(cpudata->cppc_req_cached); value &= ~GENMASK_ULL(31, 24); @@ -752,7 +752,7 @@ static int amd_pstate_get_highest_perf(int cpu, u32 *highest_perf) { int ret; - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { u64 cap1; ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); @@ -991,7 +991,7 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; - if (boot_cpu_has(X86_FEATURE_CPPC)) + if (cpu_feature_enabled(X86_FEATURE_CPPC)) policy->fast_switch_possible = true; ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], @@ -1224,7 +1224,7 @@ static int amd_pstate_change_mode_without_dvr_change(int mode) cppc_state = mode; - if (boot_cpu_has(X86_FEATURE_CPPC) || cppc_state == AMD_PSTATE_ACTIVE) + if (cpu_feature_enabled(X86_FEATURE_CPPC) || cppc_state == AMD_PSTATE_ACTIVE) return 0; for_each_present_cpu(cpu) { @@ -1453,7 +1453,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) else policy->policy = CPUFREQ_POLICY_POWERSAVE; - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); if (ret) return ret; @@ -1543,7 +1543,7 @@ static void amd_pstate_epp_update_limit(struct cpufreq_policy *policy) epp = 0; /* Set initial EPP value */ - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { value &= ~GENMASK_ULL(31, 24); value |= (u64)epp << 24; } @@ -1582,7 +1582,7 @@ static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) value = READ_ONCE(cpudata->cppc_req_cached); max_perf = READ_ONCE(cpudata->highest_perf); - if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (cpu_feature_enabled(X86_FEATURE_CPPC)) { wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); } else { perf_ctrls.max_perf = max_perf; @@ -1616,7 +1616,7 @@ static void amd_pstate_epp_offline(struct cpufreq_policy *policy) value = READ_ONCE(cpudata->cppc_req_cached); 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Mon, 17 Jun 2024 02:00:37 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v4 08/11] x86/cpufeatures: Add feature bits for AMD heterogeneous processor Date: Mon, 17 Jun 2024 14:59:10 +0800 Message-ID: <4416ff72ea5a33173b69561803f1578073baccae.1718606975.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343C:EE_|DS7PR12MB5813:EE_ X-MS-Office365-Filtering-Correlation-Id: b4a6d22f-252d-4bc4-6737-08dc8e9b3389 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|376011|1800799021|82310400023; X-Microsoft-Antispam-Message-Info: oCl6j6DBs2fGr+o320JkI7/BCy50t93gxRrw2PmAAsceiVffNcTRJQqDczSxds4pXJ8He1JbGGkUGWQH+P8d8V85lfdeJfjZGNZMYYd9wj9IvMvfAI1Zy7sWXd9gfK3JYZrUgRFWDOPIDMigXolKAHiAFskj4r5Pvj9k/5z/ZrCJ5OGFNp+hkEFHxj0TvcJOi7GCVnB8COtVody1zjCbye/9f6HA29QlbbudgrYFEkh/gV86nzrsX1IqJNtmCzb/X+q11lGiZYsxNHBDX78be2tBtMQ4ShJsNujC/pJv/R4Au4zBZEaP/BvgBQfoBeDQPt5PwuDR1PUcCPwzjr2gU9/XBmMji93aU4A9DIqpEoReIWcGnIWvHaKrX0B+8lFOTJ7jSMkZt9hLD13pjlj+ICilGNEX/bec+bbpDTO91HceawHkYi1Gf9XntLC6T2r2G3acs49KNZLZAs0nMZ82foYvcJNUqoaSMNYrHh16wqmN5Aka50voxS4hV8wULurA+wvT8l102/7VGS/wC2CxHfS7+CxEzX25xqPoonJBsq+CNOvrTgiU8a7tA0XObiG/BzjEBo+ExhZqSueiKlW4jhu/qwDn7Y8Xr9ZInIk3LftLsSBx7z5sE9KGs/04FENs3ttlsK3sKJKuvSjAdzq1iYpb1FqnS+lVrM3kNQcjRfgVFXxPz2NhqccY2gGI2gK8rmkj7o1Dx6bp/uQ8I8FxMWyp3RcPNmV2szS5gr+SJt32xmxrkAWW/UKB0AN/S9lNCmd6h25+YgKHHaBSvbRH7Hbu64enPOrNoEyEt76/PEjc6nid5ntrUjsa9wotThGVKwjd1d9w/S4vuRw2am1RRLMhshU1InhWU0UNHh1Ewm7s3+1HerrCbM5Bj/P97e4nSinA4q/w1a0prsJ3SwIvjfYhCjlYGca/9iBYq2f9PVE0/bdpx76Jti2DDhCIXOYokxvOzZbFmpN0kVy9eJhghMUf6JFkzt0nuFlgZKEjiJSP9GUTNc91s7SJrWt4cbS1DEPAXChxTqteEQR+kqO4aOiP4ct1rm4c2x6Nz57Qw6bWsZp//zzdW5YEQR3HS/a7XDNzN7a9z/YQhmR3UXkGb2g1lKqBvAw5jE8Eh/pJ5NePCnVp5LKWs6i9pKoWwV+33j3av9wBfNF3mqJ5FabDAgsLqsW8Mb/v0vJsKG0B3BrEKoE/zzDygSqvdjbzbrssZ2b+FHYGGx6qVMF0c4a9jDvvI5hbUtM8rGlnHWkUji/oB4pqmhXNPU8xZwJzsYtcyJZXfGRN+DYblkX1mIm0F/YEIoHF8hhuCZEZqwhPg4SIQztp96W6I3o6iEXnQiBZoTMVsCGQ53a8QSQDNr/nbutuHUxQhh0AhvNnYHdm9d/PUgbrwSgAKVbeeTC/yz3gyQANyYUYuc5ZSAMNZhonLg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(36860700010)(376011)(1800799021)(82310400023);DIR:OUT;SFP:1101; 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For better utilization of feature words and help to identify core type, X86_FEATURE_HETERO_CORE_TOPOLOGY is added as a few scattered feature bits. Reference: See the page 119 of PPR for AMD Family 19h Model 61h B1, docID 56713 Signed-off-by: Perry Yuan Nacked-by: Borislav Petkov (AMD) --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 6c128d463a14..eceaa0df0137 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -471,6 +471,7 @@ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* "" BHI_DIS_S HW control enabled */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */ #define X86_FEATURE_FAST_CPPC (21*32 + 5) /* "" AMD Fast CPPC */ +#define X86_FEATURE_HETERO_CORE_TOPOLOGY (21*32+ 6) /* "" Heterogeneous Core Topology */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index c84c30188fdf..6b3477503dd0 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -52,6 +52,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, + { X86_FEATURE_HETERO_CORE_TOPOLOGY, CPUID_EAX, 30, 0x80000026, 0 }, { 0, 0, 0, 0, 0 } }; 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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS2PEPF0000343E.mail.protection.outlook.com (10.167.18.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Mon, 17 Jun 2024 07:00:45 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 17 Jun 2024 02:00:41 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v4 09/11] cpufreq: amd-pstate: implement heterogeneous core topology for highest performance initialization Date: Mon, 17 Jun 2024 14:59:11 +0800 Message-ID: <7aad57a98b37fa5893d4fe602d3dcef5c3f755d5.1718606975.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343E:EE_|SA1PR12MB6848:EE_ X-MS-Office365-Filtering-Correlation-Id: 141439ab-084e-43db-0f0e-08dc8e9b35cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|1800799021|82310400023|376011; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 07:00:45.2471 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 141439ab-084e-43db-0f0e-08dc8e9b35cc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6848 Introduces an optimization to the AMD-Pstate driver by implementing a heterogeneous core topology for the initialization of the highest performance value while driver loading. The two core types supported are "performance" and "efficiency". Each core type has different highest performance and frequency values configured by the platform. The `amd_pstate` driver needs to identify the type of core to correctly set an appropriate highest perf value. X86_FEATURE_HETERO_CORE_TOPOLOGY is used to identify whether the processor support heterogeneous core type by reading CPUID leaf Fn_0x80000026_EAX and bit 30. if the bit is set as one, then amd_pstate driver will check EBX 30:28 bits to get the core type. Reference: See the page 119 of PPR for AMD Family 19h Model 61h B1, docID 56713 Signed-off-by: Perry Yuan --- arch/x86/include/asm/processor.h | 2 ++ arch/x86/kernel/cpu/amd.c | 19 ++++++++++++ drivers/cpufreq/amd-pstate.c | 53 ++++++++++++++++++++++++++++++-- 3 files changed, 71 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index cb4f6c513c48..223aa58e2d5c 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -694,10 +694,12 @@ static inline u32 per_cpu_l2c_id(unsigned int cpu) extern u32 amd_get_highest_perf(void); extern void amd_clear_divider(void); extern void amd_check_microcode(void); +extern int amd_get_this_core_type(void); #else static inline u32 amd_get_highest_perf(void) { return 0; } static inline void amd_clear_divider(void) { } static inline void amd_check_microcode(void) { } +static inline int amd_get_this_core_type(void) { return -1; } #endif extern unsigned long arch_align_stack(unsigned long sp); diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 44df3f11e731..62a4ef21ef79 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1231,3 +1231,22 @@ void noinstr amd_clear_divider(void) :: "a" (0), "d" (0), "r" (1)); } EXPORT_SYMBOL_GPL(amd_clear_divider); + +#define X86_CPU_TYPE_ID_SHIFT 28 + +/** + * amd_get_this_core_type - Get the type of this heterogeneous CPU + * + * Returns the CPU type [31:28] (i.e., performance or efficient) of + * a CPU in the processor. + * If the processor has no core type support, returns -1. + */ + +int amd_get_this_core_type(void) +{ + if (!cpu_feature_enabled(X86_FEATURE_HETERO_CORE_TOPOLOGY)) + return -1; + + return cpuid_ebx(0x80000026) >> X86_CPU_TYPE_ID_SHIFT; +} +EXPORT_SYMBOL_GPL(amd_get_this_core_type); diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index cb750ef305fe..cf68343219d1 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -52,8 +52,10 @@ #define AMD_PSTATE_TRANSITION_LATENCY 20000 #define AMD_PSTATE_TRANSITION_DELAY 1000 #define AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY 600 -#define CPPC_HIGHEST_PERF_PERFORMANCE 196 -#define CPPC_HIGHEST_PERF_DEFAULT 166 + +#define CPPC_HIGHEST_PERF_EFFICIENT 132 +#define CPPC_HIGHEST_PERF_PERFORMANCE 196 +#define CPPC_HIGHEST_PERF_DEFAULT 166 #define AMD_CPPC_EPP_PERFORMANCE 0x00 #define AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80 @@ -86,6 +88,14 @@ struct quirk_entry { u32 lowest_freq; }; +/* defined by CPUID_Fn80000026_EBX BIT [31:28] */ +enum amd_core_type { + CPU_CORE_TYPE_NO_HETERO_SUP = -1, + CPU_CORE_TYPE_PERFORMANCE = 0, + CPU_CORE_TYPE_EFFICIENCY = 1, + CPU_CORE_TYPE_UNDEFINED = 2, +}; + /* * TODO: We need more time to fine tune processors with shared memory solution * with community together. @@ -358,9 +368,27 @@ static inline int amd_pstate_enable(bool enable) return static_call(amd_pstate_enable)(enable); } +static void get_this_core_type(void *data) +{ + enum amd_core_type *cpu_type = data; + + *cpu_type = amd_get_this_core_type(); +} + +static enum amd_core_type amd_pstate_get_cpu_type(int cpu) +{ + enum amd_core_type cpu_type; + + smp_call_function_single(cpu, get_this_core_type, &cpu_type, 1); + + return cpu_type; +} + static u32 amd_pstate_highest_perf_set(struct amd_cpudata *cpudata) { struct cpuinfo_x86 *c = &cpu_data(0); + u32 highest_perf; + enum amd_core_type core_type; /* * For AMD CPUs with Family ID 19H and Model ID range 0x70 to 0x7f, @@ -370,7 +398,26 @@ static u32 amd_pstate_highest_perf_set(struct amd_cpudata *cpudata) if (c->x86 == 0x19 && (c->x86_model >= 0x70 && c->x86_model <= 0x7f)) return CPPC_HIGHEST_PERF_PERFORMANCE; - return CPPC_HIGHEST_PERF_DEFAULT; + core_type = amd_pstate_get_cpu_type(cpudata->cpu); + pr_debug("core_type %d found\n", core_type); + + switch (core_type) { + case CPU_CORE_TYPE_NO_HETERO_SUP: + highest_perf = CPPC_HIGHEST_PERF_DEFAULT; + break; + case CPU_CORE_TYPE_PERFORMANCE: + highest_perf = CPPC_HIGHEST_PERF_PERFORMANCE; + break; + case CPU_CORE_TYPE_EFFICIENCY: + highest_perf = CPPC_HIGHEST_PERF_EFFICIENT; + break; + default: + highest_perf = CPPC_HIGHEST_PERF_DEFAULT; + WARN_ONCE(true, "WARNING: Undefined core type found"); + break; + } + + return highest_perf; } static int pstate_init_perf(struct amd_cpudata *cpudata) From patchwork Mon Jun 17 06:59:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 13700217 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2087.outbound.protection.outlook.com [40.107.236.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCFA619049D; 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Mon, 17 Jun 2024 02:00:44 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v4 10/11] cpufreq: amd-pstate: auto-load pstate driver by default Date: Mon, 17 Jun 2024 14:59:12 +0800 Message-ID: <0a4699e224e1931c09d6ede2620d585382b7d168.1718606975.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003440:EE_|SJ0PR12MB5676:EE_ X-MS-Office365-Filtering-Correlation-Id: e7bf42f2-6f9b-4071-27a5-08dc8e9b376b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|376011|82310400023|1800799021|36860700010; X-Microsoft-Antispam-Message-Info: weIoQJ/IPF7sysBWwCPx3EtjzVBJov2FUwot+pVrv1qJhbmTz3MmbEntIVUmul1pxqW6S4gXJZOclTV0QbKKTqA8oVXLlNfdJ+MvRAdNk/Kq3nJcmfTgL3jXkZsOE9F+up4kPQ00nbgjvaiHtwMIaHwKSgI86DNoIc4tBnEKfY/4OtXZ0oY6FNdN0U36Q3ioi0v3eI9IlNYEc8b++iStyamzLkoJPT3fwV/sJVA7vvas8KfSNwTqnS1/tYD33dBjW9x381/cpdfAQhVtaU89x0gPIokn4ccePE8ShhORYF59NvPa2AGB0b7UobeE2mgVg8GfpfRawRvmYqEf1kyIa6Ye7yRIEM9dCTmlteozcBb9nd+kI+WfRfS8mIknFP8YSQD/Vg2fIX4xQhi80lg2Eniw5QbSR9UT6t8xyHOkihWn6hG6iWL9GhJNEcSXslXpXSgG5kojMktXas+vlcqS7NQswv+1Y2TrX3jzglxqIuvF9xM3xLIeflmswjqt9hA2Wlk2A64AZdB0NrQokF9mFihNXwWoWGPMrfrHoMTCwsINbA2rHe54aFD5TYKjgHIu2+zXMuYWwS8d8uKzqYKbPkUMxWekGuALvhSCOevLrhonK4uFSIWUrgUwgRMW1sPwby82i8vEURhgVPEyNEgSlqW+7efv4T1jC7j91w449d8Poqbf4Ic4HoPC4TKOWU1dTH0wHWDqduDgBeigJGKH5X5q4I+FJsigsCendBdKEo/abevPvguJxoA0JA+WnVimrfuSlybg081dZuJfHVsr2sNgOB45CBs2L8JR7pK2evvpATIbiLyJvxY1Rh//kkXQ+H6giNWPpV4Nk9ctbnTZNoQ/3FjrXSJz55ysdAjNmFtVFrMJxKUsE4XHck8JjiLOLwRJS4mzKq8aqJfSZVYC+QlvBAOwgiHdeBcqbfjYIts6ZcaaW6kucoT6X8jP6Yb1OveLAieBs73zYAEZ8yktapxR/7FJGAUPxDJ23DqZie4dzwVulZHgU0n29DruXWU8Ll7MbQOFdH8Mx+enmwV9O+pOCKYsXyHnLL68kpZQ5iaDU+P6C5snaJtFimzRPA0CWOCqp2Fo1yWt7YVaFTHT/0pbGctKN12XN7ro+HBujt6+BLbhvi8ydRuNu10XyLMNvd+JRe51xEBqRkqAyDxh/Lgyu56r5jmJov4GyZ0lZ936PEP3hPOnLOySZAKMwjX/FjO2lwYJmA90nZzbG0W5QPzkH/ACBp4Lq7BQECLkE9u5jSJyj2+BZYh9pI1w4FV/gfsS6kLzeNB2Lxsz2lE0vZbwtADK6sB2djjsU+XzdO+YHmFPvlsmThNoVyNw1b/06pYQAdal5n0UbuLY4ED6Z1T1NbrnOHB3kAgDTJjUj68= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(376011)(82310400023)(1800799021)(36860700010);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 07:00:47.9518 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7bf42f2-6f9b-4071-27a5-08dc8e9b376b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003440.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5676 If the `amd-pstate` driver is not loaded automatically by default, it is because the kernel command line parameter has not been added. To resolve this issue, it is necessary to call the `amd_pstate_set_driver()` function to enable the desired mode (passive/active/guided) before registering the driver instance. This ensures that the driver is loaded correctly without relying on the kernel command line parameter. When there is no parameter added to command line, Kernel config will provide the default mode to load. Meanwhle, user can add driver mode in command line which will override the kernel config default option. Reported-by: Andrei Amuraritei Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218705 Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index cf68343219d1..b48fd60cbc6d 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1857,8 +1857,13 @@ static int __init amd_pstate_init(void) /* check if this machine need CPPC quirks */ dmi_check_system(amd_pstate_quirks_table); - switch (cppc_state) { - case AMD_PSTATE_UNDEFINED: + /* + * determine the driver mode from the command line or kernel config. + * If no command line input is provided, cppc_state will be AMD_PSTATE_UNDEFINED. + * command line options will override the kernel config settings. + */ + + if (cppc_state == AMD_PSTATE_UNDEFINED) { /* Disable on the following configs by default: * 1. Undefined platforms * 2. Server platforms @@ -1870,15 +1875,20 @@ static int __init amd_pstate_init(void) pr_info("driver load is disabled, boot with specific mode to enable this\n"); return -ENODEV; } - ret = amd_pstate_set_driver(CONFIG_X86_AMD_PSTATE_DEFAULT_MODE); - if (ret) - return ret; - break; + /* get driver mode from kernel config option [1:4] */ + cppc_state = CONFIG_X86_AMD_PSTATE_DEFAULT_MODE; + } + + switch (cppc_state) { case AMD_PSTATE_DISABLE: + pr_info("driver load is disabled, boot with specific mode to enable this\n"); return -ENODEV; case AMD_PSTATE_PASSIVE: case AMD_PSTATE_ACTIVE: case AMD_PSTATE_GUIDED: + ret = amd_pstate_set_driver(cppc_state); + if (ret) + return ret; break; default: return -EINVAL; @@ -1899,7 +1909,7 @@ static int __init amd_pstate_init(void) /* enable amd pstate feature */ ret = amd_pstate_enable(true); if (ret) { - pr_err("failed to enable with return %d\n", ret); + pr_err("failed to enable driver mode(%d)\n", cppc_state); return ret; } From patchwork Mon Jun 17 06:59:13 2024 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS2PEPF0000343B.mail.protection.outlook.com (10.167.18.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Mon, 17 Jun 2024 07:00:51 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 17 Jun 2024 02:00:47 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v4 11/11] cpufreq: amd-pstate: enable shared memory type CPPC by default Date: Mon, 17 Jun 2024 14:59:13 +0800 Message-ID: <0700459b88b496963dd5914631eee753bcf0a560.1718606975.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343B:EE_|IA0PR12MB8893:EE_ X-MS-Office365-Filtering-Correlation-Id: 9ee39b2c-9313-4989-6676-08dc8e9b395d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|376011|1800799021|82310400023; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 07:00:51.2171 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ee39b2c-9313-4989-6676-08dc8e9b395d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8893 The amd-pstate-epp driver has been implemented and resolves the performance drop issue seen in passive mode. Users who enable the active mode driver will not experience a performance drop compared to the passive mode driver. Therefore, the EPP driver should be loaded by default at system boot. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index b48fd60cbc6d..eca2f7dcf7ce 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -96,15 +96,6 @@ enum amd_core_type { CPU_CORE_TYPE_UNDEFINED = 2, }; -/* - * TODO: We need more time to fine tune processors with shared memory solution - * with community together. - * - * There are some performance drops on the CPU benchmarks which reports from - * Suse. We are co-working with them to fine tune the shared memory solution. So - * we disable it by default to go acpi-cpufreq on these processors and add a - * module parameter to be able to enable it manually for debugging. - */ static struct cpufreq_driver *current_pstate_driver; static struct cpufreq_driver amd_pstate_driver; static struct cpufreq_driver amd_pstate_epp_driver; @@ -1867,11 +1858,9 @@ static int __init amd_pstate_init(void) /* Disable on the following configs by default: * 1. Undefined platforms * 2. Server platforms - * 3. Shared memory designs */ if (amd_pstate_acpi_pm_profile_undefined() || - amd_pstate_acpi_pm_profile_server() || - !cpu_feature_enabled(X86_FEATURE_CPPC)) { + amd_pstate_acpi_pm_profile_server()) { pr_info("driver load is disabled, boot with specific mode to enable this\n"); return -ENODEV; }