From patchwork Mon Jun 17 18:28:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Charkov X-Patchwork-Id: 13701249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 677CBC27C79 for ; Mon, 17 Jun 2024 18:29:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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Each of the CPU clusters (one for the little cores and two for the big cores) get a passive cooling trip point at 85C, which will trigger DVFS throttling of the respective cluster upon reaching a high temperature condition. All zones also have a critical trip point at 115C, which will trigger a reset. Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 147 ++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 629049f3dc16..574359279867 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { compatible = "rockchip,rk3588"; @@ -2368,6 +2369,152 @@ pwm15: pwm@febf0030 { status = "disabled"; }; + thermal_zones: thermal-zones { + /* sensor near the center of the SoC */ + package_thermal: package-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + /* sensor between A76 cores 0 and 1 */ + bigcore0_thermal: bigcore0-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 1>; + + trips { + bigcore0_alert: bigcore0-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + bigcore0_crit: bigcore0-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&bigcore0_alert>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor between A76 cores 2 and 3 */ + bigcore2_thermal: bigcore2-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 2>; + + trips { + bigcore2_alert: bigcore2-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + bigcore2_crit: bigcore2-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&bigcore2_alert>; + cooling-device = + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor between the four A55 cores */ + little_core_thermal: littlecore-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 3>; + + trips { + littlecore_alert: littlecore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + littlecore_crit: littlecore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&littlecore_alert>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor near the PD_CENTER power domain */ + center_thermal: center-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 4>; + + trips { + center_crit: center-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 5>; + + trips { + gpu_crit: gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 6>; + + trips { + npu_crit: npu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + tsadc: tsadc@fec00000 { compatible = "rockchip,rk3588-tsadc"; reg = <0x0 0xfec00000 0x0 0x400>; From patchwork Mon Jun 17 18:28:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Charkov X-Patchwork-Id: 13701250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33B21C2BA1A for ; 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Mon, 17 Jun 2024 11:29:31 -0700 (PDT) Received: from latitude-fedora.lan ([2001:8f8:183b:6864::d35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6f8a6e58bdsm115397666b.187.2024.06.17.11.29.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 11:29:31 -0700 (PDT) From: Alexey Charkov Date: Mon, 17 Jun 2024 22:28:52 +0400 Subject: [PATCH v5 2/8] arm64: dts: rockchip: enable thermal management on all RK3588 boards MIME-Version: 1.0 Message-Id: <20240617-rk-dts-additions-v5-2-c1f5f3267f1e@gmail.com> References: <20240617-rk-dts-additions-v5-0-c1f5f3267f1e@gmail.com> In-Reply-To: <20240617-rk-dts-additions-v5-0-c1f5f3267f1e@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , Viresh Kumar , Chen-Yu Tsai , Diederik de Haas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This enables the on-chip thermal monitoring sensor (TSADC) on all RK3588(s) boards that don't have it enabled yet. It provides temperature monitoring for the SoC and emergency thermal shutdowns, and is thus important to have in place before CPU DVFS is enabled, as high CPU operating performance points can overheat the chip quickly in the absence of thermal management. Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 4 ++++ 8 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts index 98c622b27647..c667704ba985 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -673,6 +673,10 @@ regulator-state-mem { }; }; +&tsadc { + status = "okay"; +}; + &u2phy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi index 709d348cf06b..03fd193be253 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -466,3 +466,7 @@ regulator-state-mem { }; }; }; + +&tsadc { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index 7be2190244ba..7c3696a3ad3a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -1131,6 +1131,10 @@ &sata0 { status = "okay"; }; +&tsadc { + status = "okay"; +}; + &u2phy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts index 009566d881f3..230e630820b4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts @@ -376,6 +376,10 @@ &sdmmc { status = "okay"; }; +&tsadc { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 4e2bf4eaef2b..afcc38a5bed8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -749,6 +749,10 @@ regulator-state-mem { }; }; +&tsadc { + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts index 9090c5c99f2a..d0021524e7f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts @@ -648,6 +648,10 @@ regulator-state-mem { }; }; +&tsadc { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index 6b9206ce4a03..77bcf0f6b028 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -601,6 +601,10 @@ regulator-state-mem { }; }; +&tsadc { + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index 8e2a07612d17..c671a61d3aef 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -697,6 +697,10 @@ regulator-state-mem { }; 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Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 574359279867..758aff5e040b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -2487,17 +2487,29 @@ center_crit: center-crit { }; gpu_thermal: gpu-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsadc 5>; trips { + gpu_alert: gpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; gpu_crit: gpu-crit { temperature = <115000>; hysteresis = <0>; type = "critical"; }; }; + cooling-maps { + map0 { + trip = <&gpu_alert>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; npu_thermal: npu-thermal { From patchwork Mon Jun 17 18:28:54 2024 Content-Type: text/plain; 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a=ed25519-sha256; t=1718648960; l=1732; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=x+wPPy/GT45CFx+KMeVvr+U8rd4Mn9UoMyfj4WLHlu0=; b=NJUPm95L+pz2C2VM8nrMIvvzzMyFYQ0HF7Hm/4dFduLIvCnrJxE+w1acYjyMZ7+punC5bsaWC DP9TpxoR6b5DYXVG3Vb5k7kv4TVEehg2rEy4zUHGPGml6l+Dzux0cOv X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240617_112941_088165_5467C189 X-CRM114-Status: GOOD ( 10.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This links the PWM fan on Radxa Rock 5B as an active cooling device managed automatically by the thermal subsystem, with a target SoC temperature of 65C and a minimum-spin interval from 55C to 65C to ensure airflow when the system gets warm Helped-by: Dragan Simic Reviewed-by: Dragan Simic Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 30 ++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index afcc38a5bed8..27dd95f92f33 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -52,7 +52,7 @@ led_rgb_b { fan: pwm-fan { compatible = "pwm-fan"; - cooling-levels = <0 95 145 195 255>; + cooling-levels = <0 120 150 180 210 240 255>; fan-supply = <&vcc5v0_sys>; pwms = <&pwm1 0 50000 0>; #cooling-cells = <2>; @@ -286,6 +286,34 @@ i2s0_8ch_p0_0: endpoint { }; }; +&package_thermal { + polling-delay = <1000>; + + trips { + package_fan0: package-fan0 { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + package_fan1: package-fan1 { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&package_fan0>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + map2 { + trip = <&package_fan1>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + &pcie2x1l0 { pinctrl-names = "default"; pinctrl-0 = <&pcie2_0_rst>; From patchwork Mon Jun 17 18:28:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Charkov X-Patchwork-Id: 13701253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35AACC27C79 for ; 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Mon, 17 Jun 2024 11:29:43 -0700 (PDT) Received: from latitude-fedora.lan ([2001:8f8:183b:6864::d35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6f8a6e58bdsm115397666b.187.2024.06.17.11.29.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 11:29:42 -0700 (PDT) From: Alexey Charkov Date: Mon, 17 Jun 2024 22:28:55 +0400 Subject: [PATCH v5 5/8] arm64: dts: rockchip: Add CPU/memory regulator coupling for RK3588 MIME-Version: 1.0 Message-Id: <20240617-rk-dts-additions-v5-5-c1f5f3267f1e@gmail.com> References: <20240617-rk-dts-additions-v5-0-c1f5f3267f1e@gmail.com> In-Reply-To: <20240617-rk-dts-additions-v5-0-c1f5f3267f1e@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , Viresh Kumar , Chen-Yu Tsai , Diederik de Haas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718648960; l=5927; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=Lw6cvt6e5TFSBzp/kko3I8KOLayecFMagWIlbMmvaMY=; b=QfA4GQWUTiwN1V7Ur5GD7HfKSzVBRXt2ENXTozT4AWKRGyFMO65b44VPlh7M5224KRGomKrcV mNfqhWvuQV0A8KZRhS8g0xLKAmrJjAr0Sin1g6LNQ3ywZ88nhRUBecG X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240617_112945_370439_C553489C X-CRM114-Status: GOOD ( 12.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org RK3588 chips allow for their CPU cores to be powered by a different supply vs. their corresponding memory interfaces, and two of the boards currently upstream do that (EVB1 and QuartzPro64). The voltage of the memory interface though has to match that of the CPU cores that use it, which downstream kernels achieve by the means of a custom cpufreq driver which adjusts both at the same time. It seems that regulator coupling is a more appropriate generic interface for it, so this patch introduces coupling to affected device trees to ensure that memory interface voltage is also updated whenever cpufreq switches between CPU OPPs. Note that other boards, such as Radxa Rock 5B, define both the CPU and memory interface regulators as aliases to the same DT node, so this doesn't apply there. Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 12 ++++++++++++ arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index 7c3696a3ad3a..00f660d50127 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -878,6 +878,8 @@ regulators { vdd_cpu_big1_s0: dcdc-reg1 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -890,6 +892,8 @@ regulator-state-mem { vdd_cpu_big0_s0: dcdc-reg2 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -902,6 +906,8 @@ regulator-state-mem { vdd_cpu_lit_s0: dcdc-reg3 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; @@ -926,6 +932,8 @@ regulator-state-mem { vdd_cpu_big1_mem_s0: dcdc-reg5 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -939,6 +947,8 @@ regulator-state-mem { vdd_cpu_big0_mem_s0: dcdc-reg6 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -963,6 +973,8 @@ regulator-state-mem { vdd_cpu_lit_mem_s0: dcdc-reg8 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts index b4f22d95ac0e..baeb08d665c7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts @@ -832,6 +832,8 @@ vdd_cpu_big1_s0: dcdc-reg1 { regulator-name = "vdd_cpu_big1_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -845,6 +847,8 @@ vdd_cpu_big0_s0: dcdc-reg2 { regulator-name = "vdd_cpu_big0_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -858,6 +862,8 @@ vdd_cpu_lit_s0: dcdc-reg3 { regulator-name = "vdd_cpu_lit_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; @@ -884,6 +890,8 @@ vdd_cpu_big1_mem_s0: dcdc-reg5 { regulator-name = "vdd_cpu_big1_mem_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -898,6 +906,8 @@ vdd_cpu_big0_mem_s0: dcdc-reg6 { regulator-name = "vdd_cpu_big0_mem_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -924,6 +934,8 @@ vdd_cpu_lit_mem_s0: dcdc-reg8 { regulator-name = "vdd_cpu_lit_mem_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; From patchwork Mon Jun 17 18:28:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Charkov X-Patchwork-Id: 13701255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08375C2BB85 for ; Mon, 17 Jun 2024 18:30:48 +0000 (UTC) DKIM-Signature: v=1; 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Mon, 17 Jun 2024 11:29:46 -0700 (PDT) From: Alexey Charkov Date: Mon, 17 Jun 2024 22:28:56 +0400 Subject: [PATCH v5 6/8] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588 MIME-Version: 1.0 Message-Id: <20240617-rk-dts-additions-v5-6-c1f5f3267f1e@gmail.com> References: <20240617-rk-dts-additions-v5-0-c1f5f3267f1e@gmail.com> In-Reply-To: <20240617-rk-dts-additions-v5-0-c1f5f3267f1e@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , Viresh Kumar , Chen-Yu Tsai , Diederik de Haas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718648960; l=6206; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=FnSNCV3/dY8Km0myfhW8fZDwqPdlrAVPS2pOSSMxu0E=; b=NSfEjqlSUm3OIowcgGHMo+o9tFxYS2NjNAH5PvVTjFVqj4xfZ8uqiB/bGBy4tNb42b3PJ/FMu tqeYJL5KUQWCA+VAI+O9+/OeQxYWSrwBRQu2I7U6D0CUG7O7elFsnjA X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240617_112949_820033_62F8B2C5 X-CRM114-Status: GOOD ( 17.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org By default the CPUs on RK3588 start up in a conservative performance mode. Add frequency and voltage mappings to the device tree to enable dynamic scaling via cpufreq. OPP values are adapted from Radxa's downstream kernel for Rock 5B [1], stripping them down to the minimum frequency and voltage combinations as expected by the generic upstream cpufreq-dt driver, and also dropping those OPPs that don't differ in voltage but only in frequency (keeping the top frequency OPP in each case). Note that this patch ignores voltage scaling for the CPU memory interface which the downstream kernel does through a custom cpufreq driver, and which is why the downstream version has two sets of voltage values for each OPP (the second one being meant for the memory interface supply regulator). This is done instead via regulator coupling between CPU and memory interface supplies on affected boards. This has been tested on Rock 5B with u-boot 2023.11 compiled from Collabora's integration tree [2] with binary bl31 and appears to be stable both under active cooling and passive cooling (with throttling) [1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi [2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 149 +++++++++++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 + 3 files changed, 151 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi new file mode 100644 index 000000000000..35bbc3c2134f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/ { + cluster0_opp_table: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <712500 712500 950000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <850000 850000 950000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <950000 950000 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + }; + + cluster2_opp_table: opp-table-cluster2 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + }; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_b2 { + operating-points-v2 = <&cluster2_opp_table>; +}; + +&cpu_b3 { + operating-points-v2 = <&cluster2_opp_table>; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp_table>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 0bbeee399a63..7462cc1e1007 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -5,3 +5,4 @@ */ #include "rk3588-extra.dtsi" +#include "rk3588-opp.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index a379269147c4..c7fecf8fe7ec 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -5,3 +5,4 @@ */ #include "rk3588-base.dtsi" +#include "rk3588-opp.dtsi" From patchwork Mon Jun 17 18:28:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Charkov X-Patchwork-Id: 13701254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C0E7C2BA1A for ; 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Mon, 17 Jun 2024 11:29:50 -0700 (PDT) Received: from latitude-fedora.lan ([2001:8f8:183b:6864::d35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6f8a6e58bdsm115397666b.187.2024.06.17.11.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 11:29:50 -0700 (PDT) From: Alexey Charkov Date: Mon, 17 Jun 2024 22:28:57 +0400 Subject: [PATCH v5 7/8] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588j MIME-Version: 1.0 Message-Id: <20240617-rk-dts-additions-v5-7-c1f5f3267f1e@gmail.com> References: <20240617-rk-dts-additions-v5-0-c1f5f3267f1e@gmail.com> In-Reply-To: <20240617-rk-dts-additions-v5-0-c1f5f3267f1e@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , Viresh Kumar , Chen-Yu Tsai , Diederik de Haas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718648960; l=3675; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=9usg1860HeLN2D86kwAGVsch0yxyMQiUOvKvhiX96F0=; b=7qkTQpuDo2mnr2AksYS5eW7EJtXMddKluUT3j2BIeU1VziywewZDKtSMHT8+bGsuRwNzNZAFz b/X7C7+JSK/DwNleZDa/3++SYYeZ4QAj5dZ6D+I/8RWiDgsuLhaJa81 X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240617_112953_656831_3AAE6B59 X-CRM114-Status: UNSURE ( 9.97 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org RK3588j is the 'industrial' variant of RK3588, and it uses a different set of OPPs both in terms of allowed frequencies and in terms of applicable voltages at each frequency setpoint. Add the OPPs that apply to RK3588j (and apparently RK3588m too) to enable dynamic CPU frequency scaling. OPP values are derived from Rockchip downstream sources [1] by taking only those OPPs which have the highest frequency for a given voltage level and dropping the rest (if they are included, the kernel complains at boot time about them being inefficient) [1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 108 ++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi index 0bbeee399a63..b7e69553857b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi @@ -5,3 +5,111 @@ */ #include "rk3588-extra.dtsi" + +/ { + cluster0_opp_table: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <887500 887500 950000>; + clock-latency-ns = <40000>; + }; + opp-1704000000 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <937500 937500 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <950000 950000 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster2_opp_table: opp-table-cluster2 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <950000 950000 950000>; + clock-latency-ns = <40000>; + }; + }; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_b2 { + operating-points-v2 = <&cluster2_opp_table>; +}; + +&cpu_b3 { + operating-points-v2 = <&cluster2_opp_table>; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp_table>; 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a=ed25519-sha256; t=1718648960; l=5293; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=cu+UhDK5oOLgPtUwnbvA8VAbLQ3CEl/qKKmthR966F0=; b=Iq78YcGu6PRbj8M7jUOSV+GJvF6MJXQR89ZqGUZvfYky+6DBrijA5RY/wW0J84sIVnfWYtxCZ //IhTsdQgWkBA3n9buJjiMSdZhSv/EG5BXyaHQOAdqrE8yf/6UsUwqT X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240617_112956_085328_EDD27F77 X-CRM114-Status: GOOD ( 12.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org RK3588j uses a different set of OPPs for its GPU, both in terms of allowed frequencies and in terms of voltages. Move the GPU OPPs table into per-variant .dtsi files to accommodate for this difference. The table for RK3588j is adapted from Rockchip downstream sources [1], while RK3588 one is moved verbatim into the per-variant .dtsi file. The values provided for RK3588 in the downstream sources match those in the original commit. [1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi Fixes: 6fca4edb93d3 ("arm64: dts: rockchip: Add rk3588 GPU node") Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 38 ------------------------- arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 41 +++++++++++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 33 +++++++++++++++++++++ 3 files changed, 74 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 758aff5e040b..3d918874aa02 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -451,46 +451,8 @@ gpu: gpu@fb000000 { , ; interrupt-names = "job", "mmu", "gpu"; - operating-points-v2 = <&gpu_opp_table>; power-domains = <&power RK3588_PD_GPU>; status = "disabled"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <700000 700000 850000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <750000 750000 850000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <800000 800000 850000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <850000 850000 850000>; - }; - }; }; usb_host0_xhci: usb@fc000000 { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi index 35bbc3c2134f..0f1a77697351 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi @@ -114,6 +114,43 @@ opp-2400000000 { clock-latency-ns = <40000>; }; }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>; + }; + }; }; &cpu_b0 { @@ -147,3 +184,7 @@ &cpu_l2 { &cpu_l3 { operating-points-v2 = <&cluster0_opp_table>; }; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi index b7e69553857b..bce72bac4503 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi @@ -80,6 +80,35 @@ opp-2016000000 { clock-latency-ns = <40000>; }; }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-850000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <787500 787500 850000>; + }; + }; }; &cpu_b0 { @@ -113,3 +142,7 @@ &cpu_l2 { &cpu_l3 { operating-points-v2 = <&cluster0_opp_table>; }; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +};