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[73.37.105.206]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c4c468e5a6sm9518979a91.56.2024.06.17.15.29.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 15:29:28 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 1/5] drm/msm/adreno: Split up giant device table Date: Mon, 17 Jun 2024 15:28:59 -0700 Message-ID: <20240617222916.5980-2-robdclark@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240617222916.5980-1-robdclark@gmail.com> References: <20240617222916.5980-1-robdclark@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Rob Clark Split into a separate table per generation, in preparation to move each gen's device table to it's own file. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 67 +++++++++++++++++----- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 ++++ 2 files changed, 63 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index c3703a51287b..c8319706c5fe 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -20,7 +20,7 @@ bool allow_vram_carveout = false; MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU"); module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); -static const struct adreno_info gpulist[] = { +static const struct adreno_info a2xx_gpus[] = { { .chip_ids = ADRENO_CHIP_IDS(0x02000000), .family = ADRENO_2XX_GEN1, @@ -54,7 +54,12 @@ static const struct adreno_info gpulist[] = { .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a2xx_gpu_init, - }, { + } +}; +DECLARK_ADRENO_GPULIST(a2xx); + +static const struct adreno_info a3xx_gpus[] = { + { .chip_ids = ADRENO_CHIP_IDS(0x03000512), .family = ADRENO_3XX, .fw = { @@ -116,7 +121,12 @@ static const struct adreno_info gpulist[] = { .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, - }, { + } +}; +DECLARK_ADRENO_GPULIST(a3xx); + +static const struct adreno_info a4xx_gpus[] = { + { .chip_ids = ADRENO_CHIP_IDS(0x04000500), .family = ADRENO_4XX, .revn = 405, @@ -149,7 +159,12 @@ static const struct adreno_info gpulist[] = { .gmem = (SZ_1M + SZ_512K), .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a4xx_gpu_init, - }, { + } +}; +DECLARK_ADRENO_GPULIST(a4xx); + +static const struct adreno_info a5xx_gpus[] = { + { .chip_ids = ADRENO_CHIP_IDS(0x05000600), .family = ADRENO_5XX, .revn = 506, @@ -274,7 +289,12 @@ static const struct adreno_info gpulist[] = { .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, .init = a5xx_gpu_init, .zapfw = "a540_zap.mdt", - }, { + } +}; +DECLARK_ADRENO_GPULIST(a5xx); + +static const struct adreno_info a6xx_gpus[] = { + { .chip_ids = ADRENO_CHIP_IDS(0x06010000), .family = ADRENO_6XX_GEN1, .revn = 610, @@ -520,7 +540,12 @@ static const struct adreno_info gpulist[] = { .zapfw = "a690_zap.mdt", .hwcg = a690_hwcg, .address_space_size = SZ_16G, - }, { + } +}; +DECLARK_ADRENO_GPULIST(a6xx); + +static const struct adreno_info a7xx_gpus[] = { + { .chip_ids = ADRENO_CHIP_IDS(0x07000200), .family = ADRENO_6XX_GEN1, /* NOT a mistake! */ .fw = { @@ -582,7 +607,17 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "gen70900_zap.mbn", .address_space_size = SZ_16G, - }, + } +}; +DECLARK_ADRENO_GPULIST(a7xx); + +static const struct adreno_gpulist *gpulists[] = { + &a2xx_gpulist, + &a3xx_gpulist, + &a4xx_gpulist, + &a5xx_gpulist, + &a6xx_gpulist, + &a6xx_gpulist, }; MODULE_FIRMWARE("qcom/a300_pm4.fw"); @@ -617,13 +652,17 @@ MODULE_FIRMWARE("qcom/yamato_pm4.fw"); static const struct adreno_info *adreno_info(uint32_t chip_id) { /* identify gpu: */ - for (int i = 0; i < ARRAY_SIZE(gpulist); i++) { - const struct adreno_info *info = &gpulist[i]; - if (info->machine && !of_machine_is_compatible(info->machine)) - continue; - for (int j = 0; info->chip_ids[j]; j++) - if (info->chip_ids[j] == chip_id) - return info; + for (int i = 0; i < ARRAY_SIZE(gpulists); i++) { + for (int j = 0; j < gpulists[i]->gpus_count; j++) { + const struct adreno_info *info = &gpulists[i]->gpus[j]; + + if (info->machine && !of_machine_is_compatible(info->machine)) + continue; + + for (int k = 0; info->chip_ids[k]; k++) + if (info->chip_ids[k] == chip_id) + return info; + } } return NULL; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 77526892eb8c..7f20029d3876 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -114,6 +114,16 @@ struct adreno_info { #define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 } +struct adreno_gpulist { + const struct adreno_info *gpus; + unsigned gpus_count; +}; + +#define DECLARK_ADRENO_GPULIST(name) \ +const struct adreno_gpulist name ## _gpulist = { \ + name ## _gpus, ARRAY_SIZE(name ## _gpus) \ +} + /* * Helper to build a speedbin table, ie. the table: * fuse | speedbin From patchwork Mon Jun 17 22:29:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13701499 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD68BC27C79 for ; Mon, 17 Jun 2024 22:29:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 19A8B10E519; Mon, 17 Jun 2024 22:29:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="RTsBC8+h"; dkim-atps=neutral Received: from mail-oi1-f172.google.com (mail-oi1-f172.google.com [209.85.167.172]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8FDF110E519; Mon, 17 Jun 2024 22:29:36 +0000 (UTC) Received: by mail-oi1-f172.google.com with SMTP id 5614622812f47-3cabac56b38so2866007b6e.3; Mon, 17 Jun 2024 15:29:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1718663375; x=1719268175; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/5rmpi09MO9n2hy/qrINbjOvG6eB0hWRetNoJ98udSU=; b=RTsBC8+ht9XaERvqmNdXBCAc6QgIwceQe7ngP0lfVHFuEw78r13TWmn6/FvB5kddV4 jCFo6sldgt5RVoxlXzSRseNPz1ovN49gDAw9OtGBoRnvl/QTJock82I7GPFoMM3Ijk33 /BVT9r1l/VOrzMay8rigWFqwHk+kTlKoQJhJ2VPW5oNV34GzkYi8BiVyEfvC8YjIL9I8 JC+XxciMEaaGUyXGx0XC4ICZMl4I6/956Y03DvE3tBShJDDx3A3faett60gNPq4bCd+h qrz1nRA1AXDxgJ/LX8SWWGLpCGTDW1R2hycAEcI398KXntzsS47u/h/sNoJF85aK5Rsw seLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718663375; x=1719268175; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/5rmpi09MO9n2hy/qrINbjOvG6eB0hWRetNoJ98udSU=; b=AVQ3tgatVac24dXvJR9PnQfgDu8XI8I+sEDTcEgg+MbkvK7XjjL5ltpRriRMGcIclb 9hK3QpHy8Yp2X3CsTx7tYGQV4Djoo3afvDhFJGPUpD+7f7EPOiC85/L9mKhASGOjh2sG y+UlQmHImUlwvWHTNmf3mdASr2449tEWflwg6kAJ5/uIz2d49xqXG9XIjTMXbQ3vHARc UIV6Joyfi4xutgWZvMvgK54nwOAyYXcxy7rcoeva2kZxhB0SmD2QeO2rbCc98BO6VzWS iFqflZG3IHtHbL9qWCSsMizatNfckz1gYj2jsPqF45fpM2BF3yuhwSc08tpQhiYR0Jop DeBQ== X-Forwarded-Encrypted: i=1; AJvYcCWoxqV1RXa/Cvp9M9kc9pW4qPqbghu4qUnnUz/TIWM/8u8bHJfg+kiifypSUEdc0uJJuDSFUb9ZrGXTGl8zrFNkBcWi0/HJnmu33X4I8PeG X-Gm-Message-State: AOJu0Ywoj0+6L1SB+/RC/gU3rWMZvSeO10sPGg6tJ2lVo6Bjn5zOy7dt a1ewzvB3F/FibPNZ+lnxvghn1jFXHZQr5OnyOZl3UEzFLmNg57Ww8tqpnw== X-Google-Smtp-Source: AGHT+IFT2uECiKt8e8yRM5EdmVrXYFyF3Xnbtdzl8cWcq7imB26pKamwwoH8Td+EIdlcZUpsTCv7IQ== X-Received: by 2002:a05:6870:9589:b0:254:e4a0:4d89 with SMTP id 586e51a60fabf-25842882a43mr12075795fac.10.1718663374449; Mon, 17 Jun 2024 15:29:34 -0700 (PDT) Received: from localhost (c-73-37-105-206.hsd1.or.comcast.net. [73.37.105.206]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6fee2c40887sm5836284a12.67.2024.06.17.15.29.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 15:29:33 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Konrad Dybcio , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 2/5] drm/msm/adreno: Split catalog into separate files Date: Mon, 17 Jun 2024 15:29:00 -0700 Message-ID: <20240617222916.5980-3-robdclark@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240617222916.5980-1-robdclark@gmail.com> References: <20240617222916.5980-1-robdclark@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Rob Clark Split each gen's gpu table into it's own file. Only code-motion, no functional change. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/Makefile | 5 + drivers/gpu/drm/msm/adreno/a2xx_catalog.c | 52 ++ drivers/gpu/drm/msm/adreno/a3xx_catalog.c | 81 +++ drivers/gpu/drm/msm/adreno/a4xx_catalog.c | 50 ++ drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 148 +++++ drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 338 +++++++++++ drivers/gpu/drm/msm/adreno/adreno_device.c | 625 +-------------------- 7 files changed, 680 insertions(+), 619 deletions(-) create mode 100644 drivers/gpu/drm/msm/adreno/a2xx_catalog.c create mode 100644 drivers/gpu/drm/msm/adreno/a3xx_catalog.c create mode 100644 drivers/gpu/drm/msm/adreno/a4xx_catalog.c create mode 100644 drivers/gpu/drm/msm/adreno/a5xx_catalog.c create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_catalog.c diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index eb788921ff4f..f5e2838c6a76 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -8,13 +8,18 @@ ccflags-$(CONFIG_DRM_MSM_DP) += -I $(src)/dp adreno-y := \ adreno/adreno_device.o \ adreno/adreno_gpu.o \ + adreno/a2xx_catalog.o \ adreno/a2xx_gpu.o \ adreno/a2xx_gpummu.o \ + adreno/a3xx_catalog.o \ adreno/a3xx_gpu.o \ + adreno/a4xx_catalog.o \ adreno/a4xx_gpu.o \ + adreno/a5xx_catalog.o \ adreno/a5xx_gpu.o \ adreno/a5xx_power.o \ adreno/a5xx_preempt.o \ + adreno/a6xx_catalog.o \ adreno/a6xx_gpu.o \ adreno/a6xx_gmu.o \ adreno/a6xx_hfi.o \ diff --git a/drivers/gpu/drm/msm/adreno/a2xx_catalog.c b/drivers/gpu/drm/msm/adreno/a2xx_catalog.c new file mode 100644 index 000000000000..5c6afd1291ba --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a2xx_catalog.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2014 Red Hat + * Author: Rob Clark + * + * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. + */ + +#include "adreno_gpu.h" + +static const struct adreno_info a2xx_gpus[] = { + { + .chip_ids = ADRENO_CHIP_IDS(0x02000000), + .family = ADRENO_2XX_GEN1, + .revn = 200, + .fw = { + [ADRENO_FW_PM4] = "yamato_pm4.fw", + [ADRENO_FW_PFP] = "yamato_pfp.fw", + }, + .gmem = SZ_256K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a2xx_gpu_init, + }, { /* a200 on i.mx51 has only 128kib gmem */ + .chip_ids = ADRENO_CHIP_IDS(0x02000001), + .family = ADRENO_2XX_GEN1, + .revn = 201, + .fw = { + [ADRENO_FW_PM4] = "yamato_pm4.fw", + [ADRENO_FW_PFP] = "yamato_pfp.fw", + }, + .gmem = SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a2xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x02020000), + .family = ADRENO_2XX_GEN2, + .revn = 220, + .fw = { + [ADRENO_FW_PM4] = "leia_pm4_470.fw", + [ADRENO_FW_PFP] = "leia_pfp_470.fw", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a2xx_gpu_init, + } +}; +DECLARK_ADRENO_GPULIST(a2xx); + +MODULE_FIRMWARE("qcom/leia_pfp_470.fw"); +MODULE_FIRMWARE("qcom/leia_pm4_470.fw"); +MODULE_FIRMWARE("qcom/yamato_pfp.fw"); +MODULE_FIRMWARE("qcom/yamato_pm4.fw"); diff --git a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c new file mode 100644 index 000000000000..7962ce0f3516 --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2014 Red Hat + * Author: Rob Clark + * + * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. + */ + +#include "adreno_gpu.h" + +static const struct adreno_info a3xx_gpus[] = { + { + .chip_ids = ADRENO_CHIP_IDS(0x03000512), + .family = ADRENO_3XX, + .fw = { + [ADRENO_FW_PM4] = "a330_pm4.fw", + [ADRENO_FW_PFP] = "a330_pfp.fw", + }, + .gmem = SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a3xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x03000520), + .family = ADRENO_3XX, + .revn = 305, + .fw = { + [ADRENO_FW_PM4] = "a300_pm4.fw", + [ADRENO_FW_PFP] = "a300_pfp.fw", + }, + .gmem = SZ_256K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a3xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x03000600), + .family = ADRENO_3XX, + .revn = 307, /* because a305c is revn==306 */ + .fw = { + [ADRENO_FW_PM4] = "a300_pm4.fw", + [ADRENO_FW_PFP] = "a300_pfp.fw", + }, + .gmem = SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a3xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS( + 0x03020000, + 0x03020001, + 0x03020002 + ), + .family = ADRENO_3XX, + .revn = 320, + .fw = { + [ADRENO_FW_PM4] = "a300_pm4.fw", + [ADRENO_FW_PFP] = "a300_pfp.fw", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a3xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS( + 0x03030000, + 0x03030001, + 0x03030002 + ), + .family = ADRENO_3XX, + .revn = 330, + .fw = { + [ADRENO_FW_PM4] = "a330_pm4.fw", + [ADRENO_FW_PFP] = "a330_pfp.fw", + }, + .gmem = SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a3xx_gpu_init, + } +}; +DECLARK_ADRENO_GPULIST(a3xx); + +MODULE_FIRMWARE("qcom/a300_pm4.fw"); +MODULE_FIRMWARE("qcom/a300_pfp.fw"); +MODULE_FIRMWARE("qcom/a330_pm4.fw"); +MODULE_FIRMWARE("qcom/a330_pfp.fw"); diff --git a/drivers/gpu/drm/msm/adreno/a4xx_catalog.c b/drivers/gpu/drm/msm/adreno/a4xx_catalog.c new file mode 100644 index 000000000000..11fe8dcb22bf --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a4xx_catalog.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2014 Red Hat + * Author: Rob Clark + * + * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. + */ + +#include "adreno_gpu.h" + +static const struct adreno_info a4xx_gpus[] = { + { + .chip_ids = ADRENO_CHIP_IDS(0x04000500), + .family = ADRENO_4XX, + .revn = 405, + .fw = { + [ADRENO_FW_PM4] = "a420_pm4.fw", + [ADRENO_FW_PFP] = "a420_pfp.fw", + }, + .gmem = SZ_256K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a4xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x04020000), + .family = ADRENO_4XX, + .revn = 420, + .fw = { + [ADRENO_FW_PM4] = "a420_pm4.fw", + [ADRENO_FW_PFP] = "a420_pfp.fw", + }, + .gmem = (SZ_1M + SZ_512K), + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a4xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x04030002), + .family = ADRENO_4XX, + .revn = 430, + .fw = { + [ADRENO_FW_PM4] = "a420_pm4.fw", + [ADRENO_FW_PFP] = "a420_pfp.fw", + }, + .gmem = (SZ_1M + SZ_512K), + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a4xx_gpu_init, + } +}; +DECLARK_ADRENO_GPULIST(a4xx); + +MODULE_FIRMWARE("qcom/a420_pm4.fw"); +MODULE_FIRMWARE("qcom/a420_pfp.fw"); diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c new file mode 100644 index 000000000000..0b34d834f3c3 --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2014 Red Hat + * Author: Rob Clark + * + * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. + */ + +#include "adreno_gpu.h" + +static const struct adreno_info a5xx_gpus[] = { + { + .chip_ids = ADRENO_CHIP_IDS(0x05000600), + .family = ADRENO_5XX, + .revn = 506, + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = (SZ_128K + SZ_8K), + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | + ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + .zapfw = "a506_zap.mdt", + }, { + .chip_ids = ADRENO_CHIP_IDS(0x05000800), + .family = ADRENO_5XX, + .revn = 508, + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = (SZ_128K + SZ_8K), + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + .zapfw = "a508_zap.mdt", + }, { + .chip_ids = ADRENO_CHIP_IDS(0x05000900), + .family = ADRENO_5XX, + .revn = 509, + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = (SZ_256K + SZ_16K), + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + /* Adreno 509 uses the same ZAP as 512 */ + .zapfw = "a512_zap.mdt", + }, { + .chip_ids = ADRENO_CHIP_IDS(0x05010000), + .family = ADRENO_5XX, + .revn = 510, + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = SZ_256K, + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .init = a5xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x05010200), + .family = ADRENO_5XX, + .revn = 512, + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = (SZ_256K + SZ_16K), + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + .zapfw = "a512_zap.mdt", + }, { + .chip_ids = ADRENO_CHIP_IDS( + 0x05030002, + 0x05030004 + ), + .family = ADRENO_5XX, + .revn = 530, + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2", + }, + .gmem = SZ_1M, + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | + ADRENO_QUIRK_FAULT_DETECT_MASK, + .init = a5xx_gpu_init, + .zapfw = "a530_zap.mdt", + }, { + .chip_ids = ADRENO_CHIP_IDS(0x05040001), + .family = ADRENO_5XX, + .revn = 540, + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + [ADRENO_FW_GPMU] = "a540_gpmu.fw2", + }, + .gmem = SZ_1M, + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + .zapfw = "a540_zap.mdt", + } +}; +DECLARK_ADRENO_GPULIST(a5xx); + +MODULE_FIRMWARE("qcom/a530_pm4.fw"); +MODULE_FIRMWARE("qcom/a530_pfp.fw"); +MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); +MODULE_FIRMWARE("qcom/a530_zap.mdt"); +MODULE_FIRMWARE("qcom/a530_zap.b00"); +MODULE_FIRMWARE("qcom/a530_zap.b01"); +MODULE_FIRMWARE("qcom/a530_zap.b02"); +MODULE_FIRMWARE("qcom/a540_gpmu.fw2"); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c new file mode 100644 index 000000000000..899fc5fb5184 --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2014 Red Hat + * Author: Rob Clark + * + * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. + */ + +#include "adreno_gpu.h" + +static const struct adreno_info a6xx_gpus[] = { + { + .chip_ids = ADRENO_CHIP_IDS(0x06010000), + .family = ADRENO_6XX_GEN1, + .revn = 610, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + }, + .gmem = (SZ_128K + SZ_4K), + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a610_zap.mdt", + .hwcg = a612_hwcg, + /* + * There are (at least) three SoCs implementing A610: SM6125 + * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does + * not have speedbinning, as only a single SKU exists and we + * don't support khaje upstream yet. Hence, this matching + * table is only valid for bengal. + */ + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 206, 1 }, + { 200, 2 }, + { 157, 3 }, + { 127, 4 }, + ), + }, { + .machine = "qcom,sm7150", + .chip_ids = ADRENO_CHIP_IDS(0x06010800), + .family = ADRENO_6XX_GEN1, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a630_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mbn", + .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 128, 1 }, + { 146, 2 }, + { 167, 3 }, + { 172, 4 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06010800), + .family = ADRENO_6XX_GEN1, + .revn = 618, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a630_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .init = a6xx_gpu_init, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 169, 1 }, + { 174, 2 }, + ), + }, { + .machine = "qcom,sm4350", + .chip_ids = ADRENO_CHIP_IDS(0x06010900), + .family = ADRENO_6XX_GEN1, + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 138, 1 }, + { 92, 2 }, + ), + }, { + .machine = "qcom,sm6375", + .chip_ids = ADRENO_CHIP_IDS(0x06010901), + .family = ADRENO_6XX_GEN1, + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 190, 1 }, + { 177, 2 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06010900), + .family = ADRENO_6XX_GEN1, + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 120, 4 }, + { 138, 3 }, + { 169, 2 }, + { 180, 1 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS( + 0x06030001, + 0x06030002 + ), + .family = ADRENO_6XX_GEN1, + .revn = 630, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a630_gmu.bin", + }, + .gmem = SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .init = a6xx_gpu_init, + .zapfw = "a630_zap.mdt", + .hwcg = a630_hwcg, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06040001), + .family = ADRENO_6XX_GEN2, + .revn = 640, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a640_gmu.bin", + }, + .gmem = SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .init = a6xx_gpu_init, + .zapfw = "a640_zap.mdt", + .hwcg = a640_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06050002), + .family = ADRENO_6XX_GEN3, + .revn = 650, + .fw = { + [ADRENO_FW_SQE] = "a650_sqe.fw", + [ADRENO_FW_GMU] = "a650_gmu.bin", + }, + .gmem = SZ_1M + SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a650_zap.mdt", + .hwcg = a650_hwcg, + .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */ + { 3, 2 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06060001), + .family = ADRENO_6XX_GEN4, + .revn = 660, + .fw = { + [ADRENO_FW_SQE] = "a660_sqe.fw", + [ADRENO_FW_GMU] = "a660_gmu.bin", + }, + .gmem = SZ_1M + SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a660_zap.mdt", + .hwcg = a660_hwcg, + .address_space_size = SZ_16G, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06030500), + .family = ADRENO_6XX_GEN4, + .fw = { + [ADRENO_FW_SQE] = "a660_sqe.fw", + [ADRENO_FW_GMU] = "a660_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a660_zap.mbn", + .hwcg = a660_hwcg, + .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 117, 0 }, + { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */ + { 190, 1 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06080001), + .family = ADRENO_6XX_GEN2, + .revn = 680, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a640_gmu.bin", + }, + .gmem = SZ_2M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .init = a6xx_gpu_init, + .zapfw = "a640_zap.mdt", + .hwcg = a640_hwcg, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06090000), + .family = ADRENO_6XX_GEN4, + .fw = { + [ADRENO_FW_SQE] = "a660_sqe.fw", + [ADRENO_FW_GMU] = "a660_gmu.bin", + }, + .gmem = SZ_4M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a690_zap.mdt", + .hwcg = a690_hwcg, + .address_space_size = SZ_16G, + } +}; +DECLARK_ADRENO_GPULIST(a6xx); + +MODULE_FIRMWARE("qcom/a615_zap.mbn"); +MODULE_FIRMWARE("qcom/a619_gmu.bin"); +MODULE_FIRMWARE("qcom/a630_sqe.fw"); +MODULE_FIRMWARE("qcom/a630_gmu.bin"); +MODULE_FIRMWARE("qcom/a630_zap.mbn"); +MODULE_FIRMWARE("qcom/a640_gmu.bin"); +MODULE_FIRMWARE("qcom/a650_gmu.bin"); +MODULE_FIRMWARE("qcom/a650_sqe.fw"); +MODULE_FIRMWARE("qcom/a660_gmu.bin"); +MODULE_FIRMWARE("qcom/a660_sqe.fw"); + +static const struct adreno_info a7xx_gpus[] = { + { + .chip_ids = ADRENO_CHIP_IDS(0x07000200), + .family = ADRENO_6XX_GEN1, /* NOT a mistake! */ + .fw = { + [ADRENO_FW_SQE] = "a702_sqe.fw", + }, + .gmem = SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a702_zap.mbn", + .hwcg = a702_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 236, 1 }, + { 178, 2 }, + { 142, 3 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x07030001), + .family = ADRENO_7XX_GEN1, + .fw = { + [ADRENO_FW_SQE] = "a730_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70000.bin", + }, + .gmem = SZ_2M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a730_zap.mdt", + .hwcg = a730_hwcg, + .address_space_size = SZ_16G, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ + .family = ADRENO_7XX_GEN2, + .fw = { + [ADRENO_FW_SQE] = "a740_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70200.bin", + }, + .gmem = 3 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a740_zap.mdt", + .hwcg = a740_hwcg, + .address_space_size = SZ_16G, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ + .family = ADRENO_7XX_GEN3, + .fw = { + [ADRENO_FW_SQE] = "gen70900_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70900.bin", + }, + .gmem = 3 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "gen70900_zap.mbn", + .address_space_size = SZ_16G, + } +}; +DECLARK_ADRENO_GPULIST(a7xx); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index c8319706c5fe..1e789ff6945e 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -20,596 +20,12 @@ bool allow_vram_carveout = false; MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU"); module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); -static const struct adreno_info a2xx_gpus[] = { - { - .chip_ids = ADRENO_CHIP_IDS(0x02000000), - .family = ADRENO_2XX_GEN1, - .revn = 200, - .fw = { - [ADRENO_FW_PM4] = "yamato_pm4.fw", - [ADRENO_FW_PFP] = "yamato_pfp.fw", - }, - .gmem = SZ_256K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a2xx_gpu_init, - }, { /* a200 on i.mx51 has only 128kib gmem */ - .chip_ids = ADRENO_CHIP_IDS(0x02000001), - .family = ADRENO_2XX_GEN1, - .revn = 201, - .fw = { - [ADRENO_FW_PM4] = "yamato_pm4.fw", - [ADRENO_FW_PFP] = "yamato_pfp.fw", - }, - .gmem = SZ_128K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a2xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x02020000), - .family = ADRENO_2XX_GEN2, - .revn = 220, - .fw = { - [ADRENO_FW_PM4] = "leia_pm4_470.fw", - [ADRENO_FW_PFP] = "leia_pfp_470.fw", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a2xx_gpu_init, - } -}; -DECLARK_ADRENO_GPULIST(a2xx); - -static const struct adreno_info a3xx_gpus[] = { - { - .chip_ids = ADRENO_CHIP_IDS(0x03000512), - .family = ADRENO_3XX, - .fw = { - [ADRENO_FW_PM4] = "a330_pm4.fw", - [ADRENO_FW_PFP] = "a330_pfp.fw", - }, - .gmem = SZ_128K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a3xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x03000520), - .family = ADRENO_3XX, - .revn = 305, - .fw = { - [ADRENO_FW_PM4] = "a300_pm4.fw", - [ADRENO_FW_PFP] = "a300_pfp.fw", - }, - .gmem = SZ_256K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a3xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x03000600), - .family = ADRENO_3XX, - .revn = 307, /* because a305c is revn==306 */ - .fw = { - [ADRENO_FW_PM4] = "a300_pm4.fw", - [ADRENO_FW_PFP] = "a300_pfp.fw", - }, - .gmem = SZ_128K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a3xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS( - 0x03020000, - 0x03020001, - 0x03020002 - ), - .family = ADRENO_3XX, - .revn = 320, - .fw = { - [ADRENO_FW_PM4] = "a300_pm4.fw", - [ADRENO_FW_PFP] = "a300_pfp.fw", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a3xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS( - 0x03030000, - 0x03030001, - 0x03030002 - ), - .family = ADRENO_3XX, - .revn = 330, - .fw = { - [ADRENO_FW_PM4] = "a330_pm4.fw", - [ADRENO_FW_PFP] = "a330_pfp.fw", - }, - .gmem = SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a3xx_gpu_init, - } -}; -DECLARK_ADRENO_GPULIST(a3xx); - -static const struct adreno_info a4xx_gpus[] = { - { - .chip_ids = ADRENO_CHIP_IDS(0x04000500), - .family = ADRENO_4XX, - .revn = 405, - .fw = { - [ADRENO_FW_PM4] = "a420_pm4.fw", - [ADRENO_FW_PFP] = "a420_pfp.fw", - }, - .gmem = SZ_256K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a4xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x04020000), - .family = ADRENO_4XX, - .revn = 420, - .fw = { - [ADRENO_FW_PM4] = "a420_pm4.fw", - [ADRENO_FW_PFP] = "a420_pfp.fw", - }, - .gmem = (SZ_1M + SZ_512K), - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a4xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x04030002), - .family = ADRENO_4XX, - .revn = 430, - .fw = { - [ADRENO_FW_PM4] = "a420_pm4.fw", - [ADRENO_FW_PFP] = "a420_pfp.fw", - }, - .gmem = (SZ_1M + SZ_512K), - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a4xx_gpu_init, - } -}; -DECLARK_ADRENO_GPULIST(a4xx); - -static const struct adreno_info a5xx_gpus[] = { - { - .chip_ids = ADRENO_CHIP_IDS(0x05000600), - .family = ADRENO_5XX, - .revn = 506, - .fw = { - [ADRENO_FW_PM4] = "a530_pm4.fw", - [ADRENO_FW_PFP] = "a530_pfp.fw", - }, - .gmem = (SZ_128K + SZ_8K), - /* - * Increase inactive period to 250 to avoid bouncing - * the GDSC which appears to make it grumpy - */ - .inactive_period = 250, - .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | - ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init = a5xx_gpu_init, - .zapfw = "a506_zap.mdt", - }, { - .chip_ids = ADRENO_CHIP_IDS(0x05000800), - .family = ADRENO_5XX, - .revn = 508, - .fw = { - [ADRENO_FW_PM4] = "a530_pm4.fw", - [ADRENO_FW_PFP] = "a530_pfp.fw", - }, - .gmem = (SZ_128K + SZ_8K), - /* - * Increase inactive period to 250 to avoid bouncing - * the GDSC which appears to make it grumpy - */ - .inactive_period = 250, - .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init = a5xx_gpu_init, - .zapfw = "a508_zap.mdt", - }, { - .chip_ids = ADRENO_CHIP_IDS(0x05000900), - .family = ADRENO_5XX, - .revn = 509, - .fw = { - [ADRENO_FW_PM4] = "a530_pm4.fw", - [ADRENO_FW_PFP] = "a530_pfp.fw", - }, - .gmem = (SZ_256K + SZ_16K), - /* - * Increase inactive period to 250 to avoid bouncing - * the GDSC which appears to make it grumpy - */ - .inactive_period = 250, - .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init = a5xx_gpu_init, - /* Adreno 509 uses the same ZAP as 512 */ - .zapfw = "a512_zap.mdt", - }, { - .chip_ids = ADRENO_CHIP_IDS(0x05010000), - .family = ADRENO_5XX, - .revn = 510, - .fw = { - [ADRENO_FW_PM4] = "a530_pm4.fw", - [ADRENO_FW_PFP] = "a530_pfp.fw", - }, - .gmem = SZ_256K, - /* - * Increase inactive period to 250 to avoid bouncing - * the GDSC which appears to make it grumpy - */ - .inactive_period = 250, - .init = a5xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x05010200), - .family = ADRENO_5XX, - .revn = 512, - .fw = { - [ADRENO_FW_PM4] = "a530_pm4.fw", - [ADRENO_FW_PFP] = "a530_pfp.fw", - }, - .gmem = (SZ_256K + SZ_16K), - /* - * Increase inactive period to 250 to avoid bouncing - * the GDSC which appears to make it grumpy - */ - .inactive_period = 250, - .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init = a5xx_gpu_init, - .zapfw = "a512_zap.mdt", - }, { - .chip_ids = ADRENO_CHIP_IDS( - 0x05030002, - 0x05030004 - ), - .family = ADRENO_5XX, - .revn = 530, - .fw = { - [ADRENO_FW_PM4] = "a530_pm4.fw", - [ADRENO_FW_PFP] = "a530_pfp.fw", - [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2", - }, - .gmem = SZ_1M, - /* - * Increase inactive period to 250 to avoid bouncing - * the GDSC which appears to make it grumpy - */ - .inactive_period = 250, - .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | - ADRENO_QUIRK_FAULT_DETECT_MASK, - .init = a5xx_gpu_init, - .zapfw = "a530_zap.mdt", - }, { - .chip_ids = ADRENO_CHIP_IDS(0x05040001), - .family = ADRENO_5XX, - .revn = 540, - .fw = { - [ADRENO_FW_PM4] = "a530_pm4.fw", - [ADRENO_FW_PFP] = "a530_pfp.fw", - [ADRENO_FW_GPMU] = "a540_gpmu.fw2", - }, - .gmem = SZ_1M, - /* - * Increase inactive period to 250 to avoid bouncing - * the GDSC which appears to make it grumpy - */ - .inactive_period = 250, - .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init = a5xx_gpu_init, - .zapfw = "a540_zap.mdt", - } -}; -DECLARK_ADRENO_GPULIST(a5xx); - -static const struct adreno_info a6xx_gpus[] = { - { - .chip_ids = ADRENO_CHIP_IDS(0x06010000), - .family = ADRENO_6XX_GEN1, - .revn = 610, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - }, - .gmem = (SZ_128K + SZ_4K), - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a6xx_gpu_init, - .zapfw = "a610_zap.mdt", - .hwcg = a612_hwcg, - /* - * There are (at least) three SoCs implementing A610: SM6125 - * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does - * not have speedbinning, as only a single SKU exists and we - * don't support khaje upstream yet. Hence, this matching - * table is only valid for bengal. - */ - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 206, 1 }, - { 200, 2 }, - { 157, 3 }, - { 127, 4 }, - ), - }, { - .machine = "qcom,sm7150", - .chip_ids = ADRENO_CHIP_IDS(0x06010800), - .family = ADRENO_6XX_GEN1, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a630_gmu.bin", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .zapfw = "a615_zap.mbn", - .hwcg = a615_hwcg, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 128, 1 }, - { 146, 2 }, - { 167, 3 }, - { 172, 4 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06010800), - .family = ADRENO_6XX_GEN1, - .revn = 618, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a630_gmu.bin", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 169, 1 }, - { 174, 2 }, - ), - }, { - .machine = "qcom,sm4350", - .chip_ids = ADRENO_CHIP_IDS(0x06010900), - .family = ADRENO_6XX_GEN1, - .revn = 619, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a619_gmu.bin", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a6xx_gpu_init, - .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 138, 1 }, - { 92, 2 }, - ), - }, { - .machine = "qcom,sm6375", - .chip_ids = ADRENO_CHIP_IDS(0x06010901), - .family = ADRENO_6XX_GEN1, - .revn = 619, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a619_gmu.bin", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a6xx_gpu_init, - .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 190, 1 }, - { 177, 2 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06010900), - .family = ADRENO_6XX_GEN1, - .revn = 619, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a619_gmu.bin", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 120, 4 }, - { 138, 3 }, - { 169, 2 }, - { 180, 1 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS( - 0x06030001, - 0x06030002 - ), - .family = ADRENO_6XX_GEN1, - .revn = 630, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a630_gmu.bin", - }, - .gmem = SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .zapfw = "a630_zap.mdt", - .hwcg = a630_hwcg, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06040001), - .family = ADRENO_6XX_GEN2, - .revn = 640, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a640_gmu.bin", - }, - .gmem = SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .zapfw = "a640_zap.mdt", - .hwcg = a640_hwcg, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 1, 1 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06050002), - .family = ADRENO_6XX_GEN3, - .revn = 650, - .fw = { - [ADRENO_FW_SQE] = "a650_sqe.fw", - [ADRENO_FW_GMU] = "a650_gmu.bin", - }, - .gmem = SZ_1M + SZ_128K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, - .init = a6xx_gpu_init, - .zapfw = "a650_zap.mdt", - .hwcg = a650_hwcg, - .address_space_size = SZ_16G, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 1, 1 }, - { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */ - { 3, 2 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06060001), - .family = ADRENO_6XX_GEN4, - .revn = 660, - .fw = { - [ADRENO_FW_SQE] = "a660_sqe.fw", - [ADRENO_FW_GMU] = "a660_gmu.bin", - }, - .gmem = SZ_1M + SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, - .init = a6xx_gpu_init, - .zapfw = "a660_zap.mdt", - .hwcg = a660_hwcg, - .address_space_size = SZ_16G, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06030500), - .family = ADRENO_6XX_GEN4, - .fw = { - [ADRENO_FW_SQE] = "a660_sqe.fw", - [ADRENO_FW_GMU] = "a660_gmu.bin", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, - .init = a6xx_gpu_init, - .zapfw = "a660_zap.mbn", - .hwcg = a660_hwcg, - .address_space_size = SZ_16G, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 117, 0 }, - { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */ - { 190, 1 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06080001), - .family = ADRENO_6XX_GEN2, - .revn = 680, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a640_gmu.bin", - }, - .gmem = SZ_2M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .zapfw = "a640_zap.mdt", - .hwcg = a640_hwcg, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06090000), - .family = ADRENO_6XX_GEN4, - .fw = { - [ADRENO_FW_SQE] = "a660_sqe.fw", - [ADRENO_FW_GMU] = "a660_gmu.bin", - }, - .gmem = SZ_4M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, - .init = a6xx_gpu_init, - .zapfw = "a690_zap.mdt", - .hwcg = a690_hwcg, - .address_space_size = SZ_16G, - } -}; -DECLARK_ADRENO_GPULIST(a6xx); - -static const struct adreno_info a7xx_gpus[] = { - { - .chip_ids = ADRENO_CHIP_IDS(0x07000200), - .family = ADRENO_6XX_GEN1, /* NOT a mistake! */ - .fw = { - [ADRENO_FW_SQE] = "a702_sqe.fw", - }, - .gmem = SZ_128K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, - .init = a6xx_gpu_init, - .zapfw = "a702_zap.mbn", - .hwcg = a702_hwcg, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 236, 1 }, - { 178, 2 }, - { 142, 3 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x07030001), - .family = ADRENO_7XX_GEN1, - .fw = { - [ADRENO_FW_SQE] = "a730_sqe.fw", - [ADRENO_FW_GMU] = "gmu_gen70000.bin", - }, - .gmem = SZ_2M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, - .init = a6xx_gpu_init, - .zapfw = "a730_zap.mdt", - .hwcg = a730_hwcg, - .address_space_size = SZ_16G, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ - .family = ADRENO_7XX_GEN2, - .fw = { - [ADRENO_FW_SQE] = "a740_sqe.fw", - [ADRENO_FW_GMU] = "gmu_gen70200.bin", - }, - .gmem = 3 * SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, - .init = a6xx_gpu_init, - .zapfw = "a740_zap.mdt", - .hwcg = a740_hwcg, - .address_space_size = SZ_16G, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ - .family = ADRENO_7XX_GEN3, - .fw = { - [ADRENO_FW_SQE] = "gen70900_sqe.fw", - [ADRENO_FW_GMU] = "gmu_gen70900.bin", - }, - .gmem = 3 * SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, - .init = a6xx_gpu_init, - .zapfw = "gen70900_zap.mbn", - .address_space_size = SZ_16G, - } -}; -DECLARK_ADRENO_GPULIST(a7xx); +extern const struct adreno_gpulist a2xx_gpulist; +extern const struct adreno_gpulist a3xx_gpulist; +extern const struct adreno_gpulist a4xx_gpulist; +extern const struct adreno_gpulist a5xx_gpulist; +extern const struct adreno_gpulist a6xx_gpulist; +extern const struct adreno_gpulist a7xx_gpulist; static const struct adreno_gpulist *gpulists[] = { &a2xx_gpulist, @@ -620,35 +36,6 @@ static const struct adreno_gpulist *gpulists[] = { &a6xx_gpulist, }; -MODULE_FIRMWARE("qcom/a300_pm4.fw"); -MODULE_FIRMWARE("qcom/a300_pfp.fw"); -MODULE_FIRMWARE("qcom/a330_pm4.fw"); -MODULE_FIRMWARE("qcom/a330_pfp.fw"); -MODULE_FIRMWARE("qcom/a420_pm4.fw"); -MODULE_FIRMWARE("qcom/a420_pfp.fw"); -MODULE_FIRMWARE("qcom/a530_pm4.fw"); -MODULE_FIRMWARE("qcom/a530_pfp.fw"); -MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); -MODULE_FIRMWARE("qcom/a530_zap.mdt"); -MODULE_FIRMWARE("qcom/a530_zap.b00"); -MODULE_FIRMWARE("qcom/a530_zap.b01"); -MODULE_FIRMWARE("qcom/a530_zap.b02"); -MODULE_FIRMWARE("qcom/a540_gpmu.fw2"); -MODULE_FIRMWARE("qcom/a615_zap.mbn"); -MODULE_FIRMWARE("qcom/a619_gmu.bin"); -MODULE_FIRMWARE("qcom/a630_sqe.fw"); -MODULE_FIRMWARE("qcom/a630_gmu.bin"); -MODULE_FIRMWARE("qcom/a630_zap.mbn"); -MODULE_FIRMWARE("qcom/a640_gmu.bin"); -MODULE_FIRMWARE("qcom/a650_gmu.bin"); -MODULE_FIRMWARE("qcom/a650_sqe.fw"); -MODULE_FIRMWARE("qcom/a660_gmu.bin"); -MODULE_FIRMWARE("qcom/a660_sqe.fw"); -MODULE_FIRMWARE("qcom/leia_pfp_470.fw"); -MODULE_FIRMWARE("qcom/leia_pm4_470.fw"); -MODULE_FIRMWARE("qcom/yamato_pfp.fw"); -MODULE_FIRMWARE("qcom/yamato_pm4.fw"); - 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[73.37.105.206]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855ee7feesm84209155ad.152.2024.06.17.15.29.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 15:29:36 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 3/5] drm/msm/adreno: Move hwcg regs to a6xx hw catalog Date: Mon, 17 Jun 2024 15:29:01 -0700 Message-ID: <20240617222916.5980-4-robdclark@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240617222916.5980-1-robdclark@gmail.com> References: <20240617222916.5980-1-robdclark@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Rob Clark Move the hwcg tables into the hw catalog. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 619 ++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 617 --------------------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 - 3 files changed, 619 insertions(+), 620 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 899fc5fb5184..b991d3646722 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -7,6 +7,451 @@ */ #include "adreno_gpu.h" +#include "a6xx.xml.h" +#include "a6xx_gmu.xml.h" + +static const struct adreno_reglist a612_hwcg[] = { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + +/* For a615 family (a615, a616, a618 and a619) */ +static const struct adreno_reglist a615_hwcg[] = { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + +static const struct adreno_reglist a630_hwcg[] = { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, + {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf}, + {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf}, + {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + +static const struct adreno_reglist a640_hwcg[] = { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + +static const struct adreno_reglist a650_hwcg[] = { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + +static const struct adreno_reglist a660_hwcg[] = { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + +static const struct adreno_reglist a690_hwcg[] = { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82}, + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200}, + {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111}, + {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555}, + {} +}; static const struct adreno_info a6xx_gpus[] = { { @@ -270,6 +715,180 @@ MODULE_FIRMWARE("qcom/a650_sqe.fw"); MODULE_FIRMWARE("qcom/a660_gmu.bin"); MODULE_FIRMWARE("qcom/a660_sqe.fw"); +static const struct adreno_reglist a702_hwcg[] = { + { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 }, + { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 }, + { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf }, + { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, + { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 }, + { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, + { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 }, + { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, + { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 }, + { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, + { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 }, + { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 }, + { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, + { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 }, + { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 }, + { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, + { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, + { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, + { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, + { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 }, + { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 }, + {} +}; + +static const struct adreno_reglist a730_hwcg[] = { + { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 }, + { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf }, + { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 }, + { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 }, + { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, + { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 }, + { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 }, + { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, + { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 }, + { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, + { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 }, + { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, + { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 }, + { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 }, + { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, + { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, + { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 }, + { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 }, + { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 }, + { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, + { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, + { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, + { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, + {}, +}; + +static const struct adreno_reglist a740_hwcg[] = { + { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 }, + { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf }, + { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 }, + { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 }, + { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, + { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 }, + { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 }, + { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 }, + { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, + { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 }, + { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, + { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 }, + { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, + { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 }, + { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 }, + { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, + { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, + { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, + { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 }, + { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 }, + { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 }, + { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, + { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, + { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, + { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, + {}, +}; + static const struct adreno_info a7xx_gpus[] = { { .chip_ids = ADRENO_CHIP_IDS(0x07000200), diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index d5da7dcc8a16..eea64ec1bfaa 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -394,623 +394,6 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) a6xx_flush(gpu, ring); } -const struct adreno_reglist a612_hwcg[] = { - {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, - {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081}, - {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, - {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, - {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, - {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, - {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222}, - {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, - {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, - {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, - {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, - {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, - {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, - {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, - {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, - {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, - {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, - {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, - {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, - {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, - {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, - {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, - {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, - {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, - {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, - {}, -}; - -/* For a615 family (a615, a616, a618 and a619) */ -const struct adreno_reglist a615_hwcg[] = { - {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, - {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, - {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, - {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, - {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, - {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, - {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, - {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, - {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, - {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, - {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, - {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, - {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, - {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020}, - {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, - {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, - {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, - {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, - {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00}, - {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00}, - {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00}, - {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, - {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, - {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, - {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, - {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, - {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, - {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, - {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, - {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, - {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, - {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, - {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, - {}, -}; - -const struct adreno_reglist a630_hwcg[] = { - {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220}, - {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, - {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, - {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, - {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, - {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, - {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, - {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, - {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, - {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf}, - {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf}, - {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf}, - {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, - {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, - {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222}, - {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, - {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, - {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222}, - {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222}, - {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, - {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, - {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777}, - {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777}, - {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, - {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, - {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111}, - {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111}, - {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, - {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, - {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, - {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, - {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, - {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, - {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, - {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, - {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00}, - {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00}, - {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00}, - {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, - {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, - {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, - {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, - {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, - {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, - {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, - {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, - {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, - {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, - {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, - {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, - {}, -}; - -const struct adreno_reglist a640_hwcg[] = { - {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, - {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, - {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, - {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, - {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, - {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, - {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, - {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, - {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, - {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, - {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, - {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, - {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, - {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, - {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, - {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, - {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, - {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, - {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, - {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, - {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, - {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, - {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, - {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, - {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, - {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, - {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, - {}, -}; - -const struct adreno_reglist a650_hwcg[] = { - {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, - {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, - {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, - {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, - {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, - {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, - {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, - {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, - {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, - {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, - {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, - {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, - {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, - {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, - {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, - {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, - {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, - {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, - {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, - {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, - {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777}, - {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, - {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, - {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, - {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, - {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, - {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, - {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, - {}, -}; - -const struct adreno_reglist a660_hwcg[] = { - {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, - {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, - {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, - {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, - {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, - {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, - {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, - {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, - {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, - {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, - {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, - {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, - {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, - {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, - {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, - {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, - {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, - {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, - {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, - {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, - {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, - {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, - {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, - {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, - {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, - {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, - {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, - {}, -}; - -const struct adreno_reglist a690_hwcg[] = { - {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, - {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, - {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, - {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, - {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, - {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, - {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, - {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, - {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, - {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, - {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, - {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, - {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, - {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, - {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, - {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, - {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, - {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, - {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, - {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, - {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, - {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, - {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, - {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, - {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, - {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, - {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, - {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82}, - {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, - {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, - {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, - {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, - {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, - {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, - {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200}, - {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111}, - {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555}, - {} -}; - -const struct adreno_reglist a702_hwcg[] = { - { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 }, - { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 }, - { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf }, - { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, - { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, - { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 }, - { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, - { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 }, - { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 }, - { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, - { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 }, - { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, - { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 }, - { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 }, - { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, - { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, - { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 }, - { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 }, - { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, - { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, - { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, - { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, - { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 }, - { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 }, - {} -}; - -const struct adreno_reglist a730_hwcg[] = { - { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 }, - { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf }, - { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 }, - { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 }, - { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, - { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, - { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 }, - { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 }, - { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 }, - { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, - { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 }, - { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 }, - { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, - { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 }, - { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, - { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 }, - { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 }, - { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, - { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 }, - { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, - { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 }, - { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 }, - { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 }, - { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, - { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, - { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, - { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, - {}, -}; - -const struct adreno_reglist a740_hwcg[] = { - { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 }, - { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf }, - { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 }, - { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 }, - { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, - { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, - { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, - { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, - { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 }, - { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 }, - { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 }, - { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 }, - { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, - { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 }, - { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 }, - { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 }, - { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, - { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 }, - { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, - { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 }, - { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 }, - { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, - { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, - { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, - { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 }, - { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 }, - { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 }, - { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 }, - { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, - { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, - { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, - { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, - { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, - { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, - {}, -}; - static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 7f20029d3876..a988f4ed4ea7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -77,9 +77,6 @@ struct adreno_reglist { u32 value; }; -extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[]; -extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a702_hwcg[], a730_hwcg[], a740_hwcg[]; - struct adreno_speedbin { uint16_t fuse; uint16_t speedbin; From patchwork Mon Jun 17 22:29:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13701500 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2305CC2BB85 for ; Mon, 17 Jun 2024 22:29:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1698110E51E; Mon, 17 Jun 2024 22:29:45 +0000 (UTC) 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[73.37.105.206]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855f17d5esm84090805ad.225.2024.06.17.15.29.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 15:29:39 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 4/5] drm/msm/adreno: Move hwcg table into a6xx specific info Date: Mon, 17 Jun 2024 15:29:02 -0700 Message-ID: <20240617222916.5980-5-robdclark@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240617222916.5980-1-robdclark@gmail.com> References: <20240617222916.5980-1-robdclark@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Rob Clark Introduce a6xx_info where we can stash gen specific stuff without polluting the toplevel adreno_info struct. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 65 +++++++++++++++++------ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +-- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++- 4 files changed, 67 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index b991d3646722..da49589f82d0 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -7,6 +7,7 @@ */ #include "adreno_gpu.h" +#include "a6xx_gpu.h" #include "a6xx.xml.h" #include "a6xx_gmu.xml.h" @@ -465,7 +466,9 @@ static const struct adreno_info a6xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a6xx_gpu_init, .zapfw = "a610_zap.mdt", - .hwcg = a612_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a612_hwcg, + }, /* * There are (at least) three SoCs implementing A610: SM6125 * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does @@ -493,7 +496,9 @@ static const struct adreno_info a6xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mbn", - .hwcg = a615_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a615_hwcg, + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 128, 1 }, @@ -513,6 +518,8 @@ static const struct adreno_info a6xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, + .a6xx = &(struct a6xx_info) { + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 169, 1 }, @@ -531,7 +538,9 @@ static const struct adreno_info a6xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a615_hwcg, + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 138, 1 }, @@ -550,7 +559,9 @@ static const struct adreno_info a6xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a615_hwcg, + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 190, 1 }, @@ -569,7 +580,9 @@ static const struct adreno_info a6xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a615_hwcg, + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 120, 4 }, @@ -593,7 +606,9 @@ static const struct adreno_info a6xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a630_zap.mdt", - .hwcg = a630_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a630_hwcg, + }, }, { .chip_ids = ADRENO_CHIP_IDS(0x06040001), .family = ADRENO_6XX_GEN2, @@ -607,7 +622,9 @@ static const struct adreno_info a6xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", - .hwcg = a640_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a640_hwcg, + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 1, 1 }, @@ -626,7 +643,9 @@ static const struct adreno_info a6xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", - .hwcg = a650_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a650_hwcg, + }, .address_space_size = SZ_16G, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -648,7 +667,9 @@ static const struct adreno_info a6xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", - .hwcg = a660_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a660_hwcg, + }, .address_space_size = SZ_16G, }, { .chip_ids = ADRENO_CHIP_IDS(0x06030500), @@ -663,7 +684,9 @@ static const struct adreno_info a6xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mbn", - .hwcg = a660_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a660_hwcg, + }, .address_space_size = SZ_16G, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -684,7 +707,9 @@ static const struct adreno_info a6xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", - .hwcg = a640_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a640_hwcg, + }, }, { .chip_ids = ADRENO_CHIP_IDS(0x06090000), .family = ADRENO_6XX_GEN4, @@ -698,7 +723,9 @@ static const struct adreno_info a6xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", - .hwcg = a690_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a690_hwcg, + }, .address_space_size = SZ_16G, } }; @@ -901,7 +928,9 @@ static const struct adreno_info a7xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a702_zap.mbn", - .hwcg = a702_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a702_hwcg, + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 236, 1 }, @@ -921,7 +950,9 @@ static const struct adreno_info a7xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a730_zap.mdt", - .hwcg = a730_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a730_hwcg, + }, .address_space_size = SZ_16G, }, { .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ @@ -936,7 +967,9 @@ static const struct adreno_info a7xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a740_zap.mdt", - .hwcg = a740_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a740_hwcg, + }, .address_space_size = SZ_16G, }, { .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ @@ -951,6 +984,8 @@ static const struct adreno_info a7xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "gen70900_zap.mbn", + .a6xx = &(struct a6xx_info) { + }, .address_space_size = SZ_16G, } }; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index eea64ec1bfaa..7e01fb551f12 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -403,7 +403,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) unsigned int i; u32 val, clock_cntl_on, cgc_mode; - if (!(adreno_gpu->info->hwcg || adreno_is_a7xx(adreno_gpu))) + if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu))) return; if (adreno_is_a630(adreno_gpu)) @@ -426,7 +426,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) state ? 0x5555 : 0); } - if (!adreno_gpu->info->hwcg) { + if (!adreno_gpu->info->a6xx->hwcg) { gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); @@ -455,7 +455,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); - for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) + for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); /* Enable SP clock */ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 0463a2006822..61c51e9c7f06 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -12,6 +12,15 @@ extern bool hang_debug; +/** + * struct a6xx_info - a6xx specific information from device table + * + * @hwcg: hw clock gating register sequence + */ +struct a6xx_info { + const struct adreno_reglist *hwcg; +}; + struct a6xx_gpu { struct adreno_gpu base; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index a988f4ed4ea7..849ce0ae9e75 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -82,6 +82,8 @@ struct adreno_speedbin { uint16_t speedbin; }; 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[73.37.105.206]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e6debasm83995155ad.65.2024.06.17.15.29.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 15:29:41 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 5/5] drm/msm/adreno: Move CP_PROTECT settings to hw catalog Date: Mon, 17 Jun 2024 15:29:03 -0700 Message-ID: <20240617222916.5980-6-robdclark@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240617222916.5980-1-robdclark@gmail.com> References: <20240617222916.5980-1-robdclark@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Rob Clark Move the CP_PROTECT settings into the hw catalog. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 247 +++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 257 +--------------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 + drivers/gpu/drm/msm/adreno/adreno_gpu.h | 13 ++ 4 files changed, 268 insertions(+), 251 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index da49589f82d0..89e7feffcbe3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -454,6 +454,173 @@ static const struct adreno_reglist a690_hwcg[] = { {} }; +/* For a615, a616, a618, a619, a630, a640 and a680 */ +static const u32 a630_protect_regs[] = { + A6XX_PROTECT_RDONLY(0x00000, 0x04ff), + A6XX_PROTECT_RDONLY(0x00501, 0x0005), + A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), + A6XX_PROTECT_NORDWR(0x0050e, 0x0000), + A6XX_PROTECT_NORDWR(0x00510, 0x0000), + A6XX_PROTECT_NORDWR(0x00534, 0x0000), + A6XX_PROTECT_NORDWR(0x00800, 0x0082), + A6XX_PROTECT_NORDWR(0x008a0, 0x0008), + A6XX_PROTECT_NORDWR(0x008ab, 0x0024), + A6XX_PROTECT_RDONLY(0x008de, 0x00ae), + A6XX_PROTECT_NORDWR(0x00900, 0x004d), + A6XX_PROTECT_NORDWR(0x0098d, 0x0272), + A6XX_PROTECT_NORDWR(0x00e00, 0x0001), + A6XX_PROTECT_NORDWR(0x00e03, 0x000c), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), + A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), + A6XX_PROTECT_NORDWR(0x08630, 0x01cf), + A6XX_PROTECT_NORDWR(0x08e00, 0x0000), + A6XX_PROTECT_NORDWR(0x08e08, 0x0000), + A6XX_PROTECT_NORDWR(0x08e50, 0x001f), + A6XX_PROTECT_NORDWR(0x09624, 0x01db), + A6XX_PROTECT_NORDWR(0x09e70, 0x0001), + A6XX_PROTECT_NORDWR(0x09e78, 0x0187), + A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), + A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae50, 0x032f), + A6XX_PROTECT_NORDWR(0x0b604, 0x0000), + A6XX_PROTECT_NORDWR(0x0be02, 0x0001), + A6XX_PROTECT_NORDWR(0x0be20, 0x17df), + A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */ +}; +DECLARE_ADRENO_PROTECT(a630_protect, 32); + +/* These are for a620 and a650 */ +static const u32 a650_protect_regs[] = { + A6XX_PROTECT_RDONLY(0x00000, 0x04ff), + A6XX_PROTECT_RDONLY(0x00501, 0x0005), + A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), + A6XX_PROTECT_NORDWR(0x0050e, 0x0000), + A6XX_PROTECT_NORDWR(0x00510, 0x0000), + A6XX_PROTECT_NORDWR(0x00534, 0x0000), + A6XX_PROTECT_NORDWR(0x00800, 0x0082), + A6XX_PROTECT_NORDWR(0x008a0, 0x0008), + A6XX_PROTECT_NORDWR(0x008ab, 0x0024), + A6XX_PROTECT_RDONLY(0x008de, 0x00ae), + A6XX_PROTECT_NORDWR(0x00900, 0x004d), + A6XX_PROTECT_NORDWR(0x0098d, 0x0272), + A6XX_PROTECT_NORDWR(0x00e00, 0x0001), + A6XX_PROTECT_NORDWR(0x00e03, 0x000c), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), + A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), + A6XX_PROTECT_NORDWR(0x08630, 0x01cf), + A6XX_PROTECT_NORDWR(0x08e00, 0x0000), + A6XX_PROTECT_NORDWR(0x08e08, 0x0000), + A6XX_PROTECT_NORDWR(0x08e50, 0x001f), + A6XX_PROTECT_NORDWR(0x08e80, 0x027f), + A6XX_PROTECT_NORDWR(0x09624, 0x01db), + A6XX_PROTECT_NORDWR(0x09e60, 0x0011), + A6XX_PROTECT_NORDWR(0x09e78, 0x0187), + A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), + A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae50, 0x032f), + A6XX_PROTECT_NORDWR(0x0b604, 0x0000), + A6XX_PROTECT_NORDWR(0x0b608, 0x0007), + A6XX_PROTECT_NORDWR(0x0be02, 0x0001), + A6XX_PROTECT_NORDWR(0x0be20, 0x17df), + A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1a800, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0443), + A6XX_PROTECT_RDONLY(0x1f844, 0x007b), + A6XX_PROTECT_NORDWR(0x1f887, 0x001b), + A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ +}; +DECLARE_ADRENO_PROTECT(a650_protect, 48); + +/* These are for a635 and a660 */ +static const u32 a660_protect_regs[] = { + A6XX_PROTECT_RDONLY(0x00000, 0x04ff), + A6XX_PROTECT_RDONLY(0x00501, 0x0005), + A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), + A6XX_PROTECT_NORDWR(0x0050e, 0x0000), + A6XX_PROTECT_NORDWR(0x00510, 0x0000), + A6XX_PROTECT_NORDWR(0x00534, 0x0000), + A6XX_PROTECT_NORDWR(0x00800, 0x0082), + A6XX_PROTECT_NORDWR(0x008a0, 0x0008), + A6XX_PROTECT_NORDWR(0x008ab, 0x0024), + A6XX_PROTECT_RDONLY(0x008de, 0x00ae), + A6XX_PROTECT_NORDWR(0x00900, 0x004d), + A6XX_PROTECT_NORDWR(0x0098d, 0x0272), + A6XX_PROTECT_NORDWR(0x00e00, 0x0001), + A6XX_PROTECT_NORDWR(0x00e03, 0x000c), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), + A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), + A6XX_PROTECT_NORDWR(0x08630, 0x01cf), + A6XX_PROTECT_NORDWR(0x08e00, 0x0000), + A6XX_PROTECT_NORDWR(0x08e08, 0x0000), + A6XX_PROTECT_NORDWR(0x08e50, 0x001f), + A6XX_PROTECT_NORDWR(0x08e80, 0x027f), + A6XX_PROTECT_NORDWR(0x09624, 0x01db), + A6XX_PROTECT_NORDWR(0x09e60, 0x0011), + A6XX_PROTECT_NORDWR(0x09e78, 0x0187), + A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), + A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae50, 0x012f), + A6XX_PROTECT_NORDWR(0x0b604, 0x0000), + A6XX_PROTECT_NORDWR(0x0b608, 0x0006), + A6XX_PROTECT_NORDWR(0x0be02, 0x0001), + A6XX_PROTECT_NORDWR(0x0be20, 0x015f), + A6XX_PROTECT_NORDWR(0x0d000, 0x05ff), + A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1a400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0443), + A6XX_PROTECT_RDONLY(0x1f844, 0x007b), + A6XX_PROTECT_NORDWR(0x1f860, 0x0000), + A6XX_PROTECT_NORDWR(0x1f887, 0x001b), + A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ +}; +DECLARE_ADRENO_PROTECT(a660_protect, 48); + +/* These are for a690 */ +static const u32 a690_protect_regs[] = { + A6XX_PROTECT_RDONLY(0x00000, 0x004ff), + A6XX_PROTECT_RDONLY(0x00501, 0x00001), + A6XX_PROTECT_RDONLY(0x0050b, 0x002f4), + A6XX_PROTECT_NORDWR(0x0050e, 0x00000), + A6XX_PROTECT_NORDWR(0x00510, 0x00000), + A6XX_PROTECT_NORDWR(0x00534, 0x00000), + A6XX_PROTECT_NORDWR(0x00800, 0x00082), + A6XX_PROTECT_NORDWR(0x008a0, 0x00008), + A6XX_PROTECT_NORDWR(0x008ab, 0x00024), + A6XX_PROTECT_RDONLY(0x008de, 0x000ae), + A6XX_PROTECT_NORDWR(0x00900, 0x0004d), + A6XX_PROTECT_NORDWR(0x0098d, 0x00272), + A6XX_PROTECT_NORDWR(0x00e00, 0x00001), + A6XX_PROTECT_NORDWR(0x00e03, 0x0000c), + A6XX_PROTECT_NORDWR(0x03c00, 0x000c3), + A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff), + A6XX_PROTECT_NORDWR(0x08630, 0x001cf), + A6XX_PROTECT_NORDWR(0x08e00, 0x00000), + A6XX_PROTECT_NORDWR(0x08e08, 0x00007), + A6XX_PROTECT_NORDWR(0x08e50, 0x0001f), + A6XX_PROTECT_NORDWR(0x08e80, 0x0027f), + A6XX_PROTECT_NORDWR(0x09624, 0x001db), + A6XX_PROTECT_NORDWR(0x09e60, 0x00011), + A6XX_PROTECT_NORDWR(0x09e78, 0x00187), + A6XX_PROTECT_NORDWR(0x0a630, 0x001cf), + A6XX_PROTECT_NORDWR(0x0ae02, 0x00000), + A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f), + A6XX_PROTECT_NORDWR(0x0b604, 0x00000), + A6XX_PROTECT_NORDWR(0x0b608, 0x00006), + A6XX_PROTECT_NORDWR(0x0be02, 0x00001), + A6XX_PROTECT_NORDWR(0x0be20, 0x0015f), + A6XX_PROTECT_NORDWR(0x0d000, 0x005ff), + A6XX_PROTECT_NORDWR(0x0f000, 0x00bff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff), + A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */ +}; +DECLARE_ADRENO_PROTECT(a690_protect, 48); + static const struct adreno_info a6xx_gpus[] = { { .chip_ids = ADRENO_CHIP_IDS(0x06010000), @@ -468,6 +635,7 @@ static const struct adreno_info a6xx_gpus[] = { .zapfw = "a610_zap.mdt", .a6xx = &(struct a6xx_info) { .hwcg = a612_hwcg, + .protect = &a630_protect, }, /* * There are (at least) three SoCs implementing A610: SM6125 @@ -498,6 +666,7 @@ static const struct adreno_info a6xx_gpus[] = { .zapfw = "a615_zap.mbn", .a6xx = &(struct a6xx_info) { .hwcg = a615_hwcg, + .protect = &a630_protect, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -519,6 +688,7 @@ static const struct adreno_info a6xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .a6xx = &(struct a6xx_info) { + .protect = &a630_protect, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -540,6 +710,7 @@ static const struct adreno_info a6xx_gpus[] = { .zapfw = "a615_zap.mdt", .a6xx = &(struct a6xx_info) { .hwcg = a615_hwcg, + .protect = &a630_protect, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -561,6 +732,7 @@ static const struct adreno_info a6xx_gpus[] = { .zapfw = "a615_zap.mdt", .a6xx = &(struct a6xx_info) { .hwcg = a615_hwcg, + .protect = &a630_protect, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -582,6 +754,7 @@ static const struct adreno_info a6xx_gpus[] = { .zapfw = "a615_zap.mdt", .a6xx = &(struct a6xx_info) { .hwcg = a615_hwcg, + .protect = &a630_protect, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -608,6 +781,7 @@ static const struct adreno_info a6xx_gpus[] = { .zapfw = "a630_zap.mdt", .a6xx = &(struct a6xx_info) { .hwcg = a630_hwcg, + .protect = &a630_protect, }, }, { .chip_ids = ADRENO_CHIP_IDS(0x06040001), @@ -624,6 +798,7 @@ static const struct adreno_info a6xx_gpus[] = { .zapfw = "a640_zap.mdt", .a6xx = &(struct a6xx_info) { .hwcg = a640_hwcg, + .protect = &a630_protect, }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -645,6 +820,7 @@ static const struct adreno_info a6xx_gpus[] = { .zapfw = "a650_zap.mdt", .a6xx = &(struct a6xx_info) { .hwcg = a650_hwcg, + .protect = &a650_protect, }, .address_space_size = SZ_16G, .speedbins = ADRENO_SPEEDBINS( @@ -669,6 +845,7 @@ static const struct adreno_info a6xx_gpus[] = { .zapfw = "a660_zap.mdt", .a6xx = &(struct a6xx_info) { .hwcg = a660_hwcg, + .protect = &a660_protect, }, .address_space_size = SZ_16G, }, { @@ -686,6 +863,7 @@ static const struct adreno_info a6xx_gpus[] = { .zapfw = "a660_zap.mbn", .a6xx = &(struct a6xx_info) { .hwcg = a660_hwcg, + .protect = &a660_protect, }, .address_space_size = SZ_16G, .speedbins = ADRENO_SPEEDBINS( @@ -709,6 +887,7 @@ static const struct adreno_info a6xx_gpus[] = { .zapfw = "a640_zap.mdt", .a6xx = &(struct a6xx_info) { .hwcg = a640_hwcg, + .protect = &a630_protect, }, }, { .chip_ids = ADRENO_CHIP_IDS(0x06090000), @@ -725,6 +904,7 @@ static const struct adreno_info a6xx_gpus[] = { .zapfw = "a690_zap.mdt", .a6xx = &(struct a6xx_info) { .hwcg = a690_hwcg, + .protect = &a690_protect, }, .address_space_size = SZ_16G, } @@ -916,6 +1096,60 @@ static const struct adreno_reglist a740_hwcg[] = { {}, }; +static const u32 a730_protect_regs[] = { + A6XX_PROTECT_RDONLY(0x00000, 0x04ff), + A6XX_PROTECT_RDONLY(0x0050b, 0x0058), + A6XX_PROTECT_NORDWR(0x0050e, 0x0000), + A6XX_PROTECT_NORDWR(0x00510, 0x0000), + A6XX_PROTECT_NORDWR(0x00534, 0x0000), + A6XX_PROTECT_RDONLY(0x005fb, 0x009d), + A6XX_PROTECT_NORDWR(0x00699, 0x01e9), + A6XX_PROTECT_NORDWR(0x008a0, 0x0008), + A6XX_PROTECT_NORDWR(0x008ab, 0x0024), + /* 0x008d0-0x008dd and 0x008e0-0x008e6 are unprotected on purpose for tools like perfetto */ + A6XX_PROTECT_NORDWR(0x008de, 0x0001), + A6XX_PROTECT_RDONLY(0x008e7, 0x014b), + A6XX_PROTECT_NORDWR(0x00900, 0x004d), + A6XX_PROTECT_NORDWR(0x0098d, 0x00b2), + A6XX_PROTECT_NORDWR(0x00a41, 0x01be), + A6XX_PROTECT_NORDWR(0x00df0, 0x0001), + A6XX_PROTECT_NORDWR(0x00e01, 0x0000), + A6XX_PROTECT_NORDWR(0x00e07, 0x0008), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), + A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), + A6XX_PROTECT_NORDWR(0x08630, 0x01cf), + A6XX_PROTECT_NORDWR(0x08e00, 0x0000), + A6XX_PROTECT_NORDWR(0x08e08, 0x0000), + A6XX_PROTECT_NORDWR(0x08e50, 0x001f), + A6XX_PROTECT_NORDWR(0x08e80, 0x0280), + A6XX_PROTECT_NORDWR(0x09624, 0x01db), + A6XX_PROTECT_NORDWR(0x09e40, 0x0000), + A6XX_PROTECT_NORDWR(0x09e64, 0x000d), + A6XX_PROTECT_NORDWR(0x09e78, 0x0187), + A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), + A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae50, 0x000f), + A6XX_PROTECT_NORDWR(0x0ae66, 0x0003), + A6XX_PROTECT_NORDWR(0x0ae6f, 0x0003), + A6XX_PROTECT_NORDWR(0x0b604, 0x0003), + A6XX_PROTECT_NORDWR(0x0ec00, 0x0fff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x0053), + A6XX_PROTECT_RDONLY(0x18454, 0x0004), + A6XX_PROTECT_NORDWR(0x18459, 0x1fff), + A6XX_PROTECT_NORDWR(0x1a459, 0x1fff), + A6XX_PROTECT_NORDWR(0x1c459, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0443), + A6XX_PROTECT_RDONLY(0x1f844, 0x007b), + A6XX_PROTECT_NORDWR(0x1f860, 0x0000), + A6XX_PROTECT_NORDWR(0x1f878, 0x002a), + /* CP_PROTECT_REG[45, 46] are left untouched! */ + 0, + 0, + A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000), +}; +DECLARE_ADRENO_PROTECT(a730_protect, 48); + static const struct adreno_info a7xx_gpus[] = { { .chip_ids = ADRENO_CHIP_IDS(0x07000200), @@ -952,6 +1186,7 @@ static const struct adreno_info a7xx_gpus[] = { .zapfw = "a730_zap.mdt", .a6xx = &(struct a6xx_info) { .hwcg = a730_hwcg, + .protect = &a730_protect, }, .address_space_size = SZ_16G, }, { @@ -969,6 +1204,7 @@ static const struct adreno_info a7xx_gpus[] = { .zapfw = "a740_zap.mdt", .a6xx = &(struct a6xx_info) { .hwcg = a740_hwcg, + .protect = &a730_protect, }, .address_space_size = SZ_16G, }, { @@ -985,8 +1221,19 @@ static const struct adreno_info a7xx_gpus[] = { .init = a6xx_gpu_init, .zapfw = "gen70900_zap.mbn", .a6xx = &(struct a6xx_info) { + .protect = &a730_protect, }, .address_space_size = SZ_16G, } }; DECLARK_ADRENO_GPULIST(a7xx); + +static inline void __build_asserts(void) +{ + BUILD_BUG_ON(a630_protect.count > a630_protect.count_max); + BUILD_BUG_ON(a650_protect.count > a650_protect.count_max); + BUILD_BUG_ON(a660_protect.count > a660_protect.count_max); + BUILD_BUG_ON(a690_protect.count > a690_protect.count_max); + BUILD_BUG_ON(a730_protect.count > a730_protect.count_max); +} + diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 7e01fb551f12..f22a9e8460b3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -465,256 +465,11 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); } -/* For a615, a616, a618, a619, a630, a640 and a680 */ -static const u32 a6xx_protect[] = { - A6XX_PROTECT_RDONLY(0x00000, 0x04ff), - A6XX_PROTECT_RDONLY(0x00501, 0x0005), - A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), - A6XX_PROTECT_NORDWR(0x0050e, 0x0000), - A6XX_PROTECT_NORDWR(0x00510, 0x0000), - A6XX_PROTECT_NORDWR(0x00534, 0x0000), - A6XX_PROTECT_NORDWR(0x00800, 0x0082), - A6XX_PROTECT_NORDWR(0x008a0, 0x0008), - A6XX_PROTECT_NORDWR(0x008ab, 0x0024), - A6XX_PROTECT_RDONLY(0x008de, 0x00ae), - A6XX_PROTECT_NORDWR(0x00900, 0x004d), - A6XX_PROTECT_NORDWR(0x0098d, 0x0272), - A6XX_PROTECT_NORDWR(0x00e00, 0x0001), - A6XX_PROTECT_NORDWR(0x00e03, 0x000c), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), - A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), - A6XX_PROTECT_NORDWR(0x08630, 0x01cf), - A6XX_PROTECT_NORDWR(0x08e00, 0x0000), - A6XX_PROTECT_NORDWR(0x08e08, 0x0000), - A6XX_PROTECT_NORDWR(0x08e50, 0x001f), - A6XX_PROTECT_NORDWR(0x09624, 0x01db), - A6XX_PROTECT_NORDWR(0x09e70, 0x0001), - A6XX_PROTECT_NORDWR(0x09e78, 0x0187), - A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae50, 0x032f), - A6XX_PROTECT_NORDWR(0x0b604, 0x0000), - A6XX_PROTECT_NORDWR(0x0be02, 0x0001), - A6XX_PROTECT_NORDWR(0x0be20, 0x17df), - A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */ -}; - -/* These are for a620 and a650 */ -static const u32 a650_protect[] = { - A6XX_PROTECT_RDONLY(0x00000, 0x04ff), - A6XX_PROTECT_RDONLY(0x00501, 0x0005), - A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), - A6XX_PROTECT_NORDWR(0x0050e, 0x0000), - A6XX_PROTECT_NORDWR(0x00510, 0x0000), - A6XX_PROTECT_NORDWR(0x00534, 0x0000), - A6XX_PROTECT_NORDWR(0x00800, 0x0082), - A6XX_PROTECT_NORDWR(0x008a0, 0x0008), - A6XX_PROTECT_NORDWR(0x008ab, 0x0024), - A6XX_PROTECT_RDONLY(0x008de, 0x00ae), - A6XX_PROTECT_NORDWR(0x00900, 0x004d), - A6XX_PROTECT_NORDWR(0x0098d, 0x0272), - A6XX_PROTECT_NORDWR(0x00e00, 0x0001), - A6XX_PROTECT_NORDWR(0x00e03, 0x000c), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), - A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), - A6XX_PROTECT_NORDWR(0x08630, 0x01cf), - A6XX_PROTECT_NORDWR(0x08e00, 0x0000), - A6XX_PROTECT_NORDWR(0x08e08, 0x0000), - A6XX_PROTECT_NORDWR(0x08e50, 0x001f), - A6XX_PROTECT_NORDWR(0x08e80, 0x027f), - A6XX_PROTECT_NORDWR(0x09624, 0x01db), - A6XX_PROTECT_NORDWR(0x09e60, 0x0011), - A6XX_PROTECT_NORDWR(0x09e78, 0x0187), - A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae50, 0x032f), - A6XX_PROTECT_NORDWR(0x0b604, 0x0000), - A6XX_PROTECT_NORDWR(0x0b608, 0x0007), - A6XX_PROTECT_NORDWR(0x0be02, 0x0001), - A6XX_PROTECT_NORDWR(0x0be20, 0x17df), - A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1a800, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0443), - A6XX_PROTECT_RDONLY(0x1f844, 0x007b), - A6XX_PROTECT_NORDWR(0x1f887, 0x001b), - A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ -}; - -/* These are for a635 and a660 */ -static const u32 a660_protect[] = { - A6XX_PROTECT_RDONLY(0x00000, 0x04ff), - A6XX_PROTECT_RDONLY(0x00501, 0x0005), - A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), - A6XX_PROTECT_NORDWR(0x0050e, 0x0000), - A6XX_PROTECT_NORDWR(0x00510, 0x0000), - A6XX_PROTECT_NORDWR(0x00534, 0x0000), - A6XX_PROTECT_NORDWR(0x00800, 0x0082), - A6XX_PROTECT_NORDWR(0x008a0, 0x0008), - A6XX_PROTECT_NORDWR(0x008ab, 0x0024), - A6XX_PROTECT_RDONLY(0x008de, 0x00ae), - A6XX_PROTECT_NORDWR(0x00900, 0x004d), - A6XX_PROTECT_NORDWR(0x0098d, 0x0272), - A6XX_PROTECT_NORDWR(0x00e00, 0x0001), - A6XX_PROTECT_NORDWR(0x00e03, 0x000c), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), - A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), - A6XX_PROTECT_NORDWR(0x08630, 0x01cf), - A6XX_PROTECT_NORDWR(0x08e00, 0x0000), - A6XX_PROTECT_NORDWR(0x08e08, 0x0000), - A6XX_PROTECT_NORDWR(0x08e50, 0x001f), - A6XX_PROTECT_NORDWR(0x08e80, 0x027f), - A6XX_PROTECT_NORDWR(0x09624, 0x01db), - A6XX_PROTECT_NORDWR(0x09e60, 0x0011), - A6XX_PROTECT_NORDWR(0x09e78, 0x0187), - A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae50, 0x012f), - A6XX_PROTECT_NORDWR(0x0b604, 0x0000), - A6XX_PROTECT_NORDWR(0x0b608, 0x0006), - A6XX_PROTECT_NORDWR(0x0be02, 0x0001), - A6XX_PROTECT_NORDWR(0x0be20, 0x015f), - A6XX_PROTECT_NORDWR(0x0d000, 0x05ff), - A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1a400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0443), - A6XX_PROTECT_RDONLY(0x1f844, 0x007b), - A6XX_PROTECT_NORDWR(0x1f860, 0x0000), - A6XX_PROTECT_NORDWR(0x1f887, 0x001b), - A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ -}; - -/* These are for a690 */ -static const u32 a690_protect[] = { - A6XX_PROTECT_RDONLY(0x00000, 0x004ff), - A6XX_PROTECT_RDONLY(0x00501, 0x00001), - A6XX_PROTECT_RDONLY(0x0050b, 0x002f4), - A6XX_PROTECT_NORDWR(0x0050e, 0x00000), - A6XX_PROTECT_NORDWR(0x00510, 0x00000), - A6XX_PROTECT_NORDWR(0x00534, 0x00000), - A6XX_PROTECT_NORDWR(0x00800, 0x00082), - A6XX_PROTECT_NORDWR(0x008a0, 0x00008), - A6XX_PROTECT_NORDWR(0x008ab, 0x00024), - A6XX_PROTECT_RDONLY(0x008de, 0x000ae), - A6XX_PROTECT_NORDWR(0x00900, 0x0004d), - A6XX_PROTECT_NORDWR(0x0098d, 0x00272), - A6XX_PROTECT_NORDWR(0x00e00, 0x00001), - A6XX_PROTECT_NORDWR(0x00e03, 0x0000c), - A6XX_PROTECT_NORDWR(0x03c00, 0x000c3), - A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff), - A6XX_PROTECT_NORDWR(0x08630, 0x001cf), - A6XX_PROTECT_NORDWR(0x08e00, 0x00000), - A6XX_PROTECT_NORDWR(0x08e08, 0x00007), - A6XX_PROTECT_NORDWR(0x08e50, 0x0001f), - A6XX_PROTECT_NORDWR(0x08e80, 0x0027f), - A6XX_PROTECT_NORDWR(0x09624, 0x001db), - A6XX_PROTECT_NORDWR(0x09e60, 0x00011), - A6XX_PROTECT_NORDWR(0x09e78, 0x00187), - A6XX_PROTECT_NORDWR(0x0a630, 0x001cf), - A6XX_PROTECT_NORDWR(0x0ae02, 0x00000), - A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f), - A6XX_PROTECT_NORDWR(0x0b604, 0x00000), - A6XX_PROTECT_NORDWR(0x0b608, 0x00006), - A6XX_PROTECT_NORDWR(0x0be02, 0x00001), - A6XX_PROTECT_NORDWR(0x0be20, 0x0015f), - A6XX_PROTECT_NORDWR(0x0d000, 0x005ff), - A6XX_PROTECT_NORDWR(0x0f000, 0x00bff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff), - A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */ -}; - -static const u32 a730_protect[] = { - A6XX_PROTECT_RDONLY(0x00000, 0x04ff), - A6XX_PROTECT_RDONLY(0x0050b, 0x0058), - A6XX_PROTECT_NORDWR(0x0050e, 0x0000), - A6XX_PROTECT_NORDWR(0x00510, 0x0000), - A6XX_PROTECT_NORDWR(0x00534, 0x0000), - A6XX_PROTECT_RDONLY(0x005fb, 0x009d), - A6XX_PROTECT_NORDWR(0x00699, 0x01e9), - A6XX_PROTECT_NORDWR(0x008a0, 0x0008), - A6XX_PROTECT_NORDWR(0x008ab, 0x0024), - /* 0x008d0-0x008dd and 0x008e0-0x008e6 are unprotected on purpose for tools like perfetto */ - A6XX_PROTECT_NORDWR(0x008de, 0x0001), - A6XX_PROTECT_RDONLY(0x008e7, 0x014b), - A6XX_PROTECT_NORDWR(0x00900, 0x004d), - A6XX_PROTECT_NORDWR(0x0098d, 0x00b2), - A6XX_PROTECT_NORDWR(0x00a41, 0x01be), - A6XX_PROTECT_NORDWR(0x00df0, 0x0001), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e07, 0x0008), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), - A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), - A6XX_PROTECT_NORDWR(0x08630, 0x01cf), - A6XX_PROTECT_NORDWR(0x08e00, 0x0000), - A6XX_PROTECT_NORDWR(0x08e08, 0x0000), - A6XX_PROTECT_NORDWR(0x08e50, 0x001f), - A6XX_PROTECT_NORDWR(0x08e80, 0x0280), - A6XX_PROTECT_NORDWR(0x09624, 0x01db), - A6XX_PROTECT_NORDWR(0x09e40, 0x0000), - A6XX_PROTECT_NORDWR(0x09e64, 0x000d), - A6XX_PROTECT_NORDWR(0x09e78, 0x0187), - A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae50, 0x000f), - A6XX_PROTECT_NORDWR(0x0ae66, 0x0003), - A6XX_PROTECT_NORDWR(0x0ae6f, 0x0003), - A6XX_PROTECT_NORDWR(0x0b604, 0x0003), - A6XX_PROTECT_NORDWR(0x0ec00, 0x0fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x0053), - A6XX_PROTECT_RDONLY(0x18454, 0x0004), - A6XX_PROTECT_NORDWR(0x18459, 0x1fff), - A6XX_PROTECT_NORDWR(0x1a459, 0x1fff), - A6XX_PROTECT_NORDWR(0x1c459, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0443), - A6XX_PROTECT_RDONLY(0x1f844, 0x007b), - A6XX_PROTECT_NORDWR(0x1f860, 0x0000), - A6XX_PROTECT_NORDWR(0x1f878, 0x002a), - /* CP_PROTECT_REG[45, 46] are left untouched! */ - 0, - 0, - A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000), -}; - static void a6xx_set_cp_protect(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - const u32 *regs = a6xx_protect; - unsigned i, count, count_max; - - if (adreno_is_a650(adreno_gpu) || adreno_is_a702(adreno_gpu)) { - regs = a650_protect; - count = ARRAY_SIZE(a650_protect); - count_max = 48; - BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48); - } else if (adreno_is_a690(adreno_gpu)) { - regs = a690_protect; - count = ARRAY_SIZE(a690_protect); - count_max = 48; - BUILD_BUG_ON(ARRAY_SIZE(a690_protect) > 48); - } else if (adreno_is_a660_family(adreno_gpu)) { - regs = a660_protect; - count = ARRAY_SIZE(a660_protect); - count_max = 48; - BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); - } else if (adreno_is_a730(adreno_gpu) || - adreno_is_a740(adreno_gpu) || - adreno_is_a750(adreno_gpu)) { - regs = a730_protect; - count = ARRAY_SIZE(a730_protect); - count_max = 48; - BUILD_BUG_ON(ARRAY_SIZE(a730_protect) > 48); - } else { - regs = a6xx_protect; - count = ARRAY_SIZE(a6xx_protect); - count_max = 32; - BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32); - } + const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; + unsigned i; /* * Enable access protection to privileged registers, fault on an access @@ -726,13 +481,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN | A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE); - for (i = 0; i < count - 1; i++) { + for (i = 0; i < protect->count - 1; i++) { /* Intentionally skip writing to some registers */ - if (regs[i]) - gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]); + if (protect->regs[i]) + gpu_write(gpu, REG_A6XX_CP_PROTECT(i), protect->regs[i]); } /* last CP_PROTECT to have "infinite" length on the last entry */ - gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]); + gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]); } static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 61c51e9c7f06..c206dab8bc08 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -16,9 +16,11 @@ extern bool hang_debug; * struct a6xx_info - a6xx specific information from device table * * @hwcg: hw clock gating register sequence + * @protect: CP_PROTECT settings */ struct a6xx_info { const struct adreno_reglist *hwcg; + const struct adreno_protect *protect; }; struct a6xx_gpu { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 849ce0ae9e75..4e5a437ebf8b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -143,6 +143,19 @@ const struct adreno_gpulist name ## _gpulist = { \ */ #define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} } +struct adreno_protect { + const uint32_t *regs; + uint32_t count; + uint32_t count_max; +}; + +#define DECLARE_ADRENO_PROTECT(name, __count_max) \ +static const struct adreno_protect name = { \ + .regs = name ## _regs, \ + .count = ARRAY_SIZE(name ## _regs), \ + .count_max = __count_max, \ +}; + struct adreno_gpu { struct msm_gpu base; const struct adreno_info *info;