From patchwork Tue Jun 18 05:30:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13701803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B90D1C27C4F for ; Tue, 18 Jun 2024 05:30:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 37E7010E102; Tue, 18 Jun 2024 05:30:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="V5JYFOYr"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 62C7C10E0D1 for ; Tue, 18 Jun 2024 05:30:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718688655; x=1750224655; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YrTlCdfEq3AOHWMENie1Oeemk8NXSD5BmDsq5thEYek=; b=V5JYFOYrUEueNHiz2D+shsyiGDtfc8VHpPamXrE/v5FItT1shZlhKd/r jhbp65S02TaudSB+EVDGfTKtnnYY0YgaHMoDPjuO7bqgECMj2uAC+TP6t jzh9Tpk9cFYV9k9o7RNIvdo2cXw+Abm+2BBbqLpvBYc6JBOAyU63dj0yW SGXAOtzh53uIW9KqM0x7joe9eivaJXkiGd2PqMrQ/jz+7GgfFMorTTzJY 1EFh8aGM5nx5pwVRLDhLGqTUUgYm/blHtYSC1hYWsxpBnB6uBCFiVXvi/ 64KkCtc0XT113xOnlu66453weOefpOpYlRsWiwnTlfH5h5bYuLkK+FoNh g==; X-CSE-ConnectionGUID: Rt3uxUq0T5Sm/SRdflvGoQ== X-CSE-MsgGUID: 7mDBNHMETJqSKT5TUNuplw== X-IronPort-AV: E=McAfee;i="6700,10204,11106"; a="33077705" X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="33077705" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:54 -0700 X-CSE-ConnectionGUID: WHxBIGG4Qwq9dYI6wHSWvQ== X-CSE-MsgGUID: J3fvtyrBQw6CTacFFwWnFw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="41365141" Received: from opintica-mobl1 (HELO jhogande-mobl1..) ([10.245.245.27]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:39 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 1/9] drm/i915/psr: Set SU area width as pipe src width Date: Tue, 18 Jun 2024 08:30:18 +0300 Message-Id: <20240618053026.3268759-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618053026.3268759-1-jouni.hogander@intel.com> References: <20240618053026.3268759-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently SU area width is set as MAX_INT. This is causing problems. Instead set it as pipe src width. Fixes: 86b26b6aeac7 ("drm/i915/psr: Carry su area in crtc_state") Signed-off-by: Jouni Högander Reviewed-by: Mika Kahola --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 920186c2264d..3f36b94020ff 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2316,7 +2316,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, crtc_state->psr2_su_area.x1 = 0; crtc_state->psr2_su_area.y1 = -1; - crtc_state->psr2_su_area.x2 = INT_MAX; + crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src); crtc_state->psr2_su_area.y2 = -1; /* From patchwork Tue Jun 18 05:30:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13701808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4330C2BA18 for ; Tue, 18 Jun 2024 05:31:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 06C6E10E562; Tue, 18 Jun 2024 05:31:01 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Fl2QYv5w"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2107B10E0D1 for ; Tue, 18 Jun 2024 05:30:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718688656; x=1750224656; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gKmfbzy9/jnJ1oP3iaW1LmWabsWJ1Smkbs0hdbvbuHo=; b=Fl2QYv5wpIGDqVyUQNmC33Xiy1uthL2HB2Pf8Vb6qqlprbmWhqAXfBfb OfxyitLqdUvdWGgT9D8V3MFaD19KUg+FY90WWLq93zUt4P1Y54CoSI53x /zYp0zfGXShjPKrdNQLk2+FAUrhMp25ZdLIQMeWIiTZHFaKN+ueooznK3 q+zXHKUmjxt70EKtZHNsm97xkbCvCbE9So+el2kXkYmOe9fQ7uQdtDzLb RMsiHMo/Cdd0+SFNfb8Ku+TexxIn2QxNpshdZdmQy7ayFncs9aCD+fSf7 rMcvOzljdPfz9edpJrTyLRyeb9TJ6+tyDo7bJQpG+zKt1TtXAmR7XD9P0 w==; X-CSE-ConnectionGUID: uqbWzTX+QKiJdhvWWAVDww== X-CSE-MsgGUID: aE2rs3E7SNiz3btzz+vmTQ== X-IronPort-AV: E=McAfee;i="6700,10204,11106"; a="33077706" X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="33077706" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:54 -0700 X-CSE-ConnectionGUID: JPQH5f0QTUCH5UQgDr365w== X-CSE-MsgGUID: a7ZMrKYgTwGvvI/ezYHY0g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="41365143" Received: from opintica-mobl1 (HELO jhogande-mobl1..) ([10.245.245.27]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:40 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 2/9] drm/i915/display: Wa 16021440873 is writing wrong register Date: Tue, 18 Jun 2024 08:30:19 +0300 Message-Id: <20240618053026.3268759-3-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618053026.3268759-1-jouni.hogander@intel.com> References: <20240618053026.3268759-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Wa 16021440873 is writing wrong register. Instead of PIPE_SRCSZ_ERLY_TPT write CURPOS_ERLY_TPT. v2: use right offset as well Fixes: 29cdef8539c3 ("drm/i915/display: Implement Wa_16021440873") Signed-off-by: Jouni Högander Reviewed-by: Mika Kahola --- drivers/gpu/drm/i915/display/intel_cursor.c | 4 ++-- drivers/gpu/drm/i915/display/intel_psr.c | 12 +++--------- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 7f7fc710350c..66436e526021 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -524,8 +524,8 @@ static void wa_16021440873(struct intel_plane *plane, intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl); - intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe), - PIPESRC_HEIGHT(et_y_position)); + intel_de_write(dev_priv, CURPOS_ERLY_TPT(dev_priv, pipe), + CURSOR_POS_Y(et_y_position)); } static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane, diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 3f36b94020ff..2a33e35ceeff 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2164,19 +2164,14 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, crtc_state->psr2_man_track_ctl = val; } -static u32 -psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state, - bool full_update, bool cursor_in_su_area) +static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state, + bool full_update) { int width, height; if (!crtc_state->enable_psr2_su_region_et || full_update) return 0; - if (!cursor_in_su_area) - return PIPESRC_WIDTH(0) | - PIPESRC_HEIGHT(drm_rect_height(&crtc_state->pipe_src)); - width = drm_rect_width(&crtc_state->psr2_su_area); height = drm_rect_height(&crtc_state->psr2_su_area); @@ -2485,8 +2480,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, skip_sel_fetch_set_loop: psr2_man_trk_ctl_calc(crtc_state, full_update); crtc_state->pipe_srcsz_early_tpt = - psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update, - cursor_in_su_area); + psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update); return 0; } From patchwork Tue Jun 18 05:30:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13701812 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E146C2BBCA for ; Tue, 18 Jun 2024 05:31:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1D03F10E576; Tue, 18 Jun 2024 05:31:07 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bt+xxpKH"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7EBF710E0D1 for ; Tue, 18 Jun 2024 05:30:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718688656; x=1750224656; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=33YLiH2F4aMq9H0Q/yYlkzJKKTelB/JI3Msgxqc/Gxk=; b=bt+xxpKHGM0KGYam41+/O4eVbTFwKQ24QQAyhZ20uSTWHTNELnmS53/e zRKdkyXcGabB7RCUehfRAOSx8Eqoez3z23tyZJlK3btJFkTlKfQwWFItI H0cJubcR4KzS1VT1mfXAa9Ew8Sf44+Y/Ryv6VzZaHkbisp5WK0ePbIjp8 Ez59qHjMvYiClrYgYH1rd2KFH7hweCIOvQm6QGdfVhs7wDxmZus8lJ81y W4tdCMiyM9nxrl+J7IACDDro7yh9CHcobVGrXA/HGIwb8l7ehbexxDTyw WGscIvbKDpXgdeg5YjnjQm4Rf6VSxxZ56UdTJBgrmzneYJ8vyUboxPnC+ A==; X-CSE-ConnectionGUID: WMWwLIDaTCGBf7Y/vN4uQQ== X-CSE-MsgGUID: WT7FpHFLTAyveYko+9aofg== X-IronPort-AV: E=McAfee;i="6700,10204,11106"; a="33077707" X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="33077707" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:55 -0700 X-CSE-ConnectionGUID: F86G9amVQD+Y2EGTN9FemQ== X-CSE-MsgGUID: m16ubK0zQPOfTNCqMhf7Zg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="41365145" Received: from opintica-mobl1 (HELO jhogande-mobl1..) ([10.245.245.27]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:42 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 3/9] drm/i915/alpm: Fix port clock usage in AUX Less wake time calculation Date: Tue, 18 Jun 2024 08:30:20 +0300 Message-Id: <20240618053026.3268759-4-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618053026.3268759-1-jouni.hogander@intel.com> References: <20240618053026.3268759-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Port clock is link rate in 10 kbit/s units. Take this into account when calculating AUX Less wake time. Fixes: da6a9836ac09 ("drm/i915/psr: Calculate aux less wake time") Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_alpm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 90072f6e3a33..67848fc1e24d 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -125,7 +125,8 @@ static int _lnl_compute_aux_less_wake_time(int port_clock) int tsilence_max = 180; int t1 = 50 * 1000; int tps4 = 252; - int tml_phy_lock = 1000 * 1000 * tps4 * 10 / port_clock; + /* port_clock is link rate in 10kbit/s units */ + int tml_phy_lock = 1000 * 1000 * tps4 / port_clock; int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1; int t2 = num_ml_phy_lock * tml_phy_lock; int tcds = 1 * t2; From patchwork Tue Jun 18 05:30:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13701807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1D03C2BB9A for ; Tue, 18 Jun 2024 05:31:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 06EFD10E569; Tue, 18 Jun 2024 05:31:01 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Nz0dM4Vv"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 937E410E1B9 for ; Tue, 18 Jun 2024 05:30:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718688656; x=1750224656; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=H18L/lqDtcUuhpmhy2gTGfqoglBFzuS9eAYYznD17PU=; b=Nz0dM4VvGnExQjhADAXDFpg0+ZGtF+Mnmqc6W/WpcIxi7NI8z336VH1W rn33vd7xSk0/WZC1uZMfi93qCcL9hfQH76tu8E5h7wa5ZWlTEmYQSASgm TlXHSjHP4xUhigZTDF0ZfdU26sVtzFVQnXSHX6CjB0EkMLFoVuUOHaRR+ krxOdqDPP3AyCxkZu4awEjBmuFYRunOCWry7UBkvpkfx2Zl6Rry0G2dHa gp/36ob8DGxr+KphmpeqHp7THhliBwoQDbdbomw/w8GRCBkD+9DmD4hdq kGj4EvxywO3cMc2UKynrRBX6IbB7F69E8RZRPZBTx8DPFoBn7RGr0jqS6 w==; X-CSE-ConnectionGUID: pb+SMdiKRKiFjRbigsHqiQ== X-CSE-MsgGUID: iB6tAbLNTeK6zBufbZD9ww== X-IronPort-AV: E=McAfee;i="6700,10204,11106"; a="33077708" X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="33077708" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:55 -0700 X-CSE-ConnectionGUID: uJ9ycVixQKGc4XjvY5QStg== X-CSE-MsgGUID: ShvD/LF3SAq2/+1+jiP+Nw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="41365147" Received: from opintica-mobl1 (HELO jhogande-mobl1..) ([10.245.245.27]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:44 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 4/9] drm/i915/psr: Disable Panel Replay if PSR mode is set via module parameter Date: Tue, 18 Jun 2024 08:30:21 +0300 Message-Id: <20240618053026.3268759-5-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618053026.3268759-1-jouni.hogander@intel.com> References: <20240618053026.3268759-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" If user is specifically limiting PSR mode to PSR1 or PSR2: disable Panel Replay. With default value -1 all modes are allowed including Panel Replay. Disabling PSR using value 0 disables Panel Replay as well. Also own compute config helper is added for Panel Replay. This makes sense because number of Panel Replay specific checks are increasing. v2: Squash adding Panel Replay compute config helper Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- .../drm/i915/display/intel_display_params.c | 3 +-- drivers/gpu/drm/i915/display/intel_psr.c | 27 +++++++++++++++++-- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index aebdb7b59dbf..79107607a6ff 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -106,8 +106,7 @@ intel_display_param_named_unsafe(enable_fbc, int, 0400, intel_display_param_named_unsafe(enable_psr, int, 0400, "Enable PSR " - "(0=disabled, 1=enable up to PSR1 and Panel Replay full frame update, " - "2=enable up to PSR2 and Panel Replay Selective Update) " + "(0=disabled, 1=enable up to PSR1, 2=enable up to PSR2) " "Default: -1 (use per-chip default)"); intel_display_param_named(psr_safest_params, bool, 0400, diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 2a33e35ceeff..cfce0fe05d92 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -235,6 +235,15 @@ static bool psr2_global_enabled(struct intel_dp *intel_dp) } } +static bool panel_replay_global_enabled(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + if (i915->display.params.enable_psr != -1) + return false; + return true; +} + static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -1455,6 +1464,21 @@ static bool _psr_compute_config(struct intel_dp *intel_dp, return true; } +static bool _panel_replay_compute_config(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + if (!CAN_PANEL_REPLAY(intel_dp)) + return false; + + if (!panel_replay_global_enabled(intel_dp)) { + drm_dbg_kms(&i915->drm, "Panel Replay disabled by flag\n"); + return false; + } + + return true; +} + void intel_psr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -1490,8 +1514,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, return; } - if (CAN_PANEL_REPLAY(intel_dp)) - crtc_state->has_panel_replay = true; + crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp); crtc_state->has_psr = crtc_state->has_panel_replay ? true : _psr_compute_config(intel_dp, crtc_state); From patchwork Tue Jun 18 05:30:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13701806 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1DD2C27C4F for ; Tue, 18 Jun 2024 05:31:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 74AF210E231; Tue, 18 Jun 2024 05:31:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="C9ShT20d"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id A6FBC10E231 for ; Tue, 18 Jun 2024 05:30:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718688656; x=1750224656; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fIZAZcw9P72RYJHaZXIKQWsqs6l2ETQSkP1vqzi6NAY=; b=C9ShT20dUiyE/RJxUBPfVN8R49eJg5RYARKJcqOcogTB9fufPadNmMf2 t6F3Wob6BiDGbA9I7UAkHbyHJXfeWWv3gpAEiSVoCD6R+ClacAnqzE9OC JO1qrV2ZYgEqEsbz1hE2ZWdmMdEk45swV2XYoxATMmjlbJYoWi+uMtKV/ sDsdgPVXvVzY2BbUBDSBHxVM4uCpQi8e2qQLiSDX0Pfgu68qDkizq34Vw mXK4g9eyywYbxOD/SzO7WyILIotAC9lUi+ciHL+eYXQDVnwEmN6umpJAr c5O8G3oZKeiOguQizLq3mKHnOs15jRyscsfRcpnvXbdt37oJsGH2nYipr g==; X-CSE-ConnectionGUID: 0IwOZaADQoaD8IqgDTi10Q== X-CSE-MsgGUID: RUUR6JIxTjy9NN7ByMBONA== X-IronPort-AV: E=McAfee;i="6700,10204,11106"; a="33077712" X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="33077712" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:55 -0700 X-CSE-ConnectionGUID: 7nKmdltJRAapGrE5beq6Kg== X-CSE-MsgGUID: QupTAB0HSS6Qo1sLAlfA0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="41365149" Received: from opintica-mobl1 (HELO jhogande-mobl1..) ([10.245.245.27]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:45 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 5/9] drm/i915/psr: Disable PSR2 SU Region ET if enable_psr module parameter is set Date: Tue, 18 Jun 2024 08:30:22 +0300 Message-Id: <20240618053026.3268759-6-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618053026.3268759-1-jouni.hogander@intel.com> References: <20240618053026.3268759-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently PSR2 SU Region Early Transport is enabled by default on Lunarlake if panel supports it despite enable_psr module parameter value. This patch makes it possible for user to limit used PSR mode and prevent SU Region Early Transport by setting enable_psr as 2. With default (-1) PSR2 SU Region Early Transport is allowed. v2: fix/improve commit desciption Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index cfce0fe05d92..800cfeabc139 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -235,6 +235,16 @@ static bool psr2_global_enabled(struct intel_dp *intel_dp) } } +static bool psr2_su_region_et_global_enabled(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + if (i915->display.params.enable_psr != -1) + return false; + + return true; +} + static bool panel_replay_global_enabled(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -683,7 +693,8 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay return panel_replay ? intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : - intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; + intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED && + psr2_su_region_et_global_enabled(intel_dp); } static void _panel_replay_enable_sink(struct intel_dp *intel_dp, From patchwork Tue Jun 18 05:30:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13701811 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A99E9C2BA18 for ; Tue, 18 Jun 2024 05:31:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BFA2F10E575; Tue, 18 Jun 2024 05:31:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Zt46iayG"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id B5A1310E0D1 for ; Tue, 18 Jun 2024 05:30:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718688656; x=1750224656; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QZVxvdkgU1IrxkqLEZeOwzNEIVYZ/7/NVYHhxSdYzY8=; b=Zt46iayGlVllq42cQbMnpWkJYCFVx/1ahqXZIXt8/MJMUo7rObG4wEwk Vz9tOH92Rk/dz2RE7VJ4AWlzboDDYV3NekIkV+yI57xJXmTiF0qmP3/no 1+ZSEAiZc65oIF17uVlnUA91vD+WAQjlZyzDGRJPA+qwTLuqMFqlgT2vU f40IbeJZsuqaC5tR89IJNxDEJrJCs5SUNHkub8J8TlOlciUuJ8WaZCGuF ueCPbjfpi7i0GkdlAgrdNpXVWE7Gt3yemsnbfZeELuGDb4oxjkRsNxq+d 1NpL2/ECyZL6fDL9Jj7dCUT0eXIRf4V02Lr9c9o4iKZ170BPv2NwUtbjW w==; X-CSE-ConnectionGUID: LpMTnUT4QsGKzjbub/2PFg== X-CSE-MsgGUID: 3CI5a4YaTUKx10EFJgLm/g== X-IronPort-AV: E=McAfee;i="6700,10204,11106"; a="33077715" X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="33077715" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:55 -0700 X-CSE-ConnectionGUID: DKrSPOQ7Rm+Hhc0wa+6rmw== X-CSE-MsgGUID: XY99/0nJRMmJFiydvLHOqw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="41365151" Received: from opintica-mobl1 (HELO jhogande-mobl1..) ([10.245.245.27]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:47 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 6/9] drm/i915/psr: Disable PSR/Panel Replay on sink side for PSR only Date: Tue, 18 Jun 2024 08:30:23 +0300 Message-Id: <20240618053026.3268759-7-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618053026.3268759-1-jouni.hogander@intel.com> References: <20240618053026.3268759-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enabling/disabling Panel Replay on sink side has to be done before link training. We can't disable it in sink side on PSR disable. Fixes: 88ae6c65ecdb ("drm/i915/psr: Unify panel replay enable/disable sink") Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 800cfeabc139..595097353ceb 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1974,13 +1974,13 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) } /* Disable PSR on Sink */ - drm_dp_dpcd_writeb(&intel_dp->aux, - intel_dp->psr.panel_replay_enabled ? - PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG, 0); + if (!intel_dp->psr.panel_replay_enabled) { + drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); - if (!intel_dp->psr.panel_replay_enabled && - intel_dp->psr.sel_update_enabled) - drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); + if (intel_dp->psr.sel_update_enabled) + drm_dp_dpcd_writeb(&intel_dp->aux, + DP_RECEIVER_ALPM_CONFIG, 0); + } intel_dp->psr.enabled = false; intel_dp->psr.panel_replay_enabled = false; From patchwork Tue Jun 18 05:30:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13701805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 557A7C2BB85 for ; Tue, 18 Jun 2024 05:31:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5EB5410E1B9; Tue, 18 Jun 2024 05:31:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="F8uxxqgS"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id C96DB10E1B9 for ; Tue, 18 Jun 2024 05:30:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718688656; x=1750224656; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mQrO82iDtaVTy9eQ8K9amjC0P2Dk/EDvlA8wm+52XDw=; b=F8uxxqgSy4R9TE8ipfjHcuw//J+UXYVLbjdwj6IJ46YIqNMcSQEWlXBb OY4av7IvV8P50k2K1347qNsT6/GujR/so/dJ9dw0FaECpyYifteYaduqa pFflnLdOF4n0g/offNDRiopqlUa5+7XLv85qZ9nCkS8iAapdy7A0MlEN7 YGRbKCL/GmsHC9dX2BzQx4NQ6T8SAvImbRcKCn6R4dnjljsn7i3FTxpV9 5SyWoUh6qj+GrMLR2Ufz6eAQtzfE0am4TGW9l249dDXXMNtOOo7yH1NMc mfyYkYapGLcTuSctfEG95QqJPbxMxD1DiRK3Gr7/d9ntwL4vw5/d2vxA/ A==; X-CSE-ConnectionGUID: nlPWDfIYTAyH1MwRGnRWHA== X-CSE-MsgGUID: TjbUvy2jQj6K2Xla5QQmZg== X-IronPort-AV: E=McAfee;i="6700,10204,11106"; a="33077718" X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="33077718" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:56 -0700 X-CSE-ConnectionGUID: YzWhg2uaSFyFffEbB7DikA== X-CSE-MsgGUID: pzL6rAnMTxGJsRcoy22Cvg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="41365153" Received: from opintica-mobl1 (HELO jhogande-mobl1..) ([10.245.245.27]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:49 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 7/9] drm/i915/psr: Add new debug bit to disable Panel Replay Date: Tue, 18 Jun 2024 08:30:24 +0300 Message-Id: <20240618053026.3268759-8-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618053026.3268759-1-jouni.hogander@intel.com> References: <20240618053026.3268759-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add new debug bit to be used with i915_edp_psr_debug debugfs interface. This can be used to disable Panel Replay. v2: ensure that fastset is performed when the bit changes Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 46b3cbeb4a82..8fe7942511f8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1703,6 +1703,7 @@ struct intel_psr { #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4 #define I915_PSR_DEBUG_IRQ 0x10 #define I915_PSR_DEBUG_SU_REGION_ET_DISABLE 0x20 +#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40 u32 debug; bool sink_support; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 595097353ceb..cd76109e928a 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -249,7 +249,8 @@ static bool panel_replay_global_enabled(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - if (i915->display.params.enable_psr != -1) + if ((i915->display.params.enable_psr != -1) || + (intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE)) return false; return true; } @@ -2788,11 +2789,13 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; - const u32 disable_bits = val & I915_PSR_DEBUG_SU_REGION_ET_DISABLE; + const u32 disable_bits = val & (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | + I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); u32 old_mode, old_disable_bits; int ret; if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE | + I915_PSR_DEBUG_PANEL_REPLAY_DISABLE | I915_PSR_DEBUG_MODE_MASK) || mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); @@ -2805,7 +2808,9 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; old_disable_bits = intel_dp->psr.debug & - I915_PSR_DEBUG_SU_REGION_ET_DISABLE; + (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | + I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); + intel_dp->psr.debug = val; /* From patchwork Tue Jun 18 05:30:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13701809 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 34062C27C4F for ; Tue, 18 Jun 2024 05:31:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 947E810E56D; Tue, 18 Jun 2024 05:31:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="AlLQRpSK"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id E1D8010E231 for ; Tue, 18 Jun 2024 05:30:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718688656; x=1750224656; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jIj9ij5DrGMykLZzp4Iadi8eXI53kOUQOx55c/XXF1w=; b=AlLQRpSKmT9P0jBus/zwCrzedSEr1jrdl/sRaT5ARs8hdFjtF4aMlTpx BwB8kiIQsRCa31jGlAgM57O6//I4VEJOUeqXudU9RyhV1IOY7ZQjtGJoU 60iSLjsglGmllyC48DftfYWV4EdiY1xEp6FiVY+2YoBSiNzPkeFemDeR0 W2yRNRAFyxF1lbdjUZdtTeY2/PcSo0OFnIl3CN5Srv0QG8ZPHM8mAXJ/W H4NJOPyHSSFK4/mhlT0HTxcF990T1D4Gw47FAymrH0jdl67JPmxB6aduI bdQgwle5U+48giqnSzRs3qYE6sF32gbnOV7uCMXkI+NDrmpthI1h0alrN Q==; X-CSE-ConnectionGUID: 1bL3OeocTTmO+jZUHSSEaA== X-CSE-MsgGUID: 8rekRL99TumhSzqHfWE2wA== X-IronPort-AV: E=McAfee;i="6700,10204,11106"; a="33077719" X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="33077719" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:56 -0700 X-CSE-ConnectionGUID: MbzDhq6tTWunZPaxkdoNPw== X-CSE-MsgGUID: VS3R6OvlSxOctFlL0ilLTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="41365156" Received: from opintica-mobl1 (HELO jhogande-mobl1..) ([10.245.245.27]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:50 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 8/9] Revert "drm/i915/psr: Disable early transport by default" Date: Tue, 18 Jun 2024 08:30:25 +0300 Message-Id: <20240618053026.3268759-9-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618053026.3268759-1-jouni.hogander@intel.com> References: <20240618053026.3268759-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This reverts commit f3c2031db7dfdf470a2d9bf3bd1efa6edfa72d8d. We want to notice possible issues faced with PSR2 Region Early Transport as early as possible -> let's revert patch disabling Region Early Transport by default. Also eDP 1.5 Panel Replay requires Early Transport. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index cd76109e928a..a9d9383e4ee5 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3110,9 +3110,6 @@ void intel_psr_init(struct intel_dp *intel_dp) else intel_dp->psr.source_support = true; - /* Disable early transport for now */ - intel_dp->psr.debug |= I915_PSR_DEBUG_SU_REGION_ET_DISABLE; - /* Set link_standby x link_off defaults */ if (DISPLAY_VER(dev_priv) < 12) /* For new platforms up to TGL let's respect VBT back again */ From patchwork Tue Jun 18 05:30:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13701810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE1F8C2BB85 for ; Tue, 18 Jun 2024 05:31:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 54ABC10E571; Tue, 18 Jun 2024 05:31:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="JhpfcJhe"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id EB54C10E562 for ; Tue, 18 Jun 2024 05:30:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718688657; x=1750224657; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0GnEG7sLN3HYMVpKQTciJ4TNIJX59NWBFVA+4FUHCFU=; b=JhpfcJhe9ogWwaa80X+JKMGwH8jmKWSNOsQe2xi8FYN27Afte5VA3JtC frDx3uGxSmr2IOGpxFKLRNIwYHDPxvtGCBdA9rMSQQaa8SDHXeRMRXtbz 8g8Cfv4r1kRkCCwWXx666JsBATZ+XChjxlBw58hOj1C6hz1vJjEzVrooZ b5EOC+FJIiqGIo8UdfJofOJlPKqHQ6jwBAJcsBimPcIch2Y8pPI3HYmVD fNHTGthpfLpcYQZANEWurmvovra70/4k7JJVgg5tUfUCmDrCxnVkPXUSX XsnVkyGUokvK27Cmf7LN98LpKlcElMnd1Su5ks95n1wN0CBnV/QwHcFWm w==; X-CSE-ConnectionGUID: VjlKfYNCRIWHadIm9fjjkQ== X-CSE-MsgGUID: nSMS1BtqR5yWX+CgJJgl1A== X-IronPort-AV: E=McAfee;i="6700,10204,11106"; a="33077721" X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="33077721" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:56 -0700 X-CSE-ConnectionGUID: A9YAbd1OR7+ipVdUjgVXgg== X-CSE-MsgGUID: wqP5QJ9BQIWC20+hUYWzpg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,246,1712646000"; d="scan'208";a="41365157" Received: from opintica-mobl1 (HELO jhogande-mobl1..) ([10.245.245.27]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2024 22:30:52 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 9/9] intel_alpm: Fix wrong offset for PORT_ALPM_* registers Date: Tue, 18 Jun 2024 08:30:26 +0300 Message-Id: <20240618053026.3268759-10-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618053026.3268759-1-jouni.hogander@intel.com> References: <20240618053026.3268759-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" PORT_ALPM_* registers are using MMIO_TRANS2 macro. This is not correct as they are port register. Use _PORT_MMIO instead. Fixes: 4ee30a448255 ("drm/i915/alpm: Add ALPM register definitions") Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_alpm.c | 5 +++-- drivers/gpu/drm/i915/display/intel_psr_regs.h | 6 ++++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 67848fc1e24d..c7092af7da33 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -310,6 +310,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + enum port port = dp_to_dig_port(intel_dp)->base.port; u32 alpm_ctl; if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled && @@ -328,7 +329,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines); intel_de_write(dev_priv, - PORT_ALPM_CTL(dev_priv, cpu_transcoder), + PORT_ALPM_CTL(dev_priv, port), PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | @@ -336,7 +337,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, intel_dp->alpm_parameters.silence_period_sym_clocks)); intel_de_write(dev_priv, - PORT_ALPM_LFPS_CTL(dev_priv, cpu_transcoder), + PORT_ALPM_LFPS_CTL(dev_priv, port), PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 1e503209da09..642bb15fb547 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -294,7 +294,8 @@ #define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val) #define _PORT_ALPM_CTL_A 0x16fa2c -#define PORT_ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A) +#define _PORT_ALPM_CTL_B 0x16fc2c +#define PORT_ALPM_CTL(dev_priv, port) _MMIO_PORT(port, _PORT_ALPM_CTL_A, _PORT_ALPM_CTL_B) #define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31) #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20) #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val) @@ -304,7 +305,8 @@ #define PORT_ALPM_CTL_SILENCE_PERIOD(val) REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val) #define _PORT_ALPM_LFPS_CTL_A 0x16fa30 -#define PORT_ALPM_LFPS_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A) +#define _PORT_ALPM_LFPS_CTL_B 0x16fc30 +#define PORT_ALPM_LFPS_CTL(dev_priv, port) _MMIO_PORT(port, _PORT_ALPM_LFPS_CTL_A, _PORT_ALPM_LFPS_CTL_B) #define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY REG_BIT(31) #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK REG_GENMASK(27, 24) #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN 7