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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 1/7] mlxsw: pci: Split NAPI setup/teardown into two steps Date: Tue, 18 Jun 2024 13:34:40 +0200 Message-ID: <8dbf37e859f07247498fca17109b8858ff2b0498.1718709196.git.petrm@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|SA1PR12MB6869:EE_ X-MS-Office365-Filtering-Correlation-Id: a754d114-3361-4798-ec6e-08dc8f8ac40d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|1800799021|376011|36860700010|82310400023; X-Microsoft-Antispam-Message-Info: NWIZ29Lt6nDMpFsgi6cK49NT8dnzK1rUmi5LU8MYI1Z5hYVdAJHKc2d9VV5aL75Z1xuE7dk2WrjU+x+x/DMq28HdnbXO3Xyr84BL57u+PrF507NlbOaEk3wu3EKv77JBlvq1R/bDcFSVP0AZA4QWs2h47uclU8nhjC3zjawg/M5HEcCI9gxLKHfKBlJCR0nimtWt+hEqaRYB9j1EGkw4477O5axcfHZs5U1BH4iomrDcA8gbnlvP84s4jjD6I7bLBBQNt31m/2I1oRVbPpy3MuATBumvIhHtMP0SAgVizu8LKouKsduQQnVjNKwc9905zwwFPZEbCguDvUqWcFdiIDrEpWBtbpSMlMBYHqzgZwSrrGKsvhCoYbKB3CjvrHAugVs8TYIycQgAbKs5XeIQVfeXUo9Uon7R08IMKf5UQkmhSN9OmGYqNIH+iT3FZ+OuDIUdcrZEC3jEv1Dw1GjKK8iPneSUsffqgmsgq8N+NHKoPw1uSv/zKnUgycdq/oJSSfW0YzaSVFzT43eRxuvppW5FUhBMaoxXcld8e87UBB6rheCM6ZLiB3WJsBAuY+s6glm8hQjHV4/y6VO/+ayJlDKK/a7oid8BVN77/4fLQzZ8DwvswUh31Brzxn5UiFRwFK0vlsdw4e93lm3UHNmzj2nMV+QnPknApJPqmiOWLnGUsQMHPuM2IvPxFKsr+akz+Pe6F478w9+rHFfXldYP6/5e1AF263YfiX0oxRc9+2RV9xrYOLGywHjHfPzMcvSeY89MYMD7+TSNZjn6knXjJdeYTHMI2bwRrsd5QTsKq68DYK4ldC8kcCsDk/1NRpUEolOA9qqCV/F2/UngBk6rFVBNQksySmKm9DBBBq6qwdZkRKEnbLnAHnIoRpaqvSpxVqdphvcMTtpd+sjk3y+q6u9NFnurXpkAEvvdorej1WfayWjXXfSiOD4OCy0niouDlFBmv6u52WbK1dN/xcL+boh6B1euqBwUAdrHRjy2US4g5rEKx1Vq3TzH1n3O2t9bUZxxK6fs8Hji4/08brOXSBBY8RARxQVTl5ByT/LaXSXrAUngUcZevl6jFb61jfyt350HZSjBrEgnaMtLwdqw/Cq7CoMUcIjqSmHJf0ONS+b178pGYGMNRVua+rECkPdapghG7LTgwj75cFnR46L5sj+2nDQ6/H0BGuJJ2gA7k75r/MfXa3/jm5uVMaqx17xx0Yxj1aKbcAJxyX26T0HipH969R7Ww+JFSbP2xmLqnQwspEZGd13dZON5GVQZiJdtAm52RTs5EBk6nrykB/78K+iGozieoZY5pitzlqeyOKty10P2EUSO9TRoOOehWP/hNB14kJrqUTWfH/HttNpkhAful6fZN/mkZ+Yz7LP2MnUPtw+OM8+RpTC5AFAoLEjJF4kWK/lWN2HHfOJ8Da24eA== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230037)(1800799021)(376011)(36860700010)(82310400023);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2024 11:35:33.5242 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a754d114-3361-4798-ec6e-08dc8f8ac40d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6869 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen mlxsw_pci_cq_napi_setup() includes both NAPI initialization and enablement, similar to teardown function. Next patches will add support for page pool in mlxsw driver, then we use NAPI instance for page pool. Page pool initialization should be done before NAPI enablement, same for page pool destruction which should be done after NAPI disablement. As preparation, split NAPI setup/teardown into two steps, then page pool setup will be done between the phases. Signed-off-by: Amit Cohen Reviewed-by: Petr Machata Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index c0ced4d315f3..3b6afe3aa2a1 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -832,13 +832,10 @@ static void mlxsw_pci_cq_napi_setup(struct mlxsw_pci_queue *q, mlxsw_pci_napi_poll_cq_rx); break; } - - napi_enable(&q->u.cq.napi); } static void mlxsw_pci_cq_napi_teardown(struct mlxsw_pci_queue *q) { - napi_disable(&q->u.cq.napi); netif_napi_del(&q->u.cq.napi); } @@ -875,6 +872,7 @@ static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, if (err) return err; mlxsw_pci_cq_napi_setup(q, mlxsw_pci_cq_type(mlxsw_pci, q)); + napi_enable(&q->u.cq.napi); mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 2/7] mlxsw: pci: Store CQ pointer as part of RDQ structure Date: Tue, 18 Jun 2024 13:34:41 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|MW4PR12MB6778:EE_ X-MS-Office365-Filtering-Correlation-Id: 1fe50768-8b80-400a-cd2d-08dc8f8ac6d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|82310400023|376011|1800799021|36860700010; X-Microsoft-Antispam-Message-Info: tMdr5ueB/2YbAqZDwP+UMZOcwcZMV23W9519Czekcx2GYmeeYhE/NUQszq6KZbhg/eCSVNvM+wl4vHM70V1dGSROIBh0mMYAuDM/9VNMWQpUH3Ks0DpjPVveob35pCxx71RTDO00S6Wd9y3mbNsUtZ1NhLgZuH/BmjgHwEoae18kzb59ZuEHf8ToYNofUcFFHitUlzmzOKvvFMz4mBFPeC2534+h0U8HOyZeJRHqZ8445BkPOUXj91ZQf0yc5YI7e+OpgSqYP8vJnX00yN4s7+iSgxKRm87elsO8nLWBvaE4BRD59ykDzxzR51/+ltDq9HV8t9cmHlgP0T0azIn0YJFWbeCLWiiJQ0tif9H9gipoAZx/LOkKw2v1vuf309TH0xc93i12ydR34Imi7KYrzcd2vPS3nctFmyAtzAE3K7c4IxtGVzb2Oo82IlKH1jK2DFKwLoX1WkOMZn+gTPnXHHLnj2TtJD9qFdVZOe95NZfZdlAX77JCebmDhS1DziQbmqrXT1TogtFAnUjB6G3eK9qqwPnBfyisHw3k9qqeFfBRHuVusQ42FtPAz9U0s5Dc6DJVWtJGHR0Uaa1JEpuslcUVW0aKIcrTDyXlDNUSMoNXsDcauYLV77N0pCjEd0lWQbCj+tvdcNx81QvU+hwUx8i7LStj61vjJ0aWhcgtQ9RGZZQg+nLpNKDmnB6/6s0xF6jcx1KU73LF8t/mfVN/atspBRCL7bmEetILRXNkKBWYH8ijRqNougSVHQsuL8F2z/wIGGV7CO+mvDki4vd9Y6bp27wkK6/w4z/XzscesyekGV2sv5qtukzuZuuiKxkAyepMsF6JhxQeNaowpWCIV2m8pfMjZouod96RDrQWXbQPhx1xx4dU4fJUXl1c8Oz6MpCdntAG87e/A2QEHyHW7lJJtOuNJD2qq54Sfh99NrBLUUOPl8VibIlPNA2CV45OLRoxRQq4rotLLi8mIx8u4JhLivjzctPKaY8/82jifuwZJjtHizRkvkb40/4vhL/BI9Zdx3vbiFtXFeX/7C6eJnPfRS7hB1gJQ7kHUUdpAjZnDEOQp0VvWKnJ15/eakYANyVtSPp0f4GspOVxqvcVkMDZDv8m5INDP/0SLlHkz4gRiUsEhtIfhDbZP3pvTYQwSTQW6w78pa0trGG88Wo0d+rmI80fp2peyhyHJCeg09yVlllPTklHlMwkUinY012GKBdQPxbVr/oxXQQg+wKdXntOEIH++NLqh0TcRSVl0mQoMYQyfPhf9MV5KHGxSMux0q/knrTJw5R4W/cUv0OADXszxt9XGPbDlx7Jhcfv/RYGEM9zxmg2avR/ae1M5TwkUyVm1kwhTGBStoaTWlGn6JmZgX5BFT+j0pUw5cbPTRKBvgAdOroZ/VsLSjCIxrUAWn9vsy9hkO/hqzwnCPPmqQ== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230037)(82310400023)(376011)(1800799021)(36860700010);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2024 11:35:38.1961 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1fe50768-8b80-400a-cd2d-08dc8f8ac6d6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6778 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen Next patches will add support for page pool in mlxsw driver. Page pool will be used to allocate buffers for RDQ and will use NAPI instance of the appropriate CQ (RDQ is mapped 1:1 to CQ). To allow pool initialization as part of CQ init, when NAPI is initialized, page_pool structure will be as part of CQ structure. Later, the allocations for RDQ will be done from the pool in the appropriate CQ. To allow access to the appropriate pool, set CQ pointer as part of RDQ initialization. Signed-off-by: Amit Cohen Reviewed-by: Petr Machata Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 3b6afe3aa2a1..400c7af80404 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -92,6 +92,9 @@ struct mlxsw_pci_queue { struct { struct tasklet_struct tasklet; } eq; + struct { + struct mlxsw_pci_queue *cq; + } rdq; } u; }; @@ -434,6 +437,7 @@ static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, cq = mlxsw_pci_cq_get(mlxsw_pci, cq_num); cq->u.cq.dq = q; + q->u.rdq.cq = cq; mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); @@ -455,6 +459,7 @@ static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, elem_info = mlxsw_pci_queue_elem_info_get(q, i); mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); } + q->u.rdq.cq = NULL; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 3/7] mlxsw: pci: Initialize page pool per CQ Date: Tue, 18 Jun 2024 13:34:42 +0200 Message-ID: <02e5856ae7c572d4293ce6bb92c286ee6cfec800.1718709196.git.petrm@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37F:EE_|CH3PR12MB8511:EE_ X-MS-Office365-Filtering-Correlation-Id: b2f2b905-9a1b-4abf-ff2a-08dc8f8ac960 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|1800799021|82310400023|376011|36860700010; X-Microsoft-Antispam-Message-Info: bgINtzUy2AE7wfrGjYrHE9ssDiVEXBsWjRihJkrPbkW6bagwqHaHxoVEqd0nkOqvgIyE/QWwcV/Hmej/g+bs0C7x86rvDse7QtUmhmpwjig7v2IZo27/yiQmOyta+CDxmEOFofZxjTNxkuz4aogI2rho7dWls0T0BZ49EOdPMOmrGRgHqY8PDTrbwZdNc0yCb8XW+eUK6C6CqhRawHJwnjuw/QA55x4I0/Cz1j888RatxwKsXD++ItpcHO1MRqW9n2o30mXvYr/v8x3WtpoH3osSSLUIKsH/whLS6iFRTm2146OlAa8HvTypEofWU0Yd3KHA9epSqrq5FqggwgZ/oiO+qDFHUwkkkzocB95F4g7gHlDs5JTDufJt2b42H3PXsgA7+OLqNDkO7rq+v40bKxBoS16rTIl6YT3NdwVybLj9q9AbgMoCUVjOg8uZVBVqWvxerWH3IMz+84evbCWllKXiJn8bKTmWt0gpGKgKrcDgLtjQWl+O/+ixiA35JUOsfZJ+gb8feVbU20L1HzT24rhac0VZCSHwqe/MMMu1HEYb75CRIQ94DOoRaqz4iQQH3ZJIUWOB2BlbI9ET0DvQYY/i9qAAAlwjVjJHd0dPzcR5SWsjvMqDW9gf8Vni/cOKzC7rshb9IN2Iej6IytDmcpOF6hvdGvXBgpTqbBZAaXfQqIHTe1JeCYseHweYcOgbfe82yHOy9f39Meu7sU/CUY5muFAvF2A93M6L9W5hvXntWlNuIbibhnauqw537okDtgrcWHj2lhhUyDPn1YBYqCPVQdseVpDAc0v47P6WefvhZSVeQyckquIOI0qD98wNucCrDXfXxHyhPyf0ntV8OeCdz7vFTs0sKm/A0uKtuo05aCu1h8723Z984ES0MUAoZRvGoNw3z4rZ5IdMQpv8Necce9qvKXgC1D5prnEMBm6B4igK2MtJ3QBnJWVmGiLkpefPn3Ho3d4pxJr/cBoZHcDKBYeegB8RKXxZHGR5EL9eGq/qov+T7h3DAIwrxVnth1L37wk7NQZm/aqNZQLTD534GRW3ZBKCYE1yfrEekmf40PtqUq3toVW4fMcm9/a9bUVj5EWznXyaO5qI0FWavNJ/2eezYC6HQelJFcD1r44CtxN1aJ0lF864DhPgqvxkVaekTb8TTZOBxOHEzTW4dwnCoAYKXbhXSvY7MP/xbK+uJqYvTrKRdNtJ04Whki48J8iXW+sy+nAywCynK9CaGQjnY4DJQhx06lb+PE3LkCE+qpBM/839WXikX3/AUq5SpwaGhpo/fWwgRp4P1JD44NiWdZqJSlkrr4biGbkMVyi8q6vcSsCNA00AXCRo6lA7AF6PgNMeLsOSItLUaTVQgI+tAk/ysj+S6OBSIDPNcegIoceF8vqT9RqUYf6zclNMVLG4k7vR8+iFZbzbBoZl0w== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230037)(1800799021)(82310400023)(376011)(36860700010);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2024 11:35:42.5197 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2f2b905-9a1b-4abf-ff2a-08dc8f8ac960 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8511 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen Next patch will use page pool to allocate buffers for RDQ. Initialize page pool for each CQ, which is mapped 1:1 to RDQ. Page pool for each Rx queue enhances Rx side performance by reclaiming buffers back to each queue specific pool. When only one NAPI instance is the consumer of pages from page pool, it is recommended to pass it as part of 'page_pool_params', then page pool APIs will be done without special locks. mlxsw driver holds NAPI instance per CQ, so add page pool per CQ and use the existing NAPI instance. For now, pages are not allocated from the pool, next patch will use it. Some notes regarding 'page_pool_params': * Use PP_FLAG_DMA_MAP to allow page pool handles DMA mapping, for now do not use sync flag, as only the device writes to this memory and we read it only when it finishes writing there. This will probably be changed when we will support XDP. * Define 'order' according to maximum MTU and take into account software overhead. Some round up are done, which means that we allocate more pages than we really need. This can be improved later by using fragmented buffers. * Use pool_size = MLXSW_PCI_WQE_COUNT. This will be the size of 'ptr_ring', and should be the maximum amount of packets that page pool will allocate memory for. In our case, this is the queue size, defined as MLXSW_PCI_WQE_COUNT. Signed-off-by: Amit Cohen Reviewed-by: Petr Machata Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/Kconfig | 1 + drivers/net/ethernet/mellanox/mlxsw/pci.c | 60 ++++++++++++++++++++- 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/Kconfig b/drivers/net/ethernet/mellanox/mlxsw/Kconfig index a510bf2cff2f..74f7e27b490f 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/Kconfig +++ b/drivers/net/ethernet/mellanox/mlxsw/Kconfig @@ -33,6 +33,7 @@ config MLXSW_CORE_THERMAL config MLXSW_PCI tristate "PCI bus implementation for Mellanox Technologies Switch ASICs" depends on PCI && HAS_IOMEM && MLXSW_CORE + select PAGE_POOL default m help This is PCI bus implementation for Mellanox Technologies Switch ASICs. diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 400c7af80404..045f8b77698c 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "pci_hw.h" #include "pci.h" @@ -88,6 +89,7 @@ struct mlxsw_pci_queue { enum mlxsw_pci_cqe_v v; struct mlxsw_pci_queue *dq; struct napi_struct napi; + struct page_pool *page_pool; } cq; struct { struct tasklet_struct tasklet; @@ -338,6 +340,12 @@ static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci, mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num); } +#define MLXSW_PCI_SKB_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN) + +#define MLXSW_PCI_RX_BUF_SW_OVERHEAD \ + (MLXSW_PCI_SKB_HEADROOM + \ + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) + static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe, int index, char *frag_data, size_t frag_len, int direction) @@ -844,9 +852,47 @@ static void mlxsw_pci_cq_napi_teardown(struct mlxsw_pci_queue *q) netif_napi_del(&q->u.cq.napi); } +static int mlxsw_pci_cq_page_pool_init(struct mlxsw_pci_queue *q, + enum mlxsw_pci_cq_type cq_type) +{ + struct page_pool_params pp_params = {}; + struct mlxsw_pci *mlxsw_pci = q->pci; + struct page_pool *page_pool; + u32 max_pkt_size; + + if (cq_type != MLXSW_PCI_CQ_RDQ) + return 0; + + max_pkt_size = MLXSW_PORT_MAX_MTU + MLXSW_PCI_RX_BUF_SW_OVERHEAD; + pp_params.order = get_order(max_pkt_size); + pp_params.flags = PP_FLAG_DMA_MAP; + pp_params.pool_size = MLXSW_PCI_WQE_COUNT; + pp_params.nid = dev_to_node(&mlxsw_pci->pdev->dev); + pp_params.dev = &mlxsw_pci->pdev->dev; + pp_params.napi = &q->u.cq.napi; + pp_params.dma_dir = DMA_FROM_DEVICE; + + page_pool = page_pool_create(&pp_params); + if (IS_ERR(page_pool)) + return PTR_ERR(page_pool); + + q->u.cq.page_pool = page_pool; + return 0; +} + +static void mlxsw_pci_cq_page_pool_fini(struct mlxsw_pci_queue *q, + enum mlxsw_pci_cq_type cq_type) +{ + if (cq_type != MLXSW_PCI_CQ_RDQ) + return; + + page_pool_destroy(q->u.cq.page_pool); +} + static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, struct mlxsw_pci_queue *q) { + enum mlxsw_pci_cq_type cq_type = mlxsw_pci_cq_type(mlxsw_pci, q); int i; int err; @@ -876,17 +922,29 @@ static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num); if (err) return err; - mlxsw_pci_cq_napi_setup(q, mlxsw_pci_cq_type(mlxsw_pci, q)); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 4/7] mlxsw: pci: Use page pool for Rx buffers allocation Date: Tue, 18 Jun 2024 13:34:43 +0200 Message-ID: <1cf788a8f43c70aae6d526018ef77becb27ad6d3.1718709196.git.petrm@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449F:EE_|CH3PR12MB9456:EE_ X-MS-Office365-Filtering-Correlation-Id: a8cd99a3-60ec-40c8-91f7-08dc8f8acc8d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|82310400023|1800799021|376011|36860700010; X-Microsoft-Antispam-Message-Info: 68RVvxsvIuguEnJdO9NJXmTg7l8G2MjQAiECPFeWXg3xVEGRTqAOJeZnc2RwWrDh9E8p8jzmqLsCW+GwbXkeXfnZ7iVPS2kaXP/4GtnVyD5LLhIw5SEQr2Io8WKAbXBMddp2NHKgP2XAY5DckxbYXIvCCN/dyDWTV6Hi1QqZzR0xUng8nbGhc/8FGbYPe670GIWb+VZvpd4xqRzVUz0SrT9+muNkUws4Ad3OiOGyjBIuzxbC3MGRWrTN68MtEkxxDGR5U28UwMvbd7ncMa2bqA8gQ+e7dgVUQmR4lTXu5td71aejr+N8BCCt8F28DklJMqlHd2U1rSH6tpBRSq0aThouBrOVUQDH9YV1QwTzDbjPaVzoHkkJtto4WRX2Ge/YthooPox4z1ZOOF6ybfCHFVywM+Pgh+TqEiF+kYZ1RBV49mHUN8yqHBs6HzkCKovMDPpl7RVMZVI8x+NQMKGStkSInEV3Am7pjVB02o4RhyZoEeCStkhRm5mu48VlGbEQZJ0VAbOGbrUT2eNPkubHBM6ybh8YoJspkuUkJ4g0/jI3vI382XDvyEMRWEBK7MzzNEk7j5Pzoc3kv3MXSD6sePDl78pIWhml0KgLuP/uMjWdX+S6qF8B/Uy57hzX4nzFN14Ozs0OqUofSyFa+PZXsvo0Roui9jUeF/MOIJIxIwXgxOetqLOb7S16hUihz4VOsLouglcGpDcXpjwPLXqjZHYxRDNMVN8278KE3nY4KOf75aPAdABQZCS847G76lCGoPI5bOoxRc47qmtkAP1Nls98pwwAcPvTIRMXxxpm6UzTW1u+Jkbhuv/oX7zbnFoQ6B7DR4XwfK8EO/mqsh4dMzG94QnwelgO9RYtemGLVGg9yVQFezpP6H0zNZ0UzUjhjmkfyRogb6KmxXQjrzc8VM5f1e9/Ib/V5TVNFJOdZZHUW2sqvajBbprPK7re/pOsjJTroTZ5nLz9/BSgUKaR261eheKOaNISqeodpK/biDsB/3wmltX6sbMGDVPm5hdkuwiUUO1uuRcOSJA14ED7FUMj/pq2PdOhEa1ChNU9NoEAzQE2ir1v4AO8ssOzN4ccTPldXID0kS1YOG28YpEv3E8o8Ii+ESBUeFKVIv8+injJWpkahoyxsAzaBac4z3YrwsF0n0B4E9sA+mRcXZDhGgas4DpfPT8t/4EqiZ7/q4MhHP+YtZKgBXJA5/mnbnq+trUkrRh8UvbPR7ErK3nmJKgrifhcAi0GeX7tlh5th+Lux4JMDkeWpKGeFj2SDAuBw+fGTfbuYlhE9eEbONiJXld7+iCzl6mb0pqspEZNJuxUmSvYIEo2T6mozi0AC6m4RNN2gFeaQ6eYqfV35nlq2++3InS9neSGMtk4TnyJFSeLoD87b4JtH/41TR7pumcutFnrKJMo0yV/DNYzIxKy1g== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230037)(82310400023)(1800799021)(376011)(36860700010);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2024 11:35:47.7825 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8cd99a3-60ec-40c8-91f7-08dc8f8acc8d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9456 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen As part of driver init, all Rx queues are filled with buffers for hardware usage. Later, when a packet is received, a new buffer should be allocated to be used by hardware instead of the received buffer. Packet's processing time includes allocation time, which can be improved using page pool. Using page pool, DMA mapping is done only for first allocation of buffers. As subsequent buffers allocation avoid DMA mapping, it results in performance improvement. The purpose of page pool is to allocate pages fast from cache without locking. This lockless guarantee naturally comes from running under a NAPI. Use page pool to allocate the data buffer only, so hardware will use it to fill the packet. At completion time, attach the data buffer (now filled with packet payload) to new SKB which is allocated around the received buffer. SKB building at completion time prevents cache miss for each packet, as now the SKB is allocated right before packets will be handled by networking stack. Page pool for each Rx queue enhances Rx side performance by reclaiming buffers back to each queue specific pool. This change significantly improves driver performance, CPU can handle about 345% of the packets per second it previously handled. Signed-off-by: Amit Cohen Reviewed-by: Petr Machata Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 103 ++++++++++++++-------- 1 file changed, 64 insertions(+), 39 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 045f8b77698c..711b12aecfb7 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -62,6 +62,7 @@ struct mlxsw_pci_mem_item { }; struct mlxsw_pci_queue_elem_info { + struct page *page; char *elem; /* pointer to actual dma mapped element mem chunk */ union { struct { @@ -346,6 +347,19 @@ static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci, (MLXSW_PCI_SKB_HEADROOM + \ SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) +static void +mlxsw_pci_wqe_rx_frag_set(struct mlxsw_pci *mlxsw_pci, struct page *page, + char *wqe, int index, size_t frag_len) +{ + dma_addr_t mapaddr; + + mapaddr = page_pool_get_dma_addr(page); + mapaddr += MLXSW_PCI_SKB_HEADROOM; + + mlxsw_pci_wqe_address_set(wqe, index, mapaddr); + mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len); +} + static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe, int index, char *frag_data, size_t frag_len, int direction) @@ -375,43 +389,46 @@ static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe, dma_unmap_single(&pdev->dev, mapaddr, frag_len, direction); } -static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci, - struct mlxsw_pci_queue_elem_info *elem_info, - gfp_t gfp) +static struct sk_buff *mlxsw_pci_rdq_build_skb(struct page *page, + u16 byte_count) { + void *data = page_address(page); + unsigned int allocated_size; + struct sk_buff *skb; + + allocated_size = page_size(page); + skb = napi_build_skb(data, allocated_size); + if (unlikely(!skb)) + return ERR_PTR(-ENOMEM); + + skb_reserve(skb, MLXSW_PCI_SKB_HEADROOM); + skb_put(skb, byte_count); + return skb; +} + +static int mlxsw_pci_rdq_page_alloc(struct mlxsw_pci_queue *q, + struct mlxsw_pci_queue_elem_info *elem_info) +{ + struct mlxsw_pci_queue *cq = q->u.rdq.cq; size_t buf_len = MLXSW_PORT_MAX_MTU; char *wqe = elem_info->elem; - struct sk_buff *skb; - int err; + struct page *page; - skb = __netdev_alloc_skb_ip_align(NULL, buf_len, gfp); - if (!skb) + page = page_pool_dev_alloc_pages(cq->u.cq.page_pool); + if (unlikely(!page)) return -ENOMEM; - err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, - buf_len, DMA_FROM_DEVICE); - if (err) - goto err_frag_map; - - elem_info->u.rdq.skb = skb; + mlxsw_pci_wqe_rx_frag_set(q->pci, page, wqe, 0, buf_len); + elem_info->page = page; return 0; - -err_frag_map: - dev_kfree_skb_any(skb); - return err; } -static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci, - struct mlxsw_pci_queue_elem_info *elem_info) +static void mlxsw_pci_rdq_page_free(struct mlxsw_pci_queue *q, + struct mlxsw_pci_queue_elem_info *elem_info) { - struct sk_buff *skb; - char *wqe; + struct mlxsw_pci_queue *cq = q->u.rdq.cq; - skb = elem_info->u.rdq.skb; - wqe = elem_info->elem; - - mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); - dev_kfree_skb_any(skb); + page_pool_put_page(cq->u.cq.page_pool, elem_info->page, -1, false); } static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, @@ -452,7 +469,7 @@ static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, for (i = 0; i < q->count; i++) { elem_info = mlxsw_pci_queue_elem_info_producer_get(q); BUG_ON(!elem_info); - err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info, GFP_KERNEL); + err = mlxsw_pci_rdq_page_alloc(q, elem_info); if (err) goto rollback; /* Everything is set up, ring doorbell to pass elem to HW */ @@ -465,7 +482,7 @@ static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, rollback: for (i--; i >= 0; i--) { elem_info = mlxsw_pci_queue_elem_info_get(q, i); - mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); + mlxsw_pci_rdq_page_free(q, elem_info); } q->u.rdq.cq = NULL; cq->u.cq.dq = NULL; @@ -483,7 +500,7 @@ static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci, mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); for (i = 0; i < q->count; i++) { elem_info = mlxsw_pci_queue_elem_info_get(q, i); - mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); + mlxsw_pci_rdq_page_free(q, elem_info); } } @@ -618,26 +635,38 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, { struct pci_dev *pdev = mlxsw_pci->pdev; struct mlxsw_pci_queue_elem_info *elem_info; + struct mlxsw_pci_queue *cq = q->u.rdq.cq; struct mlxsw_rx_info rx_info = {}; - char wqe[MLXSW_PCI_WQE_SIZE]; struct sk_buff *skb; + struct page *page; u16 byte_count; int err; elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); - skb = elem_info->u.rdq.skb; - memcpy(wqe, elem_info->elem, MLXSW_PCI_WQE_SIZE); if (q->consumer_counter++ != consumer_counter_limit) dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n"); - err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info, GFP_ATOMIC); + byte_count = mlxsw_pci_cqe_byte_count_get(cqe); + if (mlxsw_pci_cqe_crc_get(cqe_v, cqe)) + byte_count -= ETH_FCS_LEN; + + page = elem_info->page; + + err = mlxsw_pci_rdq_page_alloc(q, elem_info); if (err) { - dev_err_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n"); + dev_err_ratelimited(&pdev->dev, "Failed to alloc page\n"); goto out; } - mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); + skb = mlxsw_pci_rdq_build_skb(page, byte_count); + if (IS_ERR(skb)) { + dev_err_ratelimited(&pdev->dev, "Failed to build skb for RDQ\n"); + page_pool_recycle_direct(cq->u.cq.page_pool, page); + goto out; + } + + skb_mark_for_recycle(skb); if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) { rx_info.is_lag = true; @@ -670,10 +699,6 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, mlxsw_pci_skb_cb_ts_set(mlxsw_pci, skb, cqe_v, cqe); - byte_count = mlxsw_pci_cqe_byte_count_get(cqe); - if (mlxsw_pci_cqe_crc_get(cqe_v, cqe)) - byte_count -= ETH_FCS_LEN; - skb_put(skb, byte_count); mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info); out: From patchwork Tue Jun 18 11:34:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13702132 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2085.outbound.protection.outlook.com [40.107.236.85]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E809815920B for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 5/7] mlxsw: pci: Optimize data buffer access Date: Tue, 18 Jun 2024 13:34:44 +0200 Message-ID: <1fa07c510890866a6f201163ab7e78890ba28b3b.1718709196.git.petrm@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37C:EE_|SN7PR12MB6886:EE_ X-MS-Office365-Filtering-Correlation-Id: 76f5ae5c-8ad5-41e1-7f2c-08dc8f8acf65 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|376011|82310400023|1800799021; X-Microsoft-Antispam-Message-Info: hhWixaOp6xiQccFKldfhXPq0rNnOoe5BVxioUdMboSrB5K8Us3vtuJkNbUz1QgyIo04L9XG6auLssyQM3B4l3bBXGqKBdt5c5t1aN1KTF6ihMBZbqV83F8Smp/9NXSViBYA/d/0Q2xb6UES4WTZWb0yMhvvuLPWilt4qxNyDuRA1zno6TQN2CS3WFDQUVgDJsMNAfG8i2j9PeeHMT+cKtKMUCnjze+ZABdQrDZiUW7/m0rnHvz4KpPbCTVAb/sWerpa+7ohCG53sAfaSVNLnodfc3qodjSsiVWiuHdo2BW+klXDJo3nKEG/G8w227Yr6czXjhQSln0bzY/wy5cSvt0BxCqiSH02CGSpKZDks3o6Weiltbbvd7JFum9+SXAax43+eZoduFLUOYKa7ZPF8R2ik98EK7nx1OuHCwMWRx3zAjsqvTaCRw/rOe8EXhxZKAuEXprdA1pQDeiFukey+vfqvKRNYgLslJP5lwNM+Vv18mZv7tHi+DLfx4ctwYbYYgW1pFI2Fy+PT6jYpY05dm7YpDsrUHypONynsHEjQK9oVnIPz60g15giqMyFMTUed8hi02rrpaaFtp7RleAoutpgUNMi5npVrMYvibtBNeW/a9AnpCORvAnywjYmVm4Lf3vAmiBdA/sP1RU8OzHF3NhRTiH9j3jNEvFMGwrNnH8Rr84iAspB57jt6kQzZ2Icw3pbxrg6DSdElTY8vxmtdMY7iIlSCYRWhKbr0EdxkWJOhBV8r2M7Qf9srdkryVSd1uW8OBX7sD6sFDLMy6It0zuVomhdO2KfnSL00bs+23mxQCnU09KvRbOUDB0R/0NfvDQyavzWzTWYUevwhUjrwLVyZnHgfssFK+9O1A0Him2+mgpJFjPkwiup83UVC5g8jsjWWswTiGlWKScejtNw2vxUkcSQjfb1Y786n3ISCc4ielVnR7YKF3KA6BiRc+QrUusgdKV/XzWIIGN7k9iqV3IZRJ7OKiyKLakGRB9RABPsIkuaRSv1f9DHjd7vqQMpV1Gq54yrsos2CUnEK9Lmu24wx6v9dyT1iMN/ymNHb3juKPg/wfiJjYY5sFI/2lylhMUXxER0/UErolj35kVJIhZehRPhz12D/kGwzAn4vi7K0Pj9yycheOLKMOe77eUOG12QbFiWB14Q2RJ/S0yxgTnWiK5nrrbTYNiGtrjtrna1ITyVOVClm2dWmokt+bOufRR32Szdsa9Nv2n7twg7IktwUgfYh41/ZUmtKHDRscepoeW0/hNOZrEdGNMiqWgfssp3fGnZwRePG9eTNw3u7I8HTyCP1HspvOKd5sXX6S3u4aYAJqBDHFPhkFVB+X0e69j0zQhKWczlLFnENpKQXjHkjhFk8UdHek/ELX7jg8MWJ9m8D3lE2DOCT3F7vmtll00qcKFm/PNbC/dCLKu/sug== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230037)(36860700010)(376011)(82310400023)(1800799021);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2024 11:35:52.5999 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 76f5ae5c-8ad5-41e1-7f2c-08dc8f8acf65 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6886 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen Before accessing data buffer, call net_prefetch() to load it into the cache. This change improves driver performance, CPU can handle about 7.1% more packets per second. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 711b12aecfb7..c380b355b249 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -396,6 +396,7 @@ static struct sk_buff *mlxsw_pci_rdq_build_skb(struct page *page, unsigned int allocated_size; struct sk_buff *skb; + net_prefetch(data); allocated_size = page_size(page); skb = napi_build_skb(data, allocated_size); if (unlikely(!skb)) From patchwork Tue Jun 18 11:34:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13702133 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2064.outbound.protection.outlook.com [40.107.94.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C28F515278F for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 6/7] mlxsw: pci: Do not store SKB for RDQ elements Date: Tue, 18 Jun 2024 13:34:45 +0200 Message-ID: <23a531008936dc9a1a298643fb1e4f9a7b8e6eb3.1718709196.git.petrm@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37C:EE_|IA1PR12MB6411:EE_ X-MS-Office365-Filtering-Correlation-Id: ee2a559a-c721-41cf-13a7-08dc8f8ad201 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|82310400023|376011|1800799021; X-Microsoft-Antispam-Message-Info: FG+M5Oh6pTjz9qrted1zCbBsaZejXdr22zHs0VajA98RLXHchobzcSQSq43BsTqdBbC8o0BMzeK0OVfIEB57Nf7gipCAptE4GCslg8UqRjjxEXzzAoWp447YCsrg8AuLr3wBpXz1zzU8D48pSCk8/c8NvGOvQjrU6tYyFgV8XDrExf8pDUcLG+6FkIfP6BLicyWI2ai9PW+jPG7DLIaTM4WOJOV4aPM7OBS4UB8edco3+uwwEZPcxWDgpSjMo0xUNyTRsezBx+mU9NdS2bFMFn4vzOyWxymkDxorw4II9qk+3qczEsF61pKqSzaLCW6KitR4w7qjHH5YYNXKUYZIcvD8g6DCM6DYSvy+MLzTs1DE8uacbxksg8fvWPzR2wZJA4gxsWm6h7ktBegiI/Mi87XlBWHMS3l78DrMs7soPfrkFlOiC22X7Zx1hQZKJXc4WI6+tQfOdTVO3lm7xj273/eBGVPA6gGlf4VmLZtuuENruXkw3DeFkGktNivKWoptj7+jVStYLqeWGLZGcI0oXZLX4HeanBx9vhTndeHplPX/4X4N4oaSDhucofqCNP172smopYqqb+pOOPeZP+TC0tz7KxcXXCpRVfB2Hf2FgDef5BR6qcnjsxHl5uEUgeuBJhYsG2TSVU29AsB9nNAZZ2VYPtg1qy8FRrOyLrdCXH2yZGNVCtnlTrd3trS3LbhJ4a0UG6tZvW3J0HWUqD9iQWHvidLZz9ly9G2g8CxOih8PGpjry43X5NcrungeCWRdV0kfQoUtyD07LJXfwfav3AmKo8QZPkz0h6TqdLn46g87b/YV9g5H1uymK0/ZofkM1EEOG3uFmQsEOAJjWhAvdMpLT4zUFrLCFsvUgaMcKuLZVHA7XtR7PtPRSZXTdDmc4rBkf2dJeFZvlchSTYFwUYegux4lpnjKeMhOt1zS4z3y0rSEeZbGX6WDk0akNL00YZThlZzQ5WYvW8UQZ9bQ3UXYS2jdZJAoIwryf7jGVHu+FGWVVstFx8lgtRw/tZyxcpAXUUhFUHx66+GIGLmnxGKwB3pwiFLu0Lvt9tlJihRc2a0fR31+bPgy1hlBHrtcIXSjpkQ/6vXWqvZfrkKCLOu8Oxg+2kSE2r1QL9Knu9HAqXAEmY0VOn73MPRwuJQfeTcq/I8mmrSs8ciy7O2G7G9xTIy4oSGsSkdYlqD8814GSjodGfNbCeWpqEyPFdioHsFnI3PNnAYO7HarpzRan5Ie7X0y2cxLYc0I7IY/r+7sgtW9tm60SN+6bHGi2k+Dh4kkV8mKFNW8RQEuo70KsRsqkjtahqwj3ef3DDD0zmj1Sl9utRbER9y8Of9E1yMlv1JmrJcszQ8e68yE0QvTWxQD1qiQ24U/0zc90al+pbss9xCQPT2g0JnT1R38WDSVdJWKDi5EDgmkmbD4MqRsdQ== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230037)(36860700010)(82310400023)(376011)(1800799021);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2024 11:35:56.9749 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee2a559a-c721-41cf-13a7-08dc8f8ad201 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6411 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen The previous patch used page pool to allocate buffers for RDQ. With this change, 'elem_info->u.rdq.skb' is not used anymore, as we do not allocate SKB before getting the packet, we hold page pointer and build the SKB around it once packet is received. Remove the union and store SKB pointer for SDQ only. Signed-off-by: Amit Cohen Reviewed-by: Petr Machata Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index c380b355b249..498b0867f9aa 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -64,14 +64,9 @@ struct mlxsw_pci_mem_item { struct mlxsw_pci_queue_elem_info { struct page *page; char *elem; /* pointer to actual dma mapped element mem chunk */ - union { - struct { - struct sk_buff *skb; - } sdq; - struct { - struct sk_buff *skb; - } rdq; - } u; + struct { + struct sk_buff *skb; + } sdq; }; struct mlxsw_pci_queue { @@ -557,8 +552,8 @@ static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci, spin_lock(&q->lock); elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); - tx_info = mlxsw_skb_cb(elem_info->u.sdq.skb)->tx_info; - skb = elem_info->u.sdq.skb; + tx_info = mlxsw_skb_cb(elem_info->sdq.skb)->tx_info; + skb = elem_info->sdq.skb; wqe = elem_info->elem; for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); @@ -573,7 +568,7 @@ static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci, if (skb) dev_kfree_skb_any(skb); - elem_info->u.sdq.skb = NULL; + elem_info->sdq.skb = NULL; if (q->consumer_counter++ != consumer_counter_limit) dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n"); @@ -2019,7 +2014,7 @@ static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb, goto unlock; } mlxsw_skb_cb(skb)->tx_info = *tx_info; - elem_info->u.sdq.skb = skb; + elem_info->sdq.skb = skb; wqe = elem_info->elem; mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */ From patchwork Tue Jun 18 11:34:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13702134 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2054.outbound.protection.outlook.com [40.107.243.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28FE915AD96 for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 7/7] mlxsw: pci: Use napi_consume_skb() to free SKB as part of Tx completion Date: Tue, 18 Jun 2024 13:34:46 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449E:EE_|IA1PR12MB8556:EE_ X-MS-Office365-Filtering-Correlation-Id: 80485b49-5549-4f53-ae2c-08dc8f8ad43b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|1800799021|376011|82310400023|36860700010; X-Microsoft-Antispam-Message-Info: 27AdbKv7U0oaQgQS+AUliqZC8vGzHGfE5Slqt5VnFDMnDsdZw6Tpr9fbrHkfV4icBGsimhBZb2J4ZUkB9g5zbGoymHBczqYqWiiv08S6kUg5w+wmy3tk6vB64JAEpdAwMgYmEoc/hz3FGrzgEzkNLGMSvYkoC4KKHvigD9/jRzSPTypOglaeLlmUrz9+A2SWvb37RCskdglTB/sgMxGwSj8/8XVcIkUO/bAVqkFAJX4a67SNS+O8FHYNRe6MEE+qNjItQz9WD6Ynwzqin/AXwcTBfo8JPNIj1QPole42tUqmoE/b642XhPKTMEmHdhjFwd6uzAPir/mNE4ESroGDrt1x2J+PNoyKyNiZQTo/xmflo+YQzhONKcsZamvbtkyLS5MXAiQ0q0IxV+75Juwqea1xOS+UsK9nNpt4vfswpcV0l/IHZMAO9EoP4aqxzC1fS1HWG9UB/bHsSYI4tFzsUot3bJ5tSZC8vHrUeLuzTWUz3bK8l5BCoaabuUSWM29EBsx4yKfdanySsaJpsIgIM0Id0TluIxKHnr+PUnfozDRXI9jy3TT6CY2M/Lyk3JqKfu9+L51v4bPsGzT9HaAoiRbDVEH6DQUMvX/R3nbI5hPBkscItj1vZ+fn+IZx6CZp+HL5i2+4xn4IoD+XZceAnYjRLQanRQXjtoOWpfuOBYR6OTIrEnt9OY1R9subxfh+98az/m/6Oksq7qgGmTgf1/cd4NwYvtHi0Z/k/GbmeN4nLIxSBIY+RnBIRaUKutcrtPJyeA7qbEAgEf4+IrpI0hGbN/Nd939pRzWi3nKbriIPeiZfqTJoNTh6yPNh2VdKIRBjG4BSFcDeXHGyQ0RVH3YIek2aj6r2GNNDhNguZR4NLhMytO84Uo9R2PgXyhvFQlwmtcGdJdovo139X3NY+ZKbHKWqYk2sGE6VbieqFVeBL3+FJBx/U172r6T3LKcTeq4YmmpHxwhOCcHpvKRAAKDSUjG5boinZ8FY0uLnSiR1rHfBRO685m3jHnsc/F196BgmHtTPSLzsfJjo4DAuYjaX8cOgUoBChriqJkbJdno3KbFNDRqKXYBeP3EtEIGzNIePfFGugLu0AhO8BaDN21kM+i4CE7wuW8Kkxjb3sRrwY6Uky/xOfvhvLF+PWtTdAqAMtfn31N8c60Y6AIB46oNIXc0LYcR9p8ByyyWvix5w3KBO4sB32mnwcbOxDEA3bOMj8FjvIuq3OMeR2/3C0bAmcCVcKdAE9KqFOL9V10XXdMIGSr5T9wl79HVkWaIz6pd4ycn9iLOINFTWJkolYfcRFt0/Vfr7964J18LWtNEwtoInb8MLA9MQIg/k36EX+lFgK+CnRfG5YVkIEUvY0ovMCNzxnA4qCgvoBNmplc6jAnMmoyzyP1A8O5rdpk8x58+SFXE4Q3VZ4n+Jk45cNg== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230037)(1800799021)(376011)(82310400023)(36860700010);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2024 11:36:00.6832 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 80485b49-5549-4f53-ae2c-08dc8f8ad43b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8556 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen Currently, as part of Tx completion, the driver calls dev_kfree_skb_any() to free the SKB. For this flow, the correct function is napi_consume_skb(). This function and dev_consume_skb_any() were added to be used for consumed SKBs, which were not dropped, so the skb:kfree_skb tracepoint is not triggered, and we can get better diagnostics about dropped packets. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 498b0867f9aa..2fe29dba8751 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -541,7 +541,7 @@ static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci, struct mlxsw_pci_queue *q, u16 consumer_counter_limit, enum mlxsw_pci_cqe_v cqe_v, - char *cqe) + char *cqe, int budget) { struct pci_dev *pdev = mlxsw_pci->pdev; struct mlxsw_pci_queue_elem_info *elem_info; @@ -567,7 +567,7 @@ static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci, } if (skb) - dev_kfree_skb_any(skb); + napi_consume_skb(skb, budget); elem_info->sdq.skb = NULL; if (q->consumer_counter++ != consumer_counter_limit) @@ -819,7 +819,7 @@ static int mlxsw_pci_napi_poll_cq_tx(struct napi_struct *napi, int budget) mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq, - wqe_counter, q->u.cq.v, ncqe); + wqe_counter, q->u.cq.v, ncqe, budget); work_done++; }