From patchwork Tue Jun 18 14:40:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxwell Bland X-Patchwork-Id: 13702471 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D642C2BB85 for ; Tue, 18 Jun 2024 14:40:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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Tue, 18 Jun 2024 14:40:12 +0000 (UTC) Received: from ilclasset02 (ilclasset02.mot.com [100.64.49.13]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: mbland) by va32lmmrp01.lenovo.com (Postfix) with ESMTPSA id 4W3Ttg5fB5z2VZRs; Tue, 18 Jun 2024 14:40:11 +0000 (UTC) Date: Tue, 18 Jun 2024 09:40:10 -0500 From: Maxwell Bland To: linux-mm@kvack.org Cc: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Ard Biesheuvel , Mark Rutland , Christophe Leroy , Maxwell Bland , Alexandre Ghiti , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/5] mm: add ARCH_SUPPORTS_NON_LEAF_PTDUMP Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Proofpoint-GUID: blkS0LT6wZdY1-TTwIlfF-qhh7xDcsXA X-Proofpoint-ORIG-GUID: blkS0LT6wZdY1-TTwIlfF-qhh7xDcsXA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-18_02,2024-06-17_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 mlxscore=0 spamscore=0 phishscore=0 malwarescore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 mlxlogscore=618 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406180110 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240618_074039_221529_63CE9850 X-CRM114-Status: GOOD ( 15.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Provide a Kconfig option indicating if note_page can be called for intermediate page directories during ptdump. Signed-off-by: Maxwell Bland --- mm/Kconfig.debug | 9 +++++++++ mm/ptdump.c | 21 +++++++++++++-------- 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/mm/Kconfig.debug b/mm/Kconfig.debug index afc72fde0f03..6af5ecfdef93 100644 --- a/mm/Kconfig.debug +++ b/mm/Kconfig.debug @@ -201,6 +201,15 @@ config PTDUMP_DEBUGFS If in doubt, say N. +config ARCH_SUPPORTS_NON_LEAF_PTDUMP + bool "Include intermediate directory entries in pagetable dumps" + default n + help + Enable the inclusion of intermediate page directory entries in calls + to the ptdump API. Once an architecture defines correct ptdump + behavior for PGD, PUD, P4D, and PMD entries, this config can be + selected. + config HAVE_DEBUG_KMEMLEAK bool diff --git a/mm/ptdump.c b/mm/ptdump.c index 106e1d66e9f9..6180708669fe 100644 --- a/mm/ptdump.c +++ b/mm/ptdump.c @@ -41,10 +41,11 @@ static int ptdump_pgd_entry(pgd_t *pgd, unsigned long addr, if (st->effective_prot) st->effective_prot(st, 0, pgd_val(val)); - if (pgd_leaf(val)) { + if (IS_ENABLED(CONFIG_ARCH_SUPPORTS_NON_LEAF_PTDUMP) || pgd_leaf(val)) st->note_page(st, addr, 0, pgd_val(val)); + + if (pgd_leaf(val)) walk->action = ACTION_CONTINUE; - } return 0; } @@ -64,10 +65,11 @@ static int ptdump_p4d_entry(p4d_t *p4d, unsigned long addr, if (st->effective_prot) st->effective_prot(st, 1, p4d_val(val)); - if (p4d_leaf(val)) { + if (IS_ENABLED(CONFIG_ARCH_SUPPORTS_NON_LEAF_PTDUMP) || pgd_leaf(val)) st->note_page(st, addr, 1, p4d_val(val)); + + if (p4d_leaf(val)) walk->action = ACTION_CONTINUE; - } return 0; } @@ -87,10 +89,11 @@ static int ptdump_pud_entry(pud_t *pud, unsigned long addr, if (st->effective_prot) st->effective_prot(st, 2, pud_val(val)); - if (pud_leaf(val)) { + if (IS_ENABLED(CONFIG_ARCH_SUPPORTS_NON_LEAF_PTDUMP) || pgd_leaf(val)) st->note_page(st, addr, 2, pud_val(val)); + + if (pud_leaf(val)) walk->action = ACTION_CONTINUE; - } return 0; } @@ -108,10 +111,12 @@ static int ptdump_pmd_entry(pmd_t *pmd, unsigned long addr, if (st->effective_prot) st->effective_prot(st, 3, pmd_val(val)); - if (pmd_leaf(val)) { + + if (IS_ENABLED(CONFIG_ARCH_SUPPORTS_NON_LEAF_PTDUMP) || pgd_leaf(val)) st->note_page(st, addr, 3, pmd_val(val)); + + if (pmd_leaf(val)) walk->action = ACTION_CONTINUE; - } return 0; } From patchwork Tue Jun 18 14:40:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxwell Bland X-Patchwork-Id: 13702472 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31F64C27C4F for ; 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Tue, 18 Jun 2024 14:40:51 +0000 (GMT) Received: from ilclmmrp02.lenovo.com (ilclmmrp02.mot.com [100.65.83.26]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by va32lpfpp02.lenovo.com (Postfix) with ESMTPS id 4W3TvQ06ymz50TkT; Tue, 18 Jun 2024 14:40:50 +0000 (UTC) Received: from ilclasset02 (ilclasset02.mot.com [100.64.49.13]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: mbland) by ilclmmrp02.lenovo.com (Postfix) with ESMTPSA id 4W3TvP5ry1z3p6jp; Tue, 18 Jun 2024 14:40:49 +0000 (UTC) Date: Tue, 18 Jun 2024 09:40:48 -0500 From: Maxwell Bland To: linux-mm@kvack.org Cc: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Ard Biesheuvel , Mark Rutland , Christophe Leroy , Maxwell Bland , Alexandre Ghiti , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/5] arm64: non leaf ptdump support Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Proofpoint-ORIG-GUID: kmBwrD3JLnyF3RFV3h1ScHXshTVxVoVj X-Proofpoint-GUID: kmBwrD3JLnyF3RFV3h1ScHXshTVxVoVj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-18_02,2024-06-17_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 mlxscore=0 impostorscore=0 phishscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=914 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406180110 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240618_074115_428633_7C59E069 X-CRM114-Status: GOOD ( 22.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Separate the pte_bits used in ptdump from pxd_bits used by pmd, p4d, pud, and pgd descriptors, thereby adding support for printing key intermediate directory protection bits, such as PXNTable, and enable the associated support Kconfig option. Signed-off-by: Maxwell Bland --- arch/arm64/Kconfig | 1 + arch/arm64/mm/ptdump.c | 140 ++++++++++++++++++++++++++++++++++++----- 2 files changed, 125 insertions(+), 16 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 5d91259ee7b5..f4c3290160db 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -98,6 +98,7 @@ config ARM64 select ARCH_SUPPORTS_NUMA_BALANCING select ARCH_SUPPORTS_PAGE_TABLE_CHECK select ARCH_SUPPORTS_PER_VMA_LOCK + select ARCH_SUPPORTS_NON_LEAF_PTDUMP select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT select ARCH_WANT_DEFAULT_BPF_JIT diff --git a/arch/arm64/mm/ptdump.c b/arch/arm64/mm/ptdump.c index 6986827e0d64..8f0b459c13ed 100644 --- a/arch/arm64/mm/ptdump.c +++ b/arch/arm64/mm/ptdump.c @@ -24,6 +24,7 @@ #include #include #include +#include #define pt_dump_seq_printf(m, fmt, args...) \ @@ -105,11 +106,6 @@ static const struct prot_bits pte_bits[] = { .val = PTE_CONT, .set = "CON", .clear = " ", - }, { - .mask = PTE_TABLE_BIT, - .val = PTE_TABLE_BIT, - .set = " ", - .clear = "BLK", }, { .mask = PTE_UXN, .val = PTE_UXN, @@ -143,34 +139,129 @@ static const struct prot_bits pte_bits[] = { } }; +static const struct prot_bits pxd_bits[] = { + { + .mask = PMD_SECT_VALID, + .val = PMD_SECT_VALID, + .set = " ", + .clear = "F", + }, { + .mask = PMD_TABLE_BIT, + .val = PMD_TABLE_BIT, + .set = "TBL", + .clear = "BLK", + }, { + .mask = PMD_SECT_USER, + .val = PMD_SECT_USER, + .set = "USR", + .clear = " ", + }, { + .mask = PMD_SECT_RDONLY, + .val = PMD_SECT_RDONLY, + .set = "ro", + .clear = "RW", + }, { + .mask = PMD_SECT_S, + .val = PMD_SECT_S, + .set = "SHD", + .clear = " ", + }, { + .mask = PMD_SECT_AF, + .val = PMD_SECT_AF, + .set = "AF", + .clear = " ", + }, { + .mask = PMD_SECT_NG, + .val = PMD_SECT_NG, + .set = "NG", + .clear = " ", + }, { + .mask = PMD_SECT_CONT, + .val = PMD_SECT_CONT, + .set = "CON", + .clear = " ", + }, { + .mask = PMD_SECT_PXN, + .val = PMD_SECT_PXN, + .set = "NX", + .clear = "x ", + }, { + .mask = PMD_SECT_UXN, + .val = PMD_SECT_UXN, + .set = "UXN", + .clear = " ", + }, { + .mask = PMD_TABLE_PXN, + .val = PMD_TABLE_PXN, + .set = "NXTbl", + .clear = " ", + }, { + .mask = PMD_TABLE_UXN, + .val = PMD_TABLE_UXN, + .set = "UXNTbl", + .clear = " ", + }, { + .mask = PTE_GP, + .val = PTE_GP, + .set = "GP", + .clear = " ", + }, { + .mask = PMD_ATTRINDX_MASK, + .val = PMD_ATTRINDX(MT_DEVICE_nGnRnE), + .set = "DEVICE/nGnRnE", + }, { + .mask = PMD_ATTRINDX_MASK, + .val = PMD_ATTRINDX(MT_DEVICE_nGnRE), + .set = "DEVICE/nGnRE", + }, { + .mask = PMD_ATTRINDX_MASK, + .val = PMD_ATTRINDX(MT_NORMAL_NC), + .set = "MEM/NORMAL-NC", + }, { + .mask = PMD_ATTRINDX_MASK, + .val = PMD_ATTRINDX(MT_NORMAL), + .set = "MEM/NORMAL", + }, { + .mask = PMD_ATTRINDX_MASK, + .val = PMD_ATTRINDX(MT_NORMAL_TAGGED), + .set = "MEM/NORMAL-TAGGED", + } +}; + struct pg_level { const struct prot_bits *bits; char name[4]; int num; u64 mask; + unsigned long size; }; static struct pg_level pg_level[] __ro_after_init = { { /* pgd */ .name = "PGD", - .bits = pte_bits, - .num = ARRAY_SIZE(pte_bits), + .bits = pxd_bits, + .num = ARRAY_SIZE(pxd_bits), + .size = PGDIR_SIZE, }, { /* p4d */ .name = "P4D", - .bits = pte_bits, - .num = ARRAY_SIZE(pte_bits), + .bits = pxd_bits, + .num = ARRAY_SIZE(pxd_bits), + .size = P4D_SIZE, }, { /* pud */ .name = "PUD", - .bits = pte_bits, - .num = ARRAY_SIZE(pte_bits), + .bits = pxd_bits, + .num = ARRAY_SIZE(pxd_bits), + .size = PUD_SIZE, }, { /* pmd */ .name = "PMD", - .bits = pte_bits, - .num = ARRAY_SIZE(pte_bits), + .bits = pxd_bits, + .num = ARRAY_SIZE(pxd_bits), + .size = PMD_SIZE, }, { /* pte */ .name = "PTE", .bits = pte_bits, .num = ARRAY_SIZE(pte_bits), + .size = PAGE_SIZE }, }; @@ -251,10 +342,27 @@ static void note_page(struct ptdump_state *pt_st, unsigned long addr, int level, note_prot_wx(st, addr); } - pt_dump_seq_printf(st->seq, "0x%016lx-0x%016lx ", - st->start_address, addr); + /* + * Non-leaf entries use a fixed size for their range + * specification, whereas leaf entries are grouped by + * attributes and may not have a range larger than the type + * specifier. + */ + if (st->start_address == addr) { + if (check_add_overflow(addr, pg_level[st->level].size, + &delta)) + delta = ULONG_MAX - addr + 1; + else + delta = pg_level[st->level].size; + pt_dump_seq_printf(st->seq, "0x%016lx-0x%016lx ", + addr, addr + delta); + } else { + delta = (addr - st->start_address); + pt_dump_seq_printf(st->seq, "0x%016lx-0x%016lx ", + st->start_address, addr); + } - delta = (addr - st->start_address) >> 10; + delta >>= 10; while (!(delta & 1023) && unit[1]) { delta >>= 10; unit++; From patchwork Tue Jun 18 14:42:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxwell Bland X-Patchwork-Id: 13702476 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22D46C27C4F for ; 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Signed-off-by: Maxwell Bland --- arch/arm64/mm/ptdump.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/mm/ptdump.c b/arch/arm64/mm/ptdump.c index 8f0b459c13ed..2ec16b523043 100644 --- a/arch/arm64/mm/ptdump.c +++ b/arch/arm64/mm/ptdump.c @@ -336,6 +336,10 @@ static void note_page(struct ptdump_state *pt_st, unsigned long addr, int level, addr >= st->marker[1].start_address) { const char *unit = units; unsigned long delta; + unsigned int i; + + for (i = 0; i < st->level; i++) + pt_dump_seq_printf(st->seq, " "); if (st->current_prot) { note_prot_uxn(st, addr); @@ -362,6 +366,10 @@ static void note_page(struct ptdump_state *pt_st, unsigned long addr, int level, st->start_address, addr); } + /* Align region information regardlesss of level */ + for (i = st->level; i < 4; i++) + pt_dump_seq_printf(st->seq, " "); + delta >>= 10; while (!(delta & 1023) && unit[1]) { delta >>= 10; @@ -369,6 +377,7 @@ static void note_page(struct ptdump_state *pt_st, unsigned long addr, int level, } pt_dump_seq_printf(st->seq, "%9lu%c %s", delta, *unit, pg_level[st->level].name); + if (st->current_prot && pg_level[st->level].bits) dump_prot(st, pg_level[st->level].bits, pg_level[st->level].num); From patchwork Tue Jun 18 14:42:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxwell Bland X-Patchwork-Id: 13702477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72B98C27C4F for ; Tue, 18 Jun 2024 14:43:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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As the lowest byte is included and governed, this makes the size specifications exact. Signed-off-by: Maxwell Bland --- arch/arm64/mm/ptdump.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/mm/ptdump.c b/arch/arm64/mm/ptdump.c index 2ec16b523043..63f17c08c406 100644 --- a/arch/arm64/mm/ptdump.c +++ b/arch/arm64/mm/ptdump.c @@ -359,11 +359,11 @@ static void note_page(struct ptdump_state *pt_st, unsigned long addr, int level, else delta = pg_level[st->level].size; pt_dump_seq_printf(st->seq, "0x%016lx-0x%016lx ", - addr, addr + delta); + addr, addr + delta - 1); } else { delta = (addr - st->start_address); pt_dump_seq_printf(st->seq, "0x%016lx-0x%016lx ", - st->start_address, addr); + st->start_address, addr - 1); } /* Align region information regardlesss of level */ From patchwork Tue Jun 18 14:43:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxwell Bland X-Patchwork-Id: 13702478 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20689C27C4F for ; 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Tue, 18 Jun 2024 14:43:39 +0000 (GMT) Received: from va32lmmrp01.lenovo.com (va32lmmrp01.mot.com [10.62.177.113]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by va32lpfpp02.lenovo.com (Postfix) with ESMTPS id 4W3Tyg0Cs0z50TkV; Tue, 18 Jun 2024 14:43:39 +0000 (UTC) Received: from ilclasset02 (ilclasset02.mot.com [100.64.49.13]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: mbland) by va32lmmrp01.lenovo.com (Postfix) with ESMTPSA id 4W3Tyf59PGz2VZRs; Tue, 18 Jun 2024 14:43:38 +0000 (UTC) Date: Tue, 18 Jun 2024 09:43:37 -0500 From: Maxwell Bland To: linux-mm@kvack.org Cc: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Ard Biesheuvel , Mark Rutland , Christophe Leroy , Maxwell Bland , Alexandre Ghiti , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 5/5] arm64: add attrs and format to ptdump document Message-ID: <2hhihkaeeyyy3xj22mjdx44zlied2sp4mfewj7y6ffrnakw7cy@3fuds6n7f4ew> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Proofpoint-GUID: 361aNQGQXUBOEgw_wet2N1UkzcVudRSG X-Proofpoint-ORIG-GUID: 361aNQGQXUBOEgw_wet2N1UkzcVudRSG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-18_02,2024-06-17_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 spamscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 mlxlogscore=989 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406180110 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240618_074350_200791_737530B3 X-CRM114-Status: GOOD ( 17.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Update the ptdump content with a precise explanation of the attribute symbols and the identical-entry coalescing implicit in the code. Remove unnecessary layout example given the existing cat example, and opt instead for a precise, clear explantination of address markers, format, attributes. Update example to match the new cosmetic and intermediate-directory printing changes. Signed-off-by: Maxwell Bland --- Documentation/arch/arm64/ptdump.rst | 126 ++++++++++++++-------------- 1 file changed, 61 insertions(+), 65 deletions(-) diff --git a/Documentation/arch/arm64/ptdump.rst b/Documentation/arch/arm64/ptdump.rst index 5dcfc5d7cddf..fee7600dd4d1 100644 --- a/Documentation/arch/arm64/ptdump.rst +++ b/Documentation/arch/arm64/ptdump.rst @@ -29,68 +29,64 @@ configurations and mount debugfs:: mount -t debugfs nodev /sys/kernel/debug cat /sys/kernel/debug/kernel_page_tables -On analysing the output of ``cat /sys/kernel/debug/kernel_page_tables`` -one can derive information about the virtual address range of the entry, -followed by size of the memory region covered by this entry, the -hierarchical structure of the page tables and finally the attributes -associated with each page. The page attributes provide information about -access permissions, execution capability, type of mapping such as leaf -level PTE or block level PGD, PMD and PUD, and access status of a page -within the kernel memory. Assessing these attributes can assist in -understanding the memory layout, access patterns and security -characteristics of the kernel pages. - -Kernel virtual memory layout example:: - - start address end address size attributes - +---------------------------------------------------------------------------------------+ - | ---[ Linear Mapping start ]---------------------------------------------------------- | - | .................. | - | 0xfff0000000000000-0xfff0000000210000 2112K PTE RW NX SHD AF UXN MEM/NORMAL-TAGGED | - | 0xfff0000000210000-0xfff0000001c00000 26560K PTE ro NX SHD AF UXN MEM/NORMAL | - | .................. | - | ---[ Linear Mapping end ]------------------------------------------------------------ | - +---------------------------------------------------------------------------------------+ - | ---[ Modules start ]----------------------------------------------------------------- | - | .................. | - | 0xffff800000000000-0xffff800008000000 128M PTE | - | .................. | - | ---[ Modules end ]------------------------------------------------------------------- | - +---------------------------------------------------------------------------------------+ - | ---[ vmalloc() area ]---------------------------------------------------------------- | - | .................. | - | 0xffff800008010000-0xffff800008200000 1984K PTE ro x SHD AF UXN MEM/NORMAL | - | 0xffff800008200000-0xffff800008e00000 12M PTE ro x SHD AF CON UXN MEM/NORMAL | - | .................. | - | ---[ vmalloc() end ]----------------------------------------------------------------- | - +---------------------------------------------------------------------------------------+ - | ---[ Fixmap start ]------------------------------------------------------------------ | - | .................. | - | 0xfffffbfffdb80000-0xfffffbfffdb90000 64K PTE ro x SHD AF UXN MEM/NORMAL | - | 0xfffffbfffdb90000-0xfffffbfffdba0000 64K PTE ro NX SHD AF UXN MEM/NORMAL | - | .................. | - | ---[ Fixmap end ]-------------------------------------------------------------------- | - +---------------------------------------------------------------------------------------+ - | ---[ PCI I/O start ]----------------------------------------------------------------- | - | .................. | - | 0xfffffbfffe800000-0xfffffbffff800000 16M PTE | - | .................. | - | ---[ PCI I/O end ]------------------------------------------------------------------- | - +---------------------------------------------------------------------------------------+ - | ---[ vmemmap start ]----------------------------------------------------------------- | - | .................. | - | 0xfffffc0002000000-0xfffffc0002200000 2M PTE RW NX SHD AF UXN MEM/NORMAL | - | 0xfffffc0002200000-0xfffffc0020000000 478M PTE | - | .................. | - | ---[ vmemmap end ]------------------------------------------------------------------- | - +---------------------------------------------------------------------------------------+ - -``cat /sys/kernel/debug/kernel_page_tables`` output:: - - 0xfff0000001c00000-0xfff0000080000000 2020M PTE RW NX SHD AF UXN MEM/NORMAL-TAGGED - 0xfff0000080000000-0xfff0000800000000 30G PMD - 0xfff0000800000000-0xfff0000800700000 7M PTE RW NX SHD AF UXN MEM/NORMAL-TAGGED - 0xfff0000800700000-0xfff0000800710000 64K PTE ro NX SHD AF UXN MEM/NORMAL-TAGGED - 0xfff0000800710000-0xfff0000880000000 2089920K PTE RW NX SHD AF UXN MEM/NORMAL-TAGGED - 0xfff0000880000000-0xfff0040000000000 4062G PMD - 0xfff0040000000000-0xffff800000000000 3964T PGD +``/sys/kernel/debug/kernel_page_tables`` provides a line of information +for each group of page table entries sharing the same attributes and +type of mapping, i.e. leaf level PTE or block level PGD, PMD, and PUD. +Assessing these attributes can assist in determining memory layout, +access patterns and security characteristics of the kernel pages. + +Lines are formatted as follows:: + + - + +Note that the set of attributes, and therefore formatting, is not +equivalent between leaf and non-leaf entries. For example, PMD entries +can support the PXNTable permission bit and do not share that same set +of attributes as leaf level PTE entries. + +The following attributes are presently supported:: + +F Entry is invalid +USER Memory is user mapped +ro Memory is read-only +RW Memory is read-write +NX Memory is privileged execute never +x Memory is privileged executable +SHD Memory is shared +AF Entry accessed flag is set +NG Entry Not-Global flag is set +CON Entry contiguous bit is set +UXN Memory is unprivileged execute never +GP Memory supports BTI +TBL Entry is a table descriptor +BLK Entry is a block descriptor +NXTbl Entry's referenced table is PXN +UXNTbl Entry's referenced table is unprivileged execute never +DEVICE/* Entry is device memory, see ARM reference for types +MEM/* Entry is non-device memory, see ARM reference for types + +The beginning and end of each region is also delineated by a single line +tag in the following format:: + + ---[ ]--- + +With supported address markers including the kernel's linear mapping, +kasan shadow memory, kernel modules memory, vmalloc memory, PCI I/O +memory, and the kernel's fixmap region. + +Example ``cat /sys/kernel/debug/kernel_page_tables`` output:: + +---[ Linear Mapping start ]--- +0xffff000000000000-0xffff31ffffffffff 50T PGD +0xffff320000000000-0xffffffffffffffff 206T PGD TBL RW x NXTbl UXNTbl MEM/NORMAL + 0xffff320000000000-0xffff3251ffffffff 328G PUD + 0xffff325200000000-0xffff32523fffffff 1G PUD TBL RW x NXTbl UXNTbl MEM/NORMAL + 0xffff325200000000-0xffff3252001fffff 2M PMD TBL RW x NXTbl UXNTbl MEM/NORMAL + 0xffff325200000000-0xffff3252001fffff 2M PTE RW NX SHD AF NG UXN MEM/NORMAL-TAGGED + 0xffff325200200000-0xffff3252003fffff 2M PMD TBL RW x NXTbl UXNTbl MEM/NORMAL + 0xffff325200200000-0xffff32520020ffff 64K PTE RW NX SHD AF NG UXN MEM/NORMAL-TAGGED + 0xffff325200210000-0xffff3252003fffff 1984K PTE ro NX SHD AF NG UXN MEM/NORMAL + 0xffff325200400000-0xffff325201dfffff 26M PMD BLK ro SHD AF NG NX UXN MEM/NORMAL + 0xffff325201e00000-0xffff325201ffffff 2M PMD TBL RW x NXTbl UXNTbl MEM/NORMAL + 0xffff325201e00000-0xffff325201e0ffff 64K PTE ro NX SHD AF NG UXN MEM/NORMAL + 0xffff325201e10000-0xffff325201ffffff 1984K PTE RW NX SHD AF NG UXN MEM/NORMAL-TAGGED