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([202.166.44.78]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c4a75ee5a5sm13529305a91.17.2024.06.18.10.32.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 10:32:17 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH 1/4] riscv: Extend exception handling support for interrupts Date: Wed, 19 Jun 2024 01:30:50 +0800 Message-ID: <20240618173053.364776-2-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240618173053.364776-1-jamestiotio@gmail.com> References: <20240618173053.364776-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add install_irq_handler() to enable tests to install interrupt handlers. Also add local_irq_enable() and local_irq_disable() to respectively enable and disable IRQs via the sstatus.SIE bit. Signed-off-by: Andrew Jones Signed-off-by: James Raphael Tiovalen --- lib/riscv/asm/csr.h | 2 ++ lib/riscv/asm/processor.h | 13 +++++++++++++ lib/riscv/processor.c | 27 +++++++++++++++++++++++---- 3 files changed, 38 insertions(+), 4 deletions(-) diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h index 52608512..d5879d2a 100644 --- a/lib/riscv/asm/csr.h +++ b/lib/riscv/asm/csr.h @@ -11,6 +11,8 @@ #define CSR_STVAL 0x143 #define CSR_SATP 0x180 +#define SSTATUS_SIE (_AC(1, UL) << 1) + /* Exception cause high bit - is an interrupt if set */ #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h index 32c499d0..767b1caa 100644 --- a/lib/riscv/asm/processor.h +++ b/lib/riscv/asm/processor.h @@ -5,6 +5,7 @@ #include #define EXCEPTION_CAUSE_MAX 16 +#define INTERRUPT_CAUSE_MAX 16 typedef void (*exception_fn)(struct pt_regs *); @@ -13,6 +14,7 @@ struct thread_info { unsigned long hartid; unsigned long isa[1]; exception_fn exception_handlers[EXCEPTION_CAUSE_MAX]; + exception_fn interrupt_handlers[INTERRUPT_CAUSE_MAX]; }; static inline struct thread_info *current_thread_info(void) @@ -20,7 +22,18 @@ static inline struct thread_info *current_thread_info(void) return (struct thread_info *)csr_read(CSR_SSCRATCH); } +static inline void local_irq_enable(void) +{ + csr_set(CSR_SSTATUS, SSTATUS_SIE); +} + +static inline void local_irq_disable(void) +{ + csr_clear(CSR_SSTATUS, SSTATUS_SIE); +} + void install_exception_handler(unsigned long cause, void (*handler)(struct pt_regs *)); +void install_irq_handler(unsigned long cause, void (*handler)(struct pt_regs *)); void do_handle_exception(struct pt_regs *regs); void thread_info_init(void); diff --git a/lib/riscv/processor.c b/lib/riscv/processor.c index ece7cbff..0dffadc7 100644 --- a/lib/riscv/processor.c +++ b/lib/riscv/processor.c @@ -36,10 +36,21 @@ void do_handle_exception(struct pt_regs *regs) { struct thread_info *info = current_thread_info(); - assert(regs->cause < EXCEPTION_CAUSE_MAX); - if (info->exception_handlers[regs->cause]) { - info->exception_handlers[regs->cause](regs); - return; + if (regs->cause & CAUSE_IRQ_FLAG) { + unsigned long irq_cause = regs->cause & ~CAUSE_IRQ_FLAG; + + assert(irq_cause < INTERRUPT_CAUSE_MAX); + if (info->interrupt_handlers[irq_cause]) { + info->interrupt_handlers[irq_cause](regs); + return; + } + } else { + assert(regs->cause < EXCEPTION_CAUSE_MAX); + + if (info->exception_handlers[regs->cause]) { + info->exception_handlers[regs->cause](regs); + return; + } } show_regs(regs); @@ -47,6 +58,14 @@ void do_handle_exception(struct pt_regs *regs) abort(); } +void install_irq_handler(unsigned long cause, void (*handler)(struct pt_regs *)) +{ + struct thread_info *info = current_thread_info(); + + assert(cause < INTERRUPT_CAUSE_MAX); + info->interrupt_handlers[cause] = handler; +} + void install_exception_handler(unsigned long cause, void (*handler)(struct pt_regs *)) { struct thread_info *info = current_thread_info(); From patchwork Tue Jun 18 17:30:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James R T X-Patchwork-Id: 13702792 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C94C613F00A for ; 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([202.166.44.78]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c4a75ee5a5sm13529305a91.17.2024.06.18.10.32.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 10:32:19 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH 2/4] riscv: Update exception cause list Date: Wed, 19 Jun 2024 01:30:51 +0800 Message-ID: <20240618173053.364776-3-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240618173053.364776-1-jamestiotio@gmail.com> References: <20240618173053.364776-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Update the list of exception and interrupt causes to follow the latest RISC-V privileged ISA specification (version 20240411). Signed-off-by: James Raphael Tiovalen --- lib/riscv/asm/csr.h | 15 +++++++++------ lib/riscv/asm/processor.h | 2 +- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h index d5879d2a..c1777744 100644 --- a/lib/riscv/asm/csr.h +++ b/lib/riscv/asm/csr.h @@ -26,15 +26,18 @@ #define EXC_STORE_MISALIGNED 6 #define EXC_STORE_ACCESS 7 #define EXC_SYSCALL 8 -#define EXC_HYPERVISOR_SYSCALL 9 -#define EXC_SUPERVISOR_SYSCALL 10 +#define EXC_SUPERVISOR_SYSCALL 9 #define EXC_INST_PAGE_FAULT 12 #define EXC_LOAD_PAGE_FAULT 13 #define EXC_STORE_PAGE_FAULT 15 -#define EXC_INST_GUEST_PAGE_FAULT 20 -#define EXC_LOAD_GUEST_PAGE_FAULT 21 -#define EXC_VIRTUAL_INST_FAULT 22 -#define EXC_STORE_GUEST_PAGE_FAULT 23 +#define EXC_SOFTWARE_CHECK 18 +#define EXC_HARDWARE_ERROR 19 + +/* Interrupt causes */ +#define IRQ_SUPERVISOR_SOFTWARE 1 +#define IRQ_SUPERVISOR_TIMER 5 +#define IRQ_SUPERVISOR_EXTERNAL 9 +#define IRQ_COUNTER_OVERFLOW 13 #ifndef __ASSEMBLY__ diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h index 767b1caa..5942ed2e 100644 --- a/lib/riscv/asm/processor.h +++ b/lib/riscv/asm/processor.h @@ -4,7 +4,7 @@ #include #include -#define EXCEPTION_CAUSE_MAX 16 +#define EXCEPTION_CAUSE_MAX 64 #define INTERRUPT_CAUSE_MAX 16 typedef void (*exception_fn)(struct pt_regs *); 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([202.166.44.78]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c4a75ee5a5sm13529305a91.17.2024.06.18.10.32.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 10:32:21 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH 3/4] riscv: Add methods to toggle interrupt enable bits Date: Wed, 19 Jun 2024 01:30:52 +0800 Message-ID: <20240618173053.364776-4-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240618173053.364776-1-jamestiotio@gmail.com> References: <20240618173053.364776-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add some helper methods to toggle the interrupt enable bits in the SIE register. Signed-off-by: James Raphael Tiovalen --- riscv/Makefile | 1 + lib/riscv/asm/csr.h | 7 +++++++ lib/riscv/asm/interrupt.h | 12 ++++++++++++ lib/riscv/interrupt.c | 39 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 59 insertions(+) create mode 100644 lib/riscv/asm/interrupt.h create mode 100644 lib/riscv/interrupt.c diff --git a/riscv/Makefile b/riscv/Makefile index 919a3ebb..108d4481 100644 --- a/riscv/Makefile +++ b/riscv/Makefile @@ -30,6 +30,7 @@ cflatobjs += lib/memregions.o cflatobjs += lib/on-cpus.o cflatobjs += lib/vmalloc.o cflatobjs += lib/riscv/bitops.o +cflatobjs += lib/riscv/interrupt.o cflatobjs += lib/riscv/io.o cflatobjs += lib/riscv/isa.o cflatobjs += lib/riscv/mmu.o diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h index c1777744..da58b0ce 100644 --- a/lib/riscv/asm/csr.h +++ b/lib/riscv/asm/csr.h @@ -4,15 +4,22 @@ #include #define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 #define CSR_STVAL 0x143 +#define CSR_SIP 0x144 #define CSR_SATP 0x180 #define SSTATUS_SIE (_AC(1, UL) << 1) +#define SIE_SSIE (_AC(1, UL) << 1) +#define SIE_STIE (_AC(1, UL) << 5) +#define SIE_SEIE (_AC(1, UL) << 9) +#define SIE_LCOFIE (_AC(1, UL) << 13) + /* Exception cause high bit - is an interrupt if set */ #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) diff --git a/lib/riscv/asm/interrupt.h b/lib/riscv/asm/interrupt.h new file mode 100644 index 00000000..b760afbb --- /dev/null +++ b/lib/riscv/asm/interrupt.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASMRISCV_INTERRUPT_H_ +#define _ASMRISCV_INTERRUPT_H_ + +#include + +void toggle_software_interrupt(bool enable); +void toggle_timer_interrupt(bool enable); +void toggle_external_interrupt(bool enable); +void toggle_local_cof_interrupt(bool enable); + +#endif /* _ASMRISCV_INTERRUPT_H_ */ diff --git a/lib/riscv/interrupt.c b/lib/riscv/interrupt.c new file mode 100644 index 00000000..bc0e16f1 --- /dev/null +++ b/lib/riscv/interrupt.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024, James Raphael Tiovalen + */ +#include +#include +#include + +void toggle_software_interrupt(bool enable) +{ + if (enable) + csr_set(CSR_SIE, SIE_SSIE); + else + csr_clear(CSR_SIE, SIE_SSIE); +} + +void toggle_timer_interrupt(bool enable) +{ + if (enable) + csr_set(CSR_SIE, SIE_STIE); + else + csr_clear(CSR_SIE, SIE_STIE); +} + +void toggle_external_interrupt(bool enable) +{ + if (enable) + csr_set(CSR_SIE, SIE_SEIE); + else + csr_clear(CSR_SIE, SIE_SEIE); +} + +void toggle_local_cof_interrupt(bool enable) +{ + if (enable) + csr_set(CSR_SIE, SIE_LCOFIE); + else + csr_clear(CSR_SIE, SIE_LCOFIE); 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([202.166.44.78]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c4a75ee5a5sm13529305a91.17.2024.06.18.10.32.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 10:32:25 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH 4/4] riscv: sbi: Add test for timer extension Date: Wed, 19 Jun 2024 01:30:53 +0800 Message-ID: <20240618173053.364776-5-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240618173053.364776-1-jamestiotio@gmail.com> References: <20240618173053.364776-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a test for the set_timer function of the time extension. The test checks that: - The time extension is available - The time counter monotonically increases - The installed timer interrupt handler is called - The timer interrupt is received within a reasonable time frame The timer interrupt delay can be set using the TIMER_DELAY environment variable. If the variable is not set, the default delay value is 1000000. The time interval used to validate the timer interrupt is between the specified delay and double the delay. Because of this, the test might fail if the delay is too short. Hence, we set the default delay value as the minimum value. This test has been verified on RV32 and RV64 with OpenSBI using QEMU. Signed-off-by: James Raphael Tiovalen --- lib/riscv/asm/csr.h | 6 ++++ lib/riscv/asm/sbi.h | 5 +++ riscv/sbi.c | 87 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 98 insertions(+) diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h index da58b0ce..c4435650 100644 --- a/lib/riscv/asm/csr.h +++ b/lib/riscv/asm/csr.h @@ -12,6 +12,7 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 #define CSR_SATP 0x180 +#define CSR_TIME 0xc01 #define SSTATUS_SIE (_AC(1, UL) << 1) @@ -108,5 +109,10 @@ : "memory"); \ }) +#define wfi() \ +({ \ + __asm__ __volatile__("wfi" ::: "memory"); \ +}) + #endif /* !__ASSEMBLY__ */ #endif /* _ASMRISCV_CSR_H_ */ diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h index d82a384d..eb4c77ef 100644 --- a/lib/riscv/asm/sbi.h +++ b/lib/riscv/asm/sbi.h @@ -18,6 +18,7 @@ enum sbi_ext_id { SBI_EXT_BASE = 0x10, SBI_EXT_HSM = 0x48534d, SBI_EXT_SRST = 0x53525354, + SBI_EXT_TIME = 0x54494D45, }; enum sbi_ext_base_fid { @@ -37,6 +38,10 @@ enum sbi_ext_hsm_fid { SBI_EXT_HSM_HART_SUSPEND, }; +enum sbi_ext_time_fid { + SBI_EXT_TIME_SET_TIMER = 0, +}; + struct sbiret { long error; long value; diff --git a/riscv/sbi.c b/riscv/sbi.c index 762e9711..6ad1dff6 100644 --- a/riscv/sbi.c +++ b/riscv/sbi.c @@ -6,8 +6,13 @@ */ #include #include +#include +#include +#include #include +static bool timer_work; + static void help(void) { puts("Test SBI\n"); @@ -19,6 +24,18 @@ static struct sbiret __base_sbi_ecall(int fid, unsigned long arg0) return sbi_ecall(SBI_EXT_BASE, fid, arg0, 0, 0, 0, 0, 0); } +static struct sbiret __time_sbi_ecall(int fid, unsigned long arg0) +{ + return sbi_ecall(SBI_EXT_TIME, fid, arg0, 0, 0, 0, 0, 0); +} + +static void timer_interrupt_handler(struct pt_regs *regs) +{ + timer_work = true; + toggle_timer_interrupt(false); + local_irq_disable(); +} + static bool env_or_skip(const char *env) { if (!getenv(env)) { @@ -112,6 +129,75 @@ static void check_base(void) report_prefix_pop(); } +static void check_time(void) +{ + struct sbiret ret; + unsigned long begin, end, duration; + const unsigned long default_delay = 1000000; + unsigned long delay = getenv("TIMER_DELAY") + ? MAX(strtol(getenv("TIMER_DELAY"), NULL, 0), default_delay) + : default_delay; + + report_prefix_push("time"); + + ret = __base_sbi_ecall(SBI_EXT_BASE_PROBE_EXT, SBI_EXT_TIME); + + if (ret.error) { + report_fail("probing for time extension failed"); + report_prefix_pop(); + return; + } + + if (!ret.value) { + report_skip("time extension not available"); + report_prefix_pop(); + return; + } + + begin = csr_read(CSR_TIME); + end = csr_read(CSR_TIME); + if (begin >= end) { + report_fail("time counter has decreased"); + report_prefix_pop(); + return; + } + + report_prefix_push("set_timer"); + + install_irq_handler(IRQ_SUPERVISOR_TIMER, timer_interrupt_handler); + local_irq_enable(); + + begin = csr_read(CSR_TIME); + ret = __time_sbi_ecall(SBI_EXT_TIME_SET_TIMER, csr_read(CSR_TIME) + delay); + + if (ret.error) { + report_fail("setting timer failed"); + install_irq_handler(IRQ_SUPERVISOR_TIMER, NULL); + report_prefix_pop(); + report_prefix_pop(); + return; + } + + toggle_timer_interrupt(true); + + while ((!timer_work) && (csr_read(CSR_TIME) <= (begin + delay))) + wfi(); + + end = csr_read(CSR_TIME); + report(timer_work, "timer interrupt received"); + + install_irq_handler(IRQ_SUPERVISOR_TIMER, NULL); + __time_sbi_ecall(SBI_EXT_TIME_SET_TIMER, -1); + + duration = end - begin; + if (timer_work) + report((duration >= delay) && (duration <= (delay + delay)), "timer delay honored"); + + report_prefix_pop(); + + report_prefix_pop(); +} + int main(int argc, char **argv) { @@ -122,6 +208,7 @@ int main(int argc, char **argv) report_prefix_push("sbi"); check_base(); + check_time(); return report_summary(); }