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Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias --- hw/misc/zynq_slcr.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 3412ff099ea..ad814c3a79b 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -24,6 +24,8 @@ #include "hw/registerfields.h" #include "hw/qdev-clock.h" #include "qom/object.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" #ifndef ZYNQ_SLCR_ERR_DEBUG #define ZYNQ_SLCR_ERR_DEBUG 0 @@ -121,6 +123,7 @@ REG32(RST_REASON, 0x250) REG32(REBOOT_STATUS, 0x258) REG32(BOOT_MODE, 0x25c) + FIELD(BOOT_MODE, BOOT_MODE, 0, 4) REG32(APU_CTRL, 0x300) REG32(WDT_CLK_SEL, 0x304) @@ -195,6 +198,7 @@ struct ZynqSLCRState { Clock *ps_clk; Clock *uart0_ref_clk; Clock *uart1_ref_clk; + uint8_t boot_mode; }; /* @@ -371,7 +375,7 @@ static void zynq_slcr_reset_init(Object *obj, ResetType type) s->regs[R_FPGA_RST_CTRL] = 0x01F33F0F; s->regs[R_RST_REASON] = 0x00000040; - s->regs[R_BOOT_MODE] = 0x00000001; + s->regs[R_BOOT_MODE] = s->boot_mode & R_BOOT_MODE_BOOT_MODE_MASK; /* 0x700 - 0x7D4 */ for (i = 0; i < 54; i++) { @@ -588,6 +592,15 @@ static const ClockPortInitArray zynq_slcr_clocks = { QDEV_CLOCK_END }; +static void zynq_slcr_realize(DeviceState *dev, Error **errp) +{ + ZynqSLCRState *s = ZYNQ_SLCR(dev); + + if (s->boot_mode > 0xF) { + error_setg(errp, "Invalid boot mode %d specified", s->boot_mode); + } +} + static void zynq_slcr_init(Object *obj) { ZynqSLCRState *s = ZYNQ_SLCR(obj); @@ -610,15 +623,22 @@ static const VMStateDescription vmstate_zynq_slcr = { } }; +static Property zynq_slcr_props[] = { + DEFINE_PROP_UINT8("boot-mode", ZynqSLCRState, boot_mode, 1), + DEFINE_PROP_END_OF_LIST(), +}; + static void zynq_slcr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); ResettableClass *rc = RESETTABLE_CLASS(klass); dc->vmsd = &vmstate_zynq_slcr; + dc->realize = zynq_slcr_realize; rc->phases.enter = zynq_slcr_reset_init; rc->phases.hold = zynq_slcr_reset_hold; rc->phases.exit = zynq_slcr_reset_exit; + device_class_set_props(dc, zynq_slcr_props); } static const TypeInfo zynq_slcr_info = { From patchwork Wed Jun 19 09:16:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sai Pavan Boddu X-Patchwork-Id: 13703556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36997C27C53 for ; Wed, 19 Jun 2024 09:18:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sJrR6-00049U-TG; Wed, 19 Jun 2024 05:17:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sJrR4-00047N-At; Wed, 19 Jun 2024 05:16:58 -0400 Received: from mail-dm3nam02on20601.outbound.protection.outlook.com ([2a01:111:f403:2405::601] helo=NAM02-DM3-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sJrR2-0003rP-Ef; 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Wed, 19 Jun 2024 04:16:49 -0500 From: Sai Pavan Boddu To: , CC: "'Edgar E . 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Signed-off-by: Sai Pavan Boddu Acked-by: Edgar E. Iglesias --- hw/arm/xilinx_zynq.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 7f7a3d23fbe..39f07e6dfd8 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -38,6 +38,7 @@ #include "qom/object.h" #include "exec/tswap.h" #include "target/arm/cpu-qom.h" +#include "qapi/visitor.h" #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) @@ -90,6 +91,7 @@ struct ZynqMachineState { MachineState parent; Clock *ps_clk; ARMCPU *cpu[ZYNQ_MAX_CPUS]; + uint8_t boot_mode; }; static void zynq_write_board_setup(ARMCPU *cpu, @@ -176,6 +178,27 @@ static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, return unit; } +static void zynq_set_boot_mode(Object *obj, const char *str, + Error **errp) +{ + ZynqMachineState *m = ZYNQ_MACHINE(obj); + uint8_t mode = 0; + + if (!strcasecmp(str, "QSPI")) { + mode = 1; + } else if (!strcasecmp(str, "SD")) { + mode = 5; + } else if (!strcasecmp(str, "NOR")) { + mode = 2; + } else if (!strcasecmp(str, "JTAG")) { + mode = 0; + } else { + error_setg(errp, "%s bootmode is not supported", str); + return; + } + m->boot_mode = mode; +} + static void zynq_init(MachineState *machine) { ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine); @@ -241,6 +264,7 @@ static void zynq_init(MachineState *machine) /* Create slcr, keep a pointer to connect clocks */ slcr = qdev_new("xilinx-zynq_slcr"); qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); + qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->boot_mode); sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); @@ -372,6 +396,7 @@ static void zynq_machine_class_init(ObjectClass *oc, void *data) NULL }; MachineClass *mc = MACHINE_CLASS(oc); + ObjectProperty *prop; mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; mc->init = zynq_init; mc->max_cpus = ZYNQ_MAX_CPUS; @@ -379,6 +404,12 @@ static void zynq_machine_class_init(ObjectClass *oc, void *data) mc->ignore_memory_transaction_failures = true; mc->valid_cpu_types = valid_cpu_types; mc->default_ram_id = "zynq.ext_ram"; + prop = object_class_property_add_str(oc, "boot-mode", NULL, + zynq_set_boot_mode); + object_class_property_set_description(oc, "boot-mode", + "Supported boot modes:" + " JTAG QSPI SD NOR"); + object_property_set_default_str(prop, "QSPI"); } static const TypeInfo zynq_machine_type = { From patchwork Wed Jun 19 09:16:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sai Pavan Boddu X-Patchwork-Id: 13703554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8F50C27C53 for ; Wed, 19 Jun 2024 09:17:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sJrR7-00049w-Mt; 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Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias --- docs/system/arm/xlnx-zynq.rst | 47 +++++++++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + 2 files changed, 48 insertions(+) create mode 100644 docs/system/arm/xlnx-zynq.rst diff --git a/docs/system/arm/xlnx-zynq.rst b/docs/system/arm/xlnx-zynq.rst new file mode 100644 index 00000000000..419cc1aec8b --- /dev/null +++ b/docs/system/arm/xlnx-zynq.rst @@ -0,0 +1,47 @@ +Xilinx Zynq board (``xilinx-zynq-a9``) +====================================== +The Zynq 7000 family is based on the AMD SoC architecture. These products +integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based +processing system (PS) and AMD programmable logic (PL) in a single device. + +More details here: +https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual + +QEMU xilinx-zynq-a9 board supports following devices: + - A9 MPCORE + - cortex-a9 + - GIC v1 + - Generic timer + - wdt + - OCM 256KB + - SMC SRAM@0xe2000000 64MB + - Zynq SLCR + - SPI x2 + - QSPI + - UART + - TTC x2 + - Gigabit Ethernet Controller x2 + - SD Controller x2 + - XADC + - Arm PrimeCell DMA Controller + - DDR Memory + - USB 2.0 x2 + +Running +""""""" +Direct Linux boot of a generic ARM upstream Linux kernel: + +.. code-block:: bash + + $ qemu-system-aarch64 -M xilinx-zynq-a9 \ + -dtb zynq-zc702.dtb -serial null -serial mon:stdio \ + -display none -m 1024 \ + -initrd rootfs.cpio.gz -kernel zImage + +For configuring the boot-mode provide the following on the command line: + +.. code-block:: bash + + -machine boot-mode=qspi + +Supported values are JTAG, SD, QSPI, NOR. diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 870d30e3502..7b992722846 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -109,6 +109,7 @@ undocumented; you can get a complete list by running arm/virt arm/xenpvh arm/xlnx-versal-virt + arm/xlnx-zynq Emulated CPU architecture support =================================