From patchwork Wed Jun 19 14:14:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13703893 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AAD4F9D4; Wed, 19 Jun 2024 14:15:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718806512; cv=none; b=AkFJZIdyGp8Fxk0+NfNQpNqzstFRUGGiQ4ySN0d454qS150oscXTBaqO69cwZ+QpJr0Lt3xX5v/ug66C2oqP7LHVjp6iSMmTLNfdMr5E7CR5vlWBo6fD56SbBWzcGM0Y0CCjQhSmInwtwLRRXQNsObqqiLDg8Y961MCdgN7+j8Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718806512; c=relaxed/simple; bh=JUVqGjz1iRAWkVa4AnQh84lQcbsn6IWnYiyewY7joow=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WhPa4Y/PZP8R1e1ADrq0iLai6vumSaz7KmaMnQDLmw+MSXofzCIUzenTZPeeXq9V8VfPYP/psJ+HmneKb4yZeBA/U0uOV+SsJ41LrkDUyMR0nEUr5/by8WeMIzqV/PoZoEc8mBSjLnUUz7uHfPEPgCKcL9wj9G+OBTANzq+HDMY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=AltEaFb1; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="AltEaFb1" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45J9I8ow001969; Wed, 19 Jun 2024 14:14:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= UCccK02F7BsWYZLV8xPiXaTuhg11aJN+SpDz5ei1w84=; b=AltEaFb1sSaNh12R R5zU7orfV5jAfHpXJVY0kkgiY7BTmJ0GetE+YnbzCjVTSIyAqH3E25VAr4dy+wWy c6LJRHPC570a9J6ejdcrPdw+BSsPbz1fSq9G7TKjN5w3lRvho9UQsR/kbc5iNReB b5JuHFCe28hF0RhYUmNnJbxZFF6Y8N7YvtwVz2pmZQyL8AQ3J9kEwQrKFlzpET2k KSMpOZqIX4XSvE3sMst5PBKG1kliEnL0oxFvKcwEosCCnsJCat8AWSPAk6jLIlFD Jfba+d1geLfee19aYTjpkghPZ1FF2/lqFQpibfZQCLidlZRTj5wdTyFz/BnD/ChS 1e0D6A== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3yujag1wmk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jun 2024 14:14:58 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45JEEvol020426 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jun 2024 14:14:57 GMT Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 19 Jun 2024 07:14:49 -0700 From: Jagadeesh Kona To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Stanimir Varbanov , Vikash Garodia , Bryan O'Donoghue , Mauro Carvalho Chehab , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Pavel Machek , Len Brown , Greg Kroah-Hartman , Konrad Dybcio , "Andy Gross" , Dmitry Baryshkov , Abel Vesa CC: , , , , , Taniya Das , "Jagadeesh Kona" , Satya Priya Kakitapalli , Imran Shaik , "Ajit Pandey" , Dhruva Gole Subject: [PATCH V6 1/5] PM: domains: Allow devices attached to genpd to be managed by HW Date: Wed, 19 Jun 2024 19:44:09 +0530 Message-ID: <20240619141413.7983-2-quic_jkona@quicinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240619141413.7983-1-quic_jkona@quicinc.com> References: <20240619141413.7983-1-quic_jkona@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Y7iPXJciubvCXi0yMazWKKWSPbKCA3H6 X-Proofpoint-ORIG-GUID: Y7iPXJciubvCXi0yMazWKKWSPbKCA3H6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-19_02,2024-06-19_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 clxscore=1011 impostorscore=0 suspectscore=0 adultscore=0 spamscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406190105 From: Ulf Hansson Some power-domains may be capable of relying on the HW to control the power for a device that's hooked up to it. Typically, for these kinds of configurations the consumer driver should be able to change the behavior of power domain at runtime, control the power domain in SW mode for certain configurations and handover the control to HW mode for other usecases. To allow a consumer driver to change the behaviour of the PM domain for its device, let's provide a new function, dev_pm_genpd_set_hwmode(). Moreover, let's add a corresponding optional genpd callback, ->set_hwmode_dev(), which the genpd provider should implement if it can support switching between HW controlled mode and SW controlled mode. Similarly, add the dev_pm_genpd_get_hwmode() to allow consumers to read the current mode and its corresponding optional genpd callback, ->get_hwmode_dev(), which the genpd provider can also implement to synchronize the initial HW mode state in genpd_add_device() by reading back the mode from the hardware. Signed-off-by: Ulf Hansson Signed-off-by: Abel Vesa Signed-off-by: Jagadeesh Kona Reviewed-by: Dmitry Baryshkov Reviewed-by: Dhruva Gole Reviewed-by: Taniya Das --- drivers/pmdomain/core.c | 64 +++++++++++++++++++++++++++++++++++++++ include/linux/pm_domain.h | 17 +++++++++++ 2 files changed, 81 insertions(+) diff --git a/drivers/pmdomain/core.c b/drivers/pmdomain/core.c index 83d978743659..a9a409b2d25c 100644 --- a/drivers/pmdomain/core.c +++ b/drivers/pmdomain/core.c @@ -588,6 +588,68 @@ void dev_pm_genpd_synced_poweroff(struct device *dev) } EXPORT_SYMBOL_GPL(dev_pm_genpd_synced_poweroff); +/** + * dev_pm_genpd_set_hwmode() - Set the HW mode for the device and its PM domain. + * + * @dev: Device for which the HW-mode should be changed. + * @enable: Value to set or unset the HW-mode. + * + * Some PM domains can rely on HW signals to control the power for a device. To + * allow a consumer driver to switch the behaviour for its device in runtime, + * which may be beneficial from a latency or energy point of view, this function + * may be called. + * + * It is assumed that the users guarantee that the genpd wouldn't be detached + * while this routine is getting called. + * + * Return: Returns 0 on success and negative error values on failures. + */ +int dev_pm_genpd_set_hwmode(struct device *dev, bool enable) +{ + struct generic_pm_domain *genpd; + int ret = 0; + + genpd = dev_to_genpd_safe(dev); + if (!genpd) + return -ENODEV; + + if (!genpd->set_hwmode_dev) + return -EOPNOTSUPP; + + genpd_lock(genpd); + + if (dev_gpd_data(dev)->hw_mode == enable) + goto out; + + ret = genpd->set_hwmode_dev(genpd, dev, enable); + if (!ret) + dev_gpd_data(dev)->hw_mode = enable; + +out: + genpd_unlock(genpd); + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_genpd_set_hwmode); + +/** + * dev_pm_genpd_get_hwmode() - Get the HW mode setting for the device. + * + * @dev: Device for which the current HW-mode setting should be fetched. + * + * This helper function allows consumer drivers to fetch the current HW mode + * setting of its the device. + * + * It is assumed that the users guarantee that the genpd wouldn't be detached + * while this routine is getting called. + * + * Return: Returns the HW mode setting of device from SW cached hw_mode. + */ +bool dev_pm_genpd_get_hwmode(struct device *dev) +{ + return dev_gpd_data(dev)->hw_mode; +} +EXPORT_SYMBOL_GPL(dev_pm_genpd_get_hwmode); + static int _genpd_power_on(struct generic_pm_domain *genpd, bool timed) { unsigned int state_idx = genpd->state_idx; @@ -1687,6 +1749,8 @@ static int genpd_add_device(struct generic_pm_domain *genpd, struct device *dev, gpd_data->cpu = genpd_get_cpu(genpd, base_dev); + gpd_data->hw_mode = genpd->get_hwmode_dev ? genpd->get_hwmode_dev(genpd, dev) : false; + ret = genpd->attach_dev ? genpd->attach_dev(genpd, dev) : 0; if (ret) goto out; diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h index 71e4f0fb8867..858c8e7851fb 100644 --- a/include/linux/pm_domain.h +++ b/include/linux/pm_domain.h @@ -175,6 +175,10 @@ struct generic_pm_domain { int (*set_performance_state)(struct generic_pm_domain *genpd, unsigned int state); struct gpd_dev_ops dev_ops; + int (*set_hwmode_dev)(struct generic_pm_domain *domain, + struct device *dev, bool enable); + bool (*get_hwmode_dev)(struct generic_pm_domain *domain, + struct device *dev); int (*attach_dev)(struct generic_pm_domain *domain, struct device *dev); void (*detach_dev)(struct generic_pm_domain *domain, @@ -237,6 +241,7 @@ struct generic_pm_domain_data { unsigned int performance_state; unsigned int default_pstate; unsigned int rpm_pstate; + bool hw_mode; void *data; }; @@ -267,6 +272,8 @@ int dev_pm_genpd_remove_notifier(struct device *dev); void dev_pm_genpd_set_next_wakeup(struct device *dev, ktime_t next); ktime_t dev_pm_genpd_get_next_hrtimer(struct device *dev); void dev_pm_genpd_synced_poweroff(struct device *dev); +int dev_pm_genpd_set_hwmode(struct device *dev, bool enable); +bool dev_pm_genpd_get_hwmode(struct device *dev); extern struct dev_power_governor simple_qos_governor; extern struct dev_power_governor pm_domain_always_on_gov; @@ -340,6 +347,16 @@ static inline ktime_t dev_pm_genpd_get_next_hrtimer(struct device *dev) static inline void dev_pm_genpd_synced_poweroff(struct device *dev) { } +static inline int dev_pm_genpd_set_hwmode(struct device *dev, bool enable) +{ + return -EOPNOTSUPP; +} + +static inline bool dev_pm_genpd_get_hwmode(struct device *dev) +{ + return false; +} + #define simple_qos_governor (*(struct dev_power_governor *)(NULL)) #define pm_domain_always_on_gov (*(struct dev_power_governor *)(NULL)) #endif From patchwork Wed Jun 19 14:14:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13703894 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D847C17BA6; Wed, 19 Jun 2024 14:15:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718806516; cv=none; b=ozeEC/3FJTt3bzKCaubnt220ZllnPgeU1ck993+BRm3jm12tDNXiPUZOWtogrm6rzFIM7kQFHmQkzBQ7F7+Cc90JKM7YdIkCMF3TB5xW1QdMloAbN6wbfDODIfFpYSfE7xUgDXciblFomqlqTLySFiZ5wPWBYk9qwg59tMI1wtg= ARC-Message-Signature: i=1; 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Wed, 19 Jun 2024 14:15:05 GMT Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 19 Jun 2024 07:14:57 -0700 From: Jagadeesh Kona To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Stanimir Varbanov , Vikash Garodia , Bryan O'Donoghue , Mauro Carvalho Chehab , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Pavel Machek , Len Brown , Greg Kroah-Hartman , Konrad Dybcio , "Andy Gross" , Dmitry Baryshkov , Abel Vesa CC: , , , , , Taniya Das , "Jagadeesh Kona" , Satya Priya Kakitapalli , Imran Shaik , "Ajit Pandey" , Dhruva Gole Subject: [PATCH V6 2/5] PM: domains: Add the domain HW-managed mode to the summary Date: Wed, 19 Jun 2024 19:44:10 +0530 Message-ID: <20240619141413.7983-3-quic_jkona@quicinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240619141413.7983-1-quic_jkona@quicinc.com> References: <20240619141413.7983-1-quic_jkona@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: wnI4gJgmz0lQH1x_ICAFwbW6A6WV1RIo X-Proofpoint-GUID: wnI4gJgmz0lQH1x_ICAFwbW6A6WV1RIo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-19_02,2024-06-19_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=999 malwarescore=0 phishscore=0 bulkscore=0 suspectscore=0 clxscore=1015 spamscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406190106 From: Abel Vesa Now that genpd supports dynamically switching the control for an attached device between hardware- and software-mode, let's add this information to the genpd summary under managed by column in debugfs. Suggested-by: Taniya Das Signed-off-by: Abel Vesa Signed-off-by: Jagadeesh Kona Reviewed-by: Ulf Hansson Reviewed-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Reviewed-by: Dhruva Gole Reviewed-by: Taniya Das --- drivers/pmdomain/core.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/pmdomain/core.c b/drivers/pmdomain/core.c index a9a409b2d25c..7a61aa88c061 100644 --- a/drivers/pmdomain/core.c +++ b/drivers/pmdomain/core.c @@ -3184,6 +3184,15 @@ static void rtpm_status_str(struct seq_file *s, struct device *dev) seq_printf(s, "%-25s ", p); } +static void mode_status_str(struct seq_file *s, struct device *dev) +{ + struct generic_pm_domain_data *gpd_data; + + gpd_data = to_gpd_data(dev->power.subsys_data->domain_data); + + seq_printf(s, "%20s", gpd_data->hw_mode ? "HW" : "SW"); +} + static void perf_status_str(struct seq_file *s, struct device *dev) { struct generic_pm_domain_data *gpd_data; @@ -3242,6 +3251,7 @@ static int genpd_summary_one(struct seq_file *s, seq_printf(s, "\n %-50s ", kobj_path); rtpm_status_str(s, pm_data->dev); perf_status_str(s, pm_data->dev); + mode_status_str(s, pm_data->dev); kfree(kobj_path); } @@ -3258,8 +3268,8 @@ static int summary_show(struct seq_file *s, void *data) int ret = 0; seq_puts(s, "domain status children performance\n"); - seq_puts(s, " /device runtime status\n"); - seq_puts(s, "----------------------------------------------------------------------------------------------\n"); + seq_puts(s, " /device runtime status managed by\n"); + seq_puts(s, "------------------------------------------------------------------------------------------------------------\n"); ret = mutex_lock_interruptible(&gpd_list_lock); if (ret) From patchwork Wed Jun 19 14:14:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13703895 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20DD0D27E; Wed, 19 Jun 2024 14:15:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718806525; cv=none; b=f7ZRRIKG+OvZI7xADnmuqq1opAdIGSsuGXnx7394y9SfSmQMsBvV9YpfDb8tOG8LA3ZFT/3I2DBsVQD9g4uumWmWz8d8Ij0ypWJP8fxFx0mUBaJ9x4VndyI3Q+wdtCEVfKrTzXjR1b9tqNBruuXgQTgvmY1Ee4zThX/ziGZeXcw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718806525; c=relaxed/simple; bh=Et+6bg9ygYKyI2+mmGucP00F6/df/i/Onxfy/do1cD4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bLgBErHsvIrh+nCj2xUOQ5RjpuUbY30rdjvVGx3RSxoT1XLWwd2c5c/uPg/vmhiVkA8RXGf2PCK1HjHhgfvoFmPcHmCXloPgP1VumO7ZXyDKG5JoVSjIpTdBfUW+BWCZT7wMoBPKk1UYLN6hH0LA0x4P7Xq4rfSr4Wk3jfsO++M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=XM7KUXpJ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="XM7KUXpJ" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45J9llYP005109; Wed, 19 Jun 2024 14:15:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= sZR1edagXuuQElm3hgWV7NovGoUGtEWKak1GxlIYbaA=; b=XM7KUXpJoVFrUFhN E2vUISBLZKY3wovUDTuMMevrNsrlqvtMp7AYjhx3shKuvPHdcLBe3Xdz4odwl44h dj1o35AgK7sjqrkkJ1NbadCjbtmMmNIVDCQbJGPnpkoPAOzebDwlqw0uI37nL5nh ixRPCOCMQeE8mvJLcG4Btcm6P4jA17XNylw4q5GvCar4g7fjDxlqnyD5sxs0uPu+ 0lwDPFt6kQsHiu2WZqYiu1fVKC7+tAcGGJrjDztw+rX8pDrsbc8XNbI69WGr3kYR L4uVriEdTen79YggKkSBoaMm51X2qESYVW2nSBevgLea9uVgH4EMu4IF9Tu3ihFP KjibVw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3yuja79wgu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jun 2024 14:15:15 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45JEFDeZ022297 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jun 2024 14:15:13 GMT Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 19 Jun 2024 07:15:05 -0700 From: Jagadeesh Kona To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Stanimir Varbanov , Vikash Garodia , Bryan O'Donoghue , Mauro Carvalho Chehab , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Pavel Machek , Len Brown , Greg Kroah-Hartman , Konrad Dybcio , "Andy Gross" , Dmitry Baryshkov , Abel Vesa CC: , , , , , Taniya Das , "Jagadeesh Kona" , Satya Priya Kakitapalli , Imran Shaik , "Ajit Pandey" Subject: [PATCH V6 3/5] clk: qcom: gdsc: Add set and get hwmode callbacks to switch GDSC mode Date: Wed, 19 Jun 2024 19:44:11 +0530 Message-ID: <20240619141413.7983-4-quic_jkona@quicinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240619141413.7983-1-quic_jkona@quicinc.com> References: <20240619141413.7983-1-quic_jkona@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 4Y_Eb3EueTpbkdZdid8ig4QjuL3G5uIn X-Proofpoint-GUID: 4Y_Eb3EueTpbkdZdid8ig4QjuL3G5uIn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-19_02,2024-06-19_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=999 malwarescore=0 phishscore=0 bulkscore=0 suspectscore=0 clxscore=1015 spamscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406190106 Some GDSC client drivers require the GDSC mode to be switched dynamically to HW mode at runtime to gain the power benefits. Typically such client drivers require the GDSC to be brought up in SW mode initially to enable the required dependent clocks and configure the hardware to proper state. Once initial hardware set up is done, they switch the GDSC to HW mode to save power. At the end of usecase, they switch the GDSC back to SW mode and disable the GDSC. Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and get_hwmode_dev callbacks for GDSC's whose respective client drivers require the GDSC mode to be switched dynamically at runtime using dev_pm_genpd_set_hwmode() API. Signed-off-by: Jagadeesh Kona Signed-off-by: Abel Vesa Reviewed-by: Bryan O'Donoghue Reviewed-by: Taniya Das --- drivers/clk/qcom/gdsc.c | 42 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/gdsc.h | 1 + 2 files changed, 43 insertions(+) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index df9618ab7eea..6acc7af82255 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -363,6 +363,44 @@ static int gdsc_disable(struct generic_pm_domain *domain) return 0; } +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct device *dev, bool mode) +{ + struct gdsc *sc = domain_to_gdsc(domain); + int ret; + + ret = gdsc_hwctrl(sc, mode); + if (ret) + return ret; + + /* + * Wait for the GDSC to go through a power down and + * up cycle. In case SW/FW end up polling status + * bits for the gdsc before the power cycle is completed + * it might read the status wrongly. + */ + udelay(1); + + /* + * When GDSC is switched to HW mode, HW can disable the GDSC. + * When GDSC is switched back to SW mode, the GDSC will be enabled + * again, hence need to poll for GDSC to complete the power up. + */ + if (!mode) + return gdsc_poll_status(sc, GDSC_ON); + + return 0; +} + +static bool gdsc_get_hwmode(struct generic_pm_domain *domain, struct device *dev) +{ + struct gdsc *sc = domain_to_gdsc(domain); + u32 val; + + regmap_read(sc->regmap, sc->gdscr, &val); + + return !!(val & HW_CONTROL_MASK); +} + static int gdsc_init(struct gdsc *sc) { u32 mask, val; @@ -451,6 +489,10 @@ static int gdsc_init(struct gdsc *sc) sc->pd.power_off = gdsc_disable; if (!sc->pd.power_on) sc->pd.power_on = gdsc_enable; + if (sc->flags & HW_CTRL_TRIGGER) { + sc->pd.set_hwmode_dev = gdsc_set_hwmode; + sc->pd.get_hwmode_dev = gdsc_get_hwmode; + } ret = pm_genpd_init(&sc->pd, NULL, !on); if (ret) diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 803512688336..1e2779b823d1 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -67,6 +67,7 @@ struct gdsc { #define ALWAYS_ON BIT(6) #define RETAIN_FF_ENABLE BIT(7) #define NO_RET_PERIPH BIT(8) +#define HW_CTRL_TRIGGER BIT(9) struct reset_controller_dev *rcdev; unsigned int *resets; unsigned int reset_count; From patchwork Wed Jun 19 14:14:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13703897 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01E5B28DA0; Wed, 19 Jun 2024 14:15:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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Wed, 19 Jun 2024 14:15:34 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45JEFKwk014691 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jun 2024 14:15:20 GMT Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 19 Jun 2024 07:15:13 -0700 From: Jagadeesh Kona To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Stanimir Varbanov , Vikash Garodia , Bryan O'Donoghue , Mauro Carvalho Chehab , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Pavel Machek , Len Brown , Greg Kroah-Hartman , Konrad Dybcio , "Andy Gross" , Dmitry Baryshkov , Abel Vesa CC: , , , , , Taniya Das , "Jagadeesh Kona" , Satya Priya Kakitapalli , Imran Shaik , "Ajit Pandey" Subject: [PATCH V6 4/5] clk: qcom: videocc: Use HW_CTRL_TRIGGER for SM8250, SC7280 vcodec GDSC's Date: Wed, 19 Jun 2024 19:44:12 +0530 Message-ID: <20240619141413.7983-5-quic_jkona@quicinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240619141413.7983-1-quic_jkona@quicinc.com> References: <20240619141413.7983-1-quic_jkona@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: UE7GY50ZYfzPsZM6JH4rZufKg8CL0x-J X-Proofpoint-GUID: UE7GY50ZYfzPsZM6JH4rZufKg8CL0x-J X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-19_02,2024-06-19_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=785 impostorscore=0 priorityscore=1501 suspectscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406190107 For Venus V6 variant SoCs(sm8250, sc7280), the venus driver uses the newly introduced dev_pm_genpd_set_hwmode() API to switch the vcodec GDSC to HW/SW control modes at runtime. Hence use HW_CTRL_TRIGGER flag for vcodec GDSC's on sm8250, sc7280 to register the set_hwmode_dev & get_hwmode_dev callbacks for vcodec GDSC and allow the GDSC mode to be changed using dev_pm_genpd_set_hwmode() API. Signed-off-by: Jagadeesh Kona Signed-off-by: Abel Vesa Reviewed-by: Taniya Das --- drivers/clk/qcom/videocc-sc7280.c | 2 +- drivers/clk/qcom/videocc-sm8250.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/videocc-sc7280.c b/drivers/clk/qcom/videocc-sc7280.c index 317b325d6daf..88c90853cf6e 100644 --- a/drivers/clk/qcom/videocc-sc7280.c +++ b/drivers/clk/qcom/videocc-sc7280.c @@ -240,7 +240,7 @@ static struct gdsc mvs0_gdsc = { .name = "mvs0_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = HW_CTRL | RETAIN_FF_ENABLE, + .flags = HW_CTRL_TRIGGER | RETAIN_FF_ENABLE, }; static struct gdsc mvsc_gdsc = { diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index d7e0c32284c1..df479a69cddd 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -293,7 +293,7 @@ static struct gdsc mvs0_gdsc = { .pd = { .name = "mvs0_gdsc", }, - .flags = HW_CTRL, + .flags = HW_CTRL_TRIGGER, .pwrsts = PWRSTS_OFF_ON, }; @@ -302,7 +302,7 @@ static struct gdsc mvs1_gdsc = { .pd = { .name = "mvs1_gdsc", }, - .flags = HW_CTRL, + .flags = HW_CTRL_TRIGGER, .pwrsts = PWRSTS_OFF_ON, }; From patchwork Wed Jun 19 14:14:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13703896 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 850A028DA0; Wed, 19 Jun 2024 14:15:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718806539; cv=none; b=bDhYe+wCQo0XtR5IydTKcTxy/lp9g+tftZZclzmQfU4TxP/ds+R1qvpkBZWCFs+9SKLA3xbxuM14BhZ1OuHBKNHd0KIr0eEBxUv/YnViFZUDekqDPvH1HPBFiSPWgd9iEsKPclsMWkIuwTIiV0fvtPG2g5NNF4G8Gy35IBcbb+0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718806539; c=relaxed/simple; bh=EGaYFLGXnfHWlxLGmlwpGofz+AaoJSgY1Calo7leKj4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pTfzNYb4JQeI87iBCxj3EV02XQOrnyvzNVAgDIknKUZWcbEOv7gg5pJXmNpuI3AHSdjc9laIpIZVq9fzPwJJfTKXkhfgZ7aDukHFBac+SWHRfLqTIQR7Jwl+WE9UkYmkMv2WowGyMjkfwuRByvur8D5dAJcPvtwHV8FbVD7IN2I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=gVvC58Mu; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="gVvC58Mu" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45J9uMjq016040; Wed, 19 Jun 2024 14:15:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= iCv/YklMc+UPKcyKvWf9alp8n6dhbs3BgQ/OGTAGMqo=; b=gVvC58MuZ2y3f0n6 jaO6Dly0uagBvLSwjIE7McFDi1bR3Ly3W9jLd6Snk9a2pxLmrZtEhKg9OZq8g2Uu wUpsLcg/1dyhSrBK6crUvQcnMjYleS22r9G3ruR84UXzY0WVtsgD23Iv0s0jZVZa 19fMR9PQqgWfr/PMFdvDzRTvxWIEeBd9NEi2Ezcz67N6U2ObALUfbqlQykGIlxug QIgo+rajQktuqvZUHB4a84twB7LWuiIospLXTv4OLGKIhRMv4xEv2fWMeq6mf19L OJafnQuznx6Qw705w6nkDtWwO3xa7FZDh70PqxnfNzL+5op226z8890QA1RlIkpg okn3Zg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3yuja51wjs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jun 2024 14:15:29 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45JEFSLL022873 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jun 2024 14:15:28 GMT Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 19 Jun 2024 07:15:20 -0700 From: Jagadeesh Kona To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Stanimir Varbanov , Vikash Garodia , Bryan O'Donoghue , Mauro Carvalho Chehab , Ulf Hansson , "Rafael J . Wysocki" , Kevin Hilman , Pavel Machek , Len Brown , Greg Kroah-Hartman , Konrad Dybcio , "Andy Gross" , Dmitry Baryshkov , Abel Vesa CC: , , , , , Taniya Das , "Jagadeesh Kona" , Satya Priya Kakitapalli , Imran Shaik , "Ajit Pandey" Subject: [PATCH V6 5/5] venus: pm_helpers: Use dev_pm_genpd_set_hwmode to switch GDSC mode on V6 Date: Wed, 19 Jun 2024 19:44:13 +0530 Message-ID: <20240619141413.7983-6-quic_jkona@quicinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240619141413.7983-1-quic_jkona@quicinc.com> References: <20240619141413.7983-1-quic_jkona@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: EXSTL0n_KyN-LBjU4vGlXYO5Z5MjKAU_ X-Proofpoint-GUID: EXSTL0n_KyN-LBjU4vGlXYO5Z5MjKAU_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-19_02,2024-06-19_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 adultscore=0 impostorscore=0 clxscore=1015 mlxscore=0 spamscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406190106 The Venus driver requires vcodec GDSC to be ON in SW mode for clock operations and move it back to HW mode to gain power benefits. Earlier, as there is no interface to switch the GDSC mode from GenPD framework, the GDSC is moved to HW control mode as part of GDSC enable callback and venus driver is writing to its POWER_CONTROL register to keep the GDSC ON from SW whereever required. But the POWER_CONTROL register addresses are not constant and can vary across the variants. Also as per the HW recommendation, the GDSC mode switching needs to be controlled from respective GDSC register and this is a uniform approach across all the targets. Hence use dev_pm_genpd_set_hwmode() API which controls GDSC mode switching using its respective GDSC register. In venus V6 variants, the vcodec gdsc gets enabled in SW mode by default with new HW_CTRL_TRIGGER flag and there is no need to switch it to SW mode again after enable, hence add check to avoid switching gdsc to SW mode again after gdsc enable. Similarly add check to avoid switching GDSC to HW mode before disabling the GDSC, so GDSC gets enabled in SW mode in the next enable. Signed-off-by: Jagadeesh Kona Signed-off-by: Abel Vesa Tested-by: Bryan O'Donoghue Reviewed-by: Taniya Das --- .../media/platform/qcom/venus/pm_helpers.c | 39 +++++++++++-------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/drivers/media/platform/qcom/venus/pm_helpers.c b/drivers/media/platform/qcom/venus/pm_helpers.c index 502822059498..4ce76ce6dd4d 100644 --- a/drivers/media/platform/qcom/venus/pm_helpers.c +++ b/drivers/media/platform/qcom/venus/pm_helpers.c @@ -412,10 +412,9 @@ static int vcodec_control_v4(struct venus_core *core, u32 coreid, bool enable) u32 val; int ret; - if (IS_V6(core)) { - ctrl = core->wrapper_base + WRAPPER_CORE_POWER_CONTROL_V6; - stat = core->wrapper_base + WRAPPER_CORE_POWER_STATUS_V6; - } else if (coreid == VIDC_CORE_ID_1) { + if (IS_V6(core)) + return dev_pm_genpd_set_hwmode(core->pmdomains->pd_devs[coreid], !enable); + else if (coreid == VIDC_CORE_ID_1) { ctrl = core->wrapper_base + WRAPPER_VCODEC0_MMCC_POWER_CONTROL; stat = core->wrapper_base + WRAPPER_VCODEC0_MMCC_POWER_STATUS; } else { @@ -451,9 +450,11 @@ static int poweroff_coreid(struct venus_core *core, unsigned int coreid_mask) vcodec_clks_disable(core, core->vcodec0_clks); - ret = vcodec_control_v4(core, VIDC_CORE_ID_1, false); - if (ret) - return ret; + if (!IS_V6(core)) { + ret = vcodec_control_v4(core, VIDC_CORE_ID_1, false); + if (ret) + return ret; + } ret = pm_runtime_put_sync(core->pmdomains->pd_devs[1]); if (ret < 0) @@ -467,9 +468,11 @@ static int poweroff_coreid(struct venus_core *core, unsigned int coreid_mask) vcodec_clks_disable(core, core->vcodec1_clks); - ret = vcodec_control_v4(core, VIDC_CORE_ID_2, false); - if (ret) - return ret; + if (!IS_V6(core)) { + ret = vcodec_control_v4(core, VIDC_CORE_ID_2, false); + if (ret) + return ret; + } ret = pm_runtime_put_sync(core->pmdomains->pd_devs[2]); if (ret < 0) @@ -488,9 +491,11 @@ static int poweron_coreid(struct venus_core *core, unsigned int coreid_mask) if (ret < 0) return ret; - ret = vcodec_control_v4(core, VIDC_CORE_ID_1, true); - if (ret) - return ret; + if (!IS_V6(core)) { + ret = vcodec_control_v4(core, VIDC_CORE_ID_1, true); + if (ret) + return ret; + } ret = vcodec_clks_enable(core, core->vcodec0_clks); if (ret) @@ -506,9 +511,11 @@ static int poweron_coreid(struct venus_core *core, unsigned int coreid_mask) if (ret < 0) return ret; - ret = vcodec_control_v4(core, VIDC_CORE_ID_2, true); - if (ret) - return ret; + if (!IS_V6(core)) { + ret = vcodec_control_v4(core, VIDC_CORE_ID_2, true); + if (ret) + return ret; + } ret = vcodec_clks_enable(core, core->vcodec1_clks); if (ret)