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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-362c7c2dffdsm6277480f8f.35.2024.06.20.09.25.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jun 2024 09:25:58 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 1/4] mips: bmips: rework and cache CBR addr handling Date: Thu, 20 Jun 2024 17:26:42 +0200 Message-ID: <20240620152649.994-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240620152649.994-1-ansuelsmth@gmail.com> References: <20240620152649.994-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Rework the handling of the CBR address and cache it. This address doesn't change and can be cached instead of reading the register every time. This is in preparation of permitting to tweak the CBR address in DT with broken SoC or bootloader. bmips_cbr_addr is defined in setup.c for each arch to keep compatibility with legacy brcm47xx/brcm63xx and generic BMIPS target. Acked-by: Florian Fainelli Signed-off-by: Christian Marangi --- arch/mips/bcm47xx/prom.c | 3 +++ arch/mips/bcm47xx/setup.c | 4 ++++ arch/mips/bcm63xx/prom.c | 3 +++ arch/mips/bcm63xx/setup.c | 4 ++++ arch/mips/bmips/dma.c | 2 +- arch/mips/bmips/setup.c | 7 ++++++- arch/mips/include/asm/bmips.h | 1 + arch/mips/kernel/smp-bmips.c | 4 ++-- 8 files changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c index 58fb7c2dc3b8..66e3ee2b04e6 100644 --- a/arch/mips/bcm47xx/prom.c +++ b/arch/mips/bcm47xx/prom.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -110,6 +111,8 @@ static __init void prom_init_mem(void) void __init prom_init(void) { + /* Cache CBR addr before CPU/DMA setup */ + bmips_cbr_addr = BMIPS_GET_CBR(); prom_init_mem(); setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0); } diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 94bf839576c1..2f1ee0560aba 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -45,6 +46,9 @@ #include #include +/* CBR addr doesn't change and we can cache it */ +void __iomem *bmips_cbr_addr __read_mostly; + union bcm47xx_bus bcm47xx_bus; EXPORT_SYMBOL(bcm47xx_bus); diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index c3a2ea62c5c3..f21dd168171a 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -22,6 +22,9 @@ void __init prom_init(void) { u32 reg, mask; + /* Cache CBR addr before CPU/DMA setup */ + bmips_cbr_addr = BMIPS_GET_CBR(); + bcm63xx_cpu_init(); /* stop any running watchdog */ diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index c13ddb544a23..16ea8945ae3a 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,9 @@ #include #include +/* CBR addr doesn't change and we can cache it */ +void __iomem *bmips_cbr_addr __read_mostly; + void bcm63xx_machine_halt(void) { pr_info("System halted\n"); diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c index 3779e7855bd7..2bc9c0d4402f 100644 --- a/arch/mips/bmips/dma.c +++ b/arch/mips/bmips/dma.c @@ -9,7 +9,7 @@ bool bmips_rac_flush_disable; void arch_sync_dma_for_cpu_all(void) { - void __iomem *cbr = BMIPS_GET_CBR(); + void __iomem *cbr = bmips_cbr_addr; u32 cfg; if (boot_cpu_type() != CPU_BMIPS3300 && diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 66a8ba19c287..6dd166c3d643 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -34,6 +34,9 @@ #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) #define BCM6328_TP1_DISABLED BIT(9) +/* CBR addr doesn't change and we can cache it */ +void __iomem *bmips_cbr_addr __read_mostly; + extern bool bmips_rac_flush_disable; static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; @@ -111,7 +114,7 @@ static void bcm6358_quirks(void) * because the bootloader is not initializing it properly. */ bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) || - !!BMIPS_GET_CBR(); + !!bmips_cbr_addr; } static void bcm6368_quirks(void) @@ -144,6 +147,8 @@ static void __init bmips_init_cfe(void) void __init prom_init(void) { + /* Cache CBR addr before CPU/DMA setup */ + bmips_cbr_addr = BMIPS_GET_CBR(); bmips_init_cfe(); bmips_cpu_setup(); register_bmips_smp_ops(); diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h index 581a6a3c66e4..3a1cdfddb987 100644 --- a/arch/mips/include/asm/bmips.h +++ b/arch/mips/include/asm/bmips.h @@ -81,6 +81,7 @@ extern char bmips_smp_movevec[]; extern char bmips_smp_int_vec[]; extern char bmips_smp_int_vec_end[]; +extern void __iomem *bmips_cbr_addr; extern int bmips_smp_enabled; extern int bmips_cpu_offset; extern cpumask_t bmips_booted_mask; diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index b3dbf9ecb0d6..a4f84667a901 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -518,7 +518,7 @@ static void bmips_set_reset_vec(int cpu, u32 val) info.val = val; bmips_set_reset_vec_remote(&info); } else { - void __iomem *cbr = BMIPS_GET_CBR(); + void __iomem *cbr = bmips_cbr_addr; if (cpu == 0) __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); @@ -591,7 +591,7 @@ asmlinkage void __weak plat_wired_tlb_setup(void) void bmips_cpu_setup(void) { - void __iomem __maybe_unused *cbr = BMIPS_GET_CBR(); + void __iomem __maybe_unused *cbr = bmips_cbr_addr; u32 __maybe_unused cfg; switch (current_cpu_type()) { From patchwork Thu Jun 20 15:26:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13705863 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CBBF1B47BD; Thu, 20 Jun 2024 16:26:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718900763; cv=none; b=uIVZvepj+DyrFTkcto/pBNodAOUyn9jDHjjs/hEfqCE1t2wbvmSONUmuaLqSm/GRCJvsou3El6HArODqV3iqPQMbmJIT+vLUm1ycXYTsbAjQ+4h1p5Ilz26zQ+Yri0QReADmRJDJw3aF0e/izaAWJFXrRZChIgdptEs7NcFjJ0s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-362c7c2dffdsm6277480f8f.35.2024.06.20.09.25.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jun 2024 09:25:59 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Conor Dooley Subject: [PATCH v8 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property Date: Thu, 20 Jun 2024 17:26:43 +0200 Message-ID: <20240620152649.994-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240620152649.994-1-ansuelsmth@gmail.com> References: <20240620152649.994-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document brcm,bmips-cbr-reg property. Some SoC suffer from a BUG where CBR(Core Base Register) address might be badly or never initialized by the Bootloader or reading it from co-processor registers, if the system boots from secondary CPU, results in invalid address. The CBR address is always the same on the SoC. Usage of this property is to give an address also in these broken configuration/bootloader. Signed-off-by: Christian Marangi Acked-by: Conor Dooley Reviewed-by: Rob Herring (Arm) Acked-by: Florian Fainelli --- .../devicetree/bindings/mips/brcm/soc.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml index 975945ca2888..0cc634482a6a 100644 --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml @@ -55,6 +55,16 @@ properties: under the "cpus" node. $ref: /schemas/types.yaml#/definitions/uint32 + brcm,bmips-cbr-reg: + description: Reference address of the CBR. + Some SoC suffer from a BUG where CBR(Core Base Register) + address might be badly or never initialized by the Bootloader + or reading it from co-processor registers, if the system boots + from secondary CPU, results in invalid address. + The CBR address is always the same on the SoC hence it + can be provided in DT to handle these broken case. + $ref: /schemas/types.yaml#/definitions/uint32 + patternProperties: "^cpu@[0-9]$": type: object @@ -64,6 +74,20 @@ properties: required: - mips-hpt-frequency +if: + properties: + compatible: + contains: + enum: + - brcm,bcm6358 + - brcm,bcm6368 + +then: + properties: + cpus: + required: + - brcm,bmips-cbr-reg + additionalProperties: true examples: From patchwork Thu Jun 20 15:26:44 2024 Content-Type: text/plain; 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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-362c7c2dffdsm6277480f8f.35.2024.06.20.09.26.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jun 2024 09:26:00 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 3/4] mips: bmips: setup: make CBR address configurable Date: Thu, 20 Jun 2024 17:26:44 +0200 Message-ID: <20240620152649.994-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240620152649.994-1-ansuelsmth@gmail.com> References: <20240620152649.994-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support to provide CBR address from DT to handle broken SoC/Bootloader that doesn't correctly init it. This permits to use the RAC flush even in these condition. To provide a CBR address from DT, the property "brcm,bmips-cbr-reg" needs to be set in the "cpus" node. On DT init, this property presence will be checked and will set the bmips_cbr_addr value accordingly. Also bmips_rac_flush_disable will be set to false as RAC flush can be correctly supported. The CBR address from DT will overwrite the cached one and the one set in the CBR register will be ignored. Also the DT CBR address is validated on being outside DRAM window. Signed-off-by: Christian Marangi Acked-by: Florian Fainelli --- arch/mips/bcm47xx/setup.c | 6 +++++- arch/mips/bcm63xx/setup.c | 6 +++++- arch/mips/bmips/setup.c | 30 ++++++++++++++++++++++++++++-- 3 files changed, 38 insertions(+), 4 deletions(-) diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 2f1ee0560aba..247be207f293 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -46,7 +46,11 @@ #include #include -/* CBR addr doesn't change and we can cache it */ +/* + * CBR addr doesn't change and we can cache it. + * For broken SoC/Bootloader CBR addr might also be provided via DT + * with "brcm,bmips-cbr-reg" in the "cpus" node. + */ void __iomem *bmips_cbr_addr __read_mostly; union bcm47xx_bus bcm47xx_bus; diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index 16ea8945ae3a..81529084bc75 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -23,7 +23,11 @@ #include #include -/* CBR addr doesn't change and we can cache it */ +/* + * CBR addr doesn't change and we can cache it. + * For broken SoC/Bootloader CBR addr might also be provided via DT + * with "brcm,bmips-cbr-reg" in the "cpus" node. + */ void __iomem *bmips_cbr_addr __read_mostly; void bcm63xx_machine_halt(void) diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 6dd166c3d643..2572fd49a6e9 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -34,7 +34,11 @@ #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) #define BCM6328_TP1_DISABLED BIT(9) -/* CBR addr doesn't change and we can cache it */ +/* + * CBR addr doesn't change and we can cache it. + * For broken SoC/Bootloader CBR addr might also be provided via DT + * with "brcm,bmips-cbr-reg" in the "cpus" node. + */ void __iomem *bmips_cbr_addr __read_mostly; extern bool bmips_rac_flush_disable; @@ -208,13 +212,35 @@ void __init plat_mem_setup(void) void __init device_tree_init(void) { struct device_node *np; + u32 addr; unflatten_and_copy_device_tree(); /* Disable SMP boot unless both CPUs are listed in DT and !disabled */ np = of_find_node_by_name(NULL, "cpus"); - if (np && of_get_available_child_count(np) <= 1) + if (!np) + return; + + if (of_get_available_child_count(np) <= 1) bmips_smp_enabled = 0; + + /* Check if DT provide a CBR address */ + if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr)) + goto exit; + + /* Make sure CBR address is outside DRAM window */ + if (addr >= (u32)memblock_start_of_DRAM() && + addr < (u32)memblock_end_of_DRAM()) { + WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n", + addr); + goto exit; + } + + bmips_cbr_addr = (void __iomem *)addr; + /* Since CBR is provided by DT, enable RAC flush */ + bmips_rac_flush_disable = false; + +exit: of_node_put(np); } From patchwork Thu Jun 20 15:26:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13705865 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4714C1B4C3B; Thu, 20 Jun 2024 16:26:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718900766; cv=none; b=L1BKcgwI7j8MX/NblBvEqos5DsJTbNAVxHa6eSh52YHA+ADQXBP9z7j8WBuAAT7c0844GIRKgYPkjgdLsFRkgL8nANqSxCt7l6h9+Vc888Bkk0SZUZX8EHK9V8oSGiXYwQlzeiaFgBInnAyDY858IhuK3RA01/RYuZTEkwNTagg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718900766; c=relaxed/simple; bh=Ua5Wlts7wNpHZL5hvbWj8KXVM7QOoXJPqG8In6tdSdY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EHgDR4s8JjjJ5GV0/m5HK6435MY3G66SD4cZF+CZF3Mh5QkthhmiwmgDn5FabxRBIbvSe4gvPuH3sfXAKE0h4aFCWkOxoRczsKZAzAWRd+YmOnkah4GhCp+kprNP0LNChYmvwz9dzAFWdIWhW+RHKsS39msYAONar+KatFnsgPo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=knoIvOUE; arc=none smtp.client-ip=209.85.221.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="knoIvOUE" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-361785bfa71so915019f8f.2; Thu, 20 Jun 2024 09:26:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1718900762; x=1719505562; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oyhPAil700VgPIg6DuQD4ahisl4U/95chdTNhKoOxhQ=; b=knoIvOUEzwjJAkEudwHK12CcvEuFhurFeXGDAqK5Q6CHHSRlqh4AHOPwtwbow6ohDG Fqm19ZllgWhbdeZsBSzOq+x+HdqiUbAvL2BcJVkP3DO8Kus90FzyiPmlft5UMbhPzls2 hADni9wgq+aV1lJllubiiPgJ5F5awc42z3v2oA/l4MN+pbTbhU9/yKyNFVI9tFv0/7kH /MteP3Kt+Z05LBmv8R1Cks9mNiSkX1WeaAeLeqhev5+0mL4ijUmTHhQExJeYaZ7YfTC8 8HXiGjjFOPinE8TttUw4aZ4Z9yTWUk+2dTrBQqWdxJfXjJwTAaK3Xd8sflNpx8r973vE iuZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718900762; x=1719505562; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oyhPAil700VgPIg6DuQD4ahisl4U/95chdTNhKoOxhQ=; b=RnLj1/62GYcYrt2nppGfCS1B7JYRrECneRGAeiMKCzRK3BQlG4TsP+p3yDPbwiYhPS DGuOXVUfHYBde43a3NSfItFqtdPyUepSHRRHvDF4TuY2c1l9ARvuzb9HEjjYfHR8WCBX O/iyNn39OkWXBIwck66rqffGG15oTvM6PJIJN0UWUinOfGipGTHZa6MpcsZr2RTxJ65o e8B2v/IYdYGRF1+sZnLDqK8qDXj0iBsASWoxbmTZ4a2bLDQeFg+F2XY8KnrQ3xesV8mO 40gVGDb9zTfE/LzO0q6RXz1hloyzB9Kk9J4DRt6YpdJJh2DYLO/CAC/GvGabE5MTJPp1 e+OA== X-Forwarded-Encrypted: i=1; AJvYcCWfr0XIdPSUD3Kjcd/77ql60IVNV3HAjNr4Iy8dQgTZZ5LWzT1DompuAvol10Phub8dF6Tz9RbUaYWa+jzVnZbnniobmgqkUrztV5nZ5VcR/7Psz4tJ6V1VpPwJ1LpO/gBw0e2FetEer79tD13jIt0jiwzC8VU86aTnj9i6XuUm0ehdn7o= X-Gm-Message-State: AOJu0Yz87wA9a9hy2AaklVhMYVWnCOBfyx/UaFyJC/xA9i++WRqhdfqS 26Baz9e5mrGc6AaDTim+rw7v5wUvgn06OU1+IHLteWO6FxX4ctHs X-Google-Smtp-Source: AGHT+IGIY10g7FmHbibRhqlObKCnHDMnPOxDLE1jTG94vjc+tPuD9nHsAzb92AMmiz35tyYnPaf8cQ== X-Received: by 2002:a5d:69c8:0:b0:360:8476:678a with SMTP id ffacd0b85a97d-363192ce1camr4012556f8f.45.1718900762401; Thu, 20 Jun 2024 09:26:02 -0700 (PDT) Received: from localhost.localdomain (93-34-90-105.ip49.fastwebnet.it. [93.34.90.105]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-362c7c2dffdsm6277480f8f.35.2024.06.20.09.26.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jun 2024 09:26:02 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?utf-8?q?Daniel_Gonz=C3=A1lez_Cabanelas?= , =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= Subject: [PATCH v8 4/4] mips: bmips: enable RAC on BMIPS4350 Date: Thu, 20 Jun 2024 17:26:45 +0200 Message-ID: <20240620152649.994-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240620152649.994-1-ansuelsmth@gmail.com> References: <20240620152649.994-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel González Cabanelas The data RAC is left disabled by the bootloader in some SoCs, at least in the core it boots from. Enabling this feature increases the performance up to +30% depending on the task. Signed-off-by: Daniel González Cabanelas Signed-off-by: Álvaro Fernández Rojas [ rework code and reduce code duplication ] Acked-by: Florian Fainelli Signed-off-by: Christian Marangi --- arch/mips/kernel/smp-bmips.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index a4f84667a901..35b8d810833c 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -592,6 +592,7 @@ asmlinkage void __weak plat_wired_tlb_setup(void) void bmips_cpu_setup(void) { void __iomem __maybe_unused *cbr = bmips_cbr_addr; + u32 __maybe_unused rac_addr; u32 __maybe_unused cfg; switch (current_cpu_type()) { @@ -620,6 +621,23 @@ void bmips_cpu_setup(void) __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); break; + case CPU_BMIPS4350: + rac_addr = BMIPS_RAC_CONFIG_1; + + if (!(read_c0_brcm_cmt_local() & (1 << 31))) + rac_addr = BMIPS_RAC_CONFIG; + + /* Enable data RAC */ + cfg = __raw_readl(cbr + rac_addr); + __raw_writel(cfg | 0xf, cbr + rac_addr); + __raw_readl(cbr + rac_addr); + + /* Flush stale data out of the readahead cache */ + cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); + __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); + __raw_readl(cbr + BMIPS_RAC_CONFIG); + break; + case CPU_BMIPS4380: /* CBG workaround for early BMIPS4380 CPUs */ switch (read_c0_prid()) {