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[2001:4c4e:1812:9200:74ca:f940:6985:b739]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d30535005sm60919a12.69.2024.06.20.14.52.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jun 2024 14:52:12 -0700 (PDT) From: =?utf-8?b?QmFybmFiw6FzIEN6w6ltw6Fu?= Date: Thu, 20 Jun 2024 23:52:09 +0200 Subject: [PATCH v2] drm/msm/adreno: Add A306A support MIME-Version: 1.0 Message-Id: <20240620-a306a-v2-1-0d388e1deebf@gmail.com> X-B4-Tracking: v=1; b=H4sIAIikdGYC/13OTWrDMBCG4asYraugH3s8MiX0HiWLkTROROO4k VzTEnL3Ks6i0OU3DA/vTRTOiYsYmpvIvKaS5ksd5qUR4USXI8sU6xZGmVZ1BiVZBSRbZN3b3rQ Rgqi/n5nH9L0574e6T6ksc/7Z2FU/rv+FVUstlSWASCFi6N+OE6XzLsyTONyfZObrVy1anq6Yu BTaiobmdeNAo4bWKrsDAN1VMc8+hjPljz9u/wj0VFjWMaVlaLxzxvcuEPpgLYyEbAIq55TvaET FEcd6jjXk/gvuY3GTIgEAAA== To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, =?utf-8?q?O?= =?utf-8?q?tto_Pfl=C3=BCger?= , =?utf-8?b?QmFybmFi?= =?utf-8?b?w6FzIEN6w6ltw6Fu?= , 20240618164303.66615-1-robdclark@gmail.com X-Mailer: b4 0.14.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Otto Pflüger Add support for Adreno 306A GPU what is found in MSM8917 SoC. This GPU marketing name is Adreno 308. Signed-off-by: Otto Pflüger [use internal name of the GPU, reword the commit message] Signed-off-by: Barnabás Czémán Reviewed-by: Konrad Dybcio --- Changes in v2: - Rebase on https://patchwork.freedesktop.org/series/127393/ - Link to v1: https://lore.kernel.org/r/20240528-a306a-v1-1-03a66dacd8c7@gmail.com --- drivers/gpu/drm/msm/adreno/a3xx_catalog.c | 11 +++++++++++ drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 14 +++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++++++ 3 files changed, 28 insertions(+), 3 deletions(-) --- base-commit: b992b79ca8bc336fa8e2c80990b5af80ed8f36fd change-id: 20240528-a306a-48e173724d6c prerequisite-message-id: <20240618164303.66615-1-robdclark@gmail.com> prerequisite-patch-id: b26cd6e5aa23ea623fec94f938a06d1e3359de55 prerequisite-patch-id: 301e8fe4c2687a4606ee7debce95a5ada732e27f prerequisite-patch-id: 24a5654d9b52079c010b0594d8599d84af1659c7 prerequisite-patch-id: b09a3d28d04b7ebe968e05835ebf8397c27f8d7d prerequisite-patch-id: a74556e25862c22f0ec543b8a7c7d92cb2e55099 Best regards, diff --git a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c index 0de8465b6cf0..61aeac5054a2 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c @@ -41,6 +41,17 @@ static const struct adreno_info a3xx_gpus[] = { .gmem = SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x03000620), + .family = ADRENO_3XX, + .revn = 308, + .fw = { + [ADRENO_FW_PM4] = "a300_pm4.fw", + [ADRENO_FW_PFP] = "a300_pfp.fw", + }, + .gmem = SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a3xx_gpu_init, }, { .chip_ids = ADRENO_CHIP_IDS( 0x03020000, diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index 5273dc849838..b46ff49f47cf 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -145,6 +145,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003); gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a); gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a); + } else if (adreno_is_a306a(adreno_gpu)) { + gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003); + gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000010); + gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000010); } else if (adreno_is_a320(adreno_gpu)) { /* Set up 16 deep read/write request queues: */ gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); @@ -237,7 +241,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001); /* Enable Clock gating: */ - if (adreno_is_a305b(adreno_gpu) || adreno_is_a306(adreno_gpu)) + if (adreno_is_a305b(adreno_gpu) || + adreno_is_a306(adreno_gpu) || + adreno_is_a306a(adreno_gpu)) gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa); else if (adreno_is_a320(adreno_gpu)) gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff); @@ -334,8 +340,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]); /* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */ - if (adreno_is_a305(adreno_gpu) || adreno_is_a306(adreno_gpu) || - adreno_is_a320(adreno_gpu)) { + if (adreno_is_a305(adreno_gpu) || + adreno_is_a306(adreno_gpu) || + adreno_is_a306a(adreno_gpu) || + adreno_is_a320(adreno_gpu)) { gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) | AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) | diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index b8ee9320a315..3b361a077688 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -292,6 +292,12 @@ static inline bool adreno_is_a306(const struct adreno_gpu *gpu) return adreno_is_revn(gpu, 307); } +static inline bool adreno_is_a306a(const struct adreno_gpu *gpu) +{ + /* a306a marketing name is a308 */ + return adreno_is_revn(gpu, 308); +} + static inline bool adreno_is_a320(const struct adreno_gpu *gpu) { return adreno_is_revn(gpu, 320);