From patchwork Fri Jun 21 09:38:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13707175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2D51C27C4F for ; Fri, 21 Jun 2024 09:38:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 88586C32781; Fri, 21 Jun 2024 09:38:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D9F71C4AF0B; Fri, 21 Jun 2024 09:38:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718962721; bh=vj6EQMvMATxpuv+etEjf5cI+Mx7UlzGS/ax61uO76rA=; h=From:List-Id:To:Cc:Subject:Date:In-Reply-To:References:From; b=Jd5mVQbk0jTQGRuaCYBn+mTNhDYwXfKLzsyDX4skZSpVKxtIvp3Ed9a3ruEOLVIMR RRV0nWuxzB3Lh21r1t8/HEp1/TcN+Uh0HWvFsNfSeWhizc8027K9To2Zq2rNmd1MGX RcSIj7L6oGa2GZflXxtDgJv3ia9BiMaGciq3qdmoiHRgViNGuQbDl/cmV9Muxil1bo /3rkkPXaNFRy9OwN5UdoKAZ1h7ziXiYu1b+2IEPTPX5G/Vy/tA/ALRuHnWxdv1pPx8 my3odinsO8NxougcTMTJO+ruZmupd9Ii6aPyUdWNYnXfE/zH2x9L8mAVSbqQabY/Ys cWsxjuZ4oCR+Q== From: =?utf-8?q?Marek_Beh=C3=BAn?= List-Id: To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , Arnd Bergmann , soc@kernel.org, linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v3 1/5] irqchip/armada-370-xp: Do not allow mapping IRQ 0 and 1 Date: Fri, 21 Jun 2024 11:38:28 +0200 Message-ID: <20240621093832.23319-2-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240621093832.23319-1-kabel@kernel.org> References: <20240621093832.23319-1-kabel@kernel.org> MIME-Version: 1.0 From: Pali Rohár IRQs 0 (IPI) and 1 (MSI) are handled internally by this driver, generic_handle_domain_irq() is never called for these IRQs. Disallow mapping these IRQs. Signed-off-by: Pali Rohár [ changed commit message ] Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn --- drivers/irqchip/irq-armada-370-xp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 4b021a67bdfe..f488c35d9130 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -566,6 +566,10 @@ static struct irq_chip armada_370_xp_irq_chip = { static int armada_370_xp_mpic_irq_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { + /* IRQs 0 and 1 cannot be mapped, they are handled internally */ + if (hw <= 1) + return -EINVAL; + armada_370_xp_irq_mask(irq_get_irq_data(virq)); if (!is_percpu_irq(hw)) writel(hw, per_cpu_int_base + From patchwork Fri Jun 21 09:38:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13707176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC563C27C4F for ; Fri, 21 Jun 2024 09:38:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 921BCC4AF09; Fri, 21 Jun 2024 09:38:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E31A6C2BBFC; Fri, 21 Jun 2024 09:38:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718962724; bh=rjmq+a+eqDmXMO7oWjSTlXXoL3t36KVhnFeyO68IOhY=; h=From:List-Id:To:Cc:Subject:Date:In-Reply-To:References:From; b=tWtsPAWN7tacbP8TqQBX9XZ7Nw4o3usNXKyuJwXs2LsAfEKGWFm83kMtdDjX0Lgkr jduC01mgYAfQvu3UCbhSZkRklwDrbTPy0AhWgtheYU0+vGd4Getl6rCtLWxtTbHQCH hRk+woHJxOUDQiRhc5qj1dAEyPM3kHR870VTHm4R0Dw59CIOJatYnfcQg2x5WGSg8H 39J90qpMhsf8s8sWLIoFOWa0ifJKQSivenJN/fLv9e7kBIkA7p1iuW0OdbnQwa8OpI Yqa9ZdmSP8mJyrf/5tmNnhP5wtLfKeBbXv2jpAFrd3xEoB8XDasEhZFsP730uOCHX4 AsAGQNyDT2A5w== From: =?utf-8?q?Marek_Beh=C3=BAn?= List-Id: To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , Arnd Bergmann , soc@kernel.org, linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v3 2/5] irqchip/armada-370-xp: Only call ipi_resume() if IPI is available Date: Fri, 21 Jun 2024 11:38:29 +0200 Message-ID: <20240621093832.23319-3-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240621093832.23319-1-kabel@kernel.org> References: <20240621093832.23319-1-kabel@kernel.org> MIME-Version: 1.0 From: Pali Rohár IPI is available only on systems where the mpic controller does not have a parent IRQ defined (e.g. on Armada XP). If a parent IRQ is defined, inter-processor interrupts are handled by an interrupt controller higher in the hierarchy (most probably a parent GIC). Only call ipi_resume() on systems where IPI is available in the mpic controller. Signed-off-by: Pali Rohár [ refactored a little and changed commit message ] Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn --- drivers/irqchip/irq-armada-370-xp.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index f488c35d9130..ea95e327f672 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -156,6 +157,17 @@ static DEFINE_MUTEX(msi_used_lock); static phys_addr_t msi_doorbell_addr; #endif +static inline bool is_ipi_available(void) +{ + /* + * We distinguish IPI availability in the IC by the IC not having a + * parent irq defined. If a parent irq is defined, there is a parent + * interrupt controller (e.g. GIC) that takes care of inter-processor + * interrupts. + */ + return parent_irq <= 0; +} + static inline bool is_percpu_irq(irq_hw_number_t irq) { if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS) @@ -527,7 +539,8 @@ static void armada_xp_mpic_reenable_percpu(void) armada_370_xp_irq_unmask(data); } - ipi_resume(); + if (is_ipi_available()) + ipi_resume(); armada_370_xp_msi_reenable_percpu(); } @@ -750,7 +763,8 @@ static void armada_370_xp_mpic_resume(void) if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK) writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); - ipi_resume(); + if (is_ipi_available()) + ipi_resume(); } static struct syscore_ops armada_370_xp_mpic_syscore_ops = { From patchwork Fri Jun 21 09:38:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13707177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B375DC27C4F for ; Fri, 21 Jun 2024 09:38:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 9B5B2C32781; Fri, 21 Jun 2024 09:38:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ECC07C4AF09; Fri, 21 Jun 2024 09:38:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718962727; bh=dZrLVKTdPiccjRN/nS6wrH8xra7iqcEJWj9cQdWfU3Y=; h=From:List-Id:To:Cc:Subject:Date:In-Reply-To:References:From; b=Viez9LUpLhXHiFu+0/0n8UqsEqbwBNJRjj4DKvzSbPQmn6qVtTPbk4ULWIyyZblu+ cq/jJ31HIvMJIbiXqD2IypwKXrVQEsRN92hhIGfckmEjslLqSo9ODKQ8iQNGFDqxI+ 9zVFNjQ+QumvAdDn12NRyhG5MXH+Zz5hgUJKCyci1115m91JF1N1rLEf+iY/Xk2ID0 b2au888hEOzOI5hMhaCQTNGw7Qfxg/dEtRvsdxEFi7bAOaOFG1nyi4SgnaqJ7tvPu4 AJ023XhL3iHptBlGBlAI/urjDyKfSrA5/GGOsdm6XuvW3fXeXuCtK1aMxqEQ1gYWfn kNBlOw46lzkkg== From: =?utf-8?q?Marek_Beh=C3=BAn?= List-Id: To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , Arnd Bergmann , soc@kernel.org, linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v3 3/5] irqchip/armada-370-xp: Do not touch IPI registers on platforms without IPI Date: Fri, 21 Jun 2024 11:38:30 +0200 Message-ID: <20240621093832.23319-4-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240621093832.23319-1-kabel@kernel.org> References: <20240621093832.23319-1-kabel@kernel.org> MIME-Version: 1.0 From: Pali Rohár On platforms where IPI is not available in the MPIC, the IPI registers instead represent an additional set of MSI interrupt registers (currently unused by the driver). Do not touch these registers on platforms where IPI is not available in the MPIC. Signed-off-by: Pali Rohár [ refactored, changed commit message ] Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn --- drivers/irqchip/irq-armada-370-xp.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index ea95e327f672..aca64de4e3f8 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -508,6 +508,9 @@ static void armada_xp_mpic_smp_cpu_init(void) for (i = 0; i < nr_irqs; i++) writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); + if (!is_ipi_available()) + return; + /* Disable all IPIs */ writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); @@ -758,7 +761,7 @@ static void armada_370_xp_mpic_resume(void) /* Reconfigure doorbells for IPIs and MSIs */ writel(doorbell_mask_reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); - if (doorbell_mask_reg & IPI_DOORBELL_MASK) + if (is_ipi_available() && (doorbell_mask_reg & IPI_DOORBELL_MASK)) writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK) writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); @@ -809,13 +812,18 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node, BUG_ON(!armada_370_xp_mpic_domain); irq_domain_update_bus_token(armada_370_xp_mpic_domain, DOMAIN_BUS_WIRED); + /* + * Initialize parent_irq before calling any other functions, since it is + * used to distinguish between IPI and non-IPI platforms. + */ + parent_irq = irq_of_parse_and_map(node, 0); + /* Setup for the boot CPU */ armada_xp_mpic_perf_init(); armada_xp_mpic_smp_cpu_init(); armada_370_xp_msi_init(node, main_int_res.start); - parent_irq = irq_of_parse_and_map(node, 0); if (parent_irq <= 0) { irq_set_default_host(armada_370_xp_mpic_domain); set_handle_irq(armada_370_xp_handle_irq); From patchwork Fri Jun 21 09:38:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13707178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BFF6EC2BA1A for ; Fri, 21 Jun 2024 09:38:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id A4CDFC32781; Fri, 21 Jun 2024 09:38:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 01C13C2BBFC; Fri, 21 Jun 2024 09:38:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718962730; bh=BxDi/2A/VpuLHj7Y7p1xYV7lGTZaxc9UA9RFY1emoOA=; h=From:List-Id:To:Cc:Subject:Date:In-Reply-To:References:From; b=VDDuJzigS8WBss4wiIY69MeRAwvbV+ziPD/anwU8G7q6Cs4mL9teBAO/9CLBaJuF6 365PpZmKRYhhhp3/x0df4bhEx5QltLapwOuGlkykJcsSuqjduOa2o5BxILGVbLBqla CtyKR6mG3Qm1vIcNtugqoEVNwYuCmaPwVOYorOwUnwTeEX3iC2hk9eIdci0U2kPaoi ZrjBOpmEjLfjka4IYrzkAQ+0QTFFdlzTktoJO7yR3kVaVKjrMfe9P/JDqzRi4nIzhI bVxfEErAqWKlLNftWa4Ls+1CGVzMPr4F2zh6OASj4R3ge8s1yK/mmIWnXBpwnonSg1 A3YxGAIEORlhQ== From: =?utf-8?q?Marek_Beh=C3=BAn?= List-Id: To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , Arnd Bergmann , soc@kernel.org, linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v3 4/5] irqchip/armada-370-xp: Add support for 32 MSI interrupts on non-IPI platforms Date: Fri, 21 Jun 2024 11:38:31 +0200 Message-ID: <20240621093832.23319-5-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240621093832.23319-1-kabel@kernel.org> References: <20240621093832.23319-1-kabel@kernel.org> MIME-Version: 1.0 From: Pali Rohár The doorbell interrupts have the following layout on IPI vs no-IPI platforms: | 0...7 | 8...15 | 16...31 | ------------------+---------+----------+---------------------+ IPI platform | IPI | n/a | MSI | ------------------+---------+----------+---------------------+ non-IPI platform | MSI | ------------------+------------------------------------------+ Currently the driver only allows for the upper 16...31 interrupts for MSI domain (i.e. the MSI domain has only 16 interrupts). On platforms where IPI is not available, we can use whole 32 MSI interrupts. Implement support also for the lower 16 MSI interrupts on non-IPI platforms. Signed-off-by: Pali Rohár [ refactored, changed commit message ] Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn --- drivers/irqchip/irq-armada-370-xp.c | 77 +++++++++++++++++++++++------ 1 file changed, 63 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index aca64de4e3f8..ada257aeba78 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -13,6 +13,7 @@ * warranty of any kind, whether express or implied. */ +#include #include #include #include @@ -136,6 +137,7 @@ #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) +/* IPI and MSI interrupt definitions for IPI platforms */ #define IPI_DOORBELL_START (0) #define IPI_DOORBELL_END (8) #define IPI_DOORBELL_MASK 0xFF @@ -144,6 +146,14 @@ #define PCI_MSI_DOORBELL_END (32) #define PCI_MSI_DOORBELL_MASK 0xFFFF0000 +/* MSI interrupt definitions for non-IPI platforms */ +#define PCI_MSI_FULL_DOORBELL_START 0 +#define PCI_MSI_FULL_DOORBELL_NR 32 +#define PCI_MSI_FULL_DOORBELL_END 32 +#define PCI_MSI_FULL_DOORBELL_MASK GENMASK(31, 0) +#define PCI_MSI_FULL_DOORBELL_SRC0_MASK GENMASK(15, 0) +#define PCI_MSI_FULL_DOORBELL_SRC1_MASK GENMASK(31, 16) + static void __iomem *per_cpu_int_base; static void __iomem *main_int_base; static struct irq_domain *armada_370_xp_mpic_domain; @@ -152,7 +162,7 @@ static int parent_irq; #ifdef CONFIG_PCI_MSI static struct irq_domain *armada_370_xp_msi_domain; static struct irq_domain *armada_370_xp_msi_inner_domain; -static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR); +static DECLARE_BITMAP(msi_used, PCI_MSI_FULL_DOORBELL_NR); static DEFINE_MUTEX(msi_used_lock); static phys_addr_t msi_doorbell_addr; #endif @@ -168,6 +178,30 @@ static inline bool is_ipi_available(void) return parent_irq <= 0; } +static inline u32 msi_doorbell_mask(void) +{ + return is_ipi_available() ? PCI_MSI_DOORBELL_MASK : + PCI_MSI_FULL_DOORBELL_MASK; +} + +static inline unsigned int msi_doorbell_start(void) +{ + return is_ipi_available() ? PCI_MSI_DOORBELL_START : + PCI_MSI_FULL_DOORBELL_START; +} + +static inline unsigned int msi_doorbell_size(void) +{ + return is_ipi_available() ? PCI_MSI_DOORBELL_NR : + PCI_MSI_FULL_DOORBELL_NR; +} + +static inline unsigned int msi_doorbell_end(void) +{ + return is_ipi_available() ? PCI_MSI_DOORBELL_END : + PCI_MSI_FULL_DOORBELL_END; +} + static inline bool is_percpu_irq(irq_hw_number_t irq) { if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS) @@ -225,7 +259,7 @@ static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg msg->address_lo = lower_32_bits(msi_doorbell_addr); msg->address_hi = upper_32_bits(msi_doorbell_addr); - msg->data = BIT(cpu + 8) | (data->hwirq + PCI_MSI_DOORBELL_START); + msg->data = BIT(cpu + 8) | (data->hwirq + msi_doorbell_start()); } static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data, @@ -258,7 +292,7 @@ static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq, int hwirq, i; mutex_lock(&msi_used_lock); - hwirq = bitmap_find_free_region(msi_used, PCI_MSI_DOORBELL_NR, + hwirq = bitmap_find_free_region(msi_used, msi_doorbell_size(), order_base_2(nr_irqs)); mutex_unlock(&msi_used_lock); @@ -295,9 +329,10 @@ static void armada_370_xp_msi_reenable_percpu(void) u32 reg; /* Enable MSI doorbell mask and combined cpu local interrupt */ - reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS) - | PCI_MSI_DOORBELL_MASK; + reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); + reg |= msi_doorbell_mask(); writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); + /* Unmask local doorbell interrupt */ writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); } @@ -309,7 +344,7 @@ static int armada_370_xp_msi_init(struct device_node *node, ARMADA_370_XP_SW_TRIG_INT_OFFS; armada_370_xp_msi_inner_domain = - irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR, + irq_domain_add_linear(NULL, msi_doorbell_size(), &armada_370_xp_msi_domain_ops, NULL); if (!armada_370_xp_msi_inner_domain) return -ENOMEM; @@ -325,6 +360,10 @@ static int armada_370_xp_msi_init(struct device_node *node, armada_370_xp_msi_reenable_percpu(); + /* Unmask low 16 MSI irqs on non-IPI platforms */ + if (!is_ipi_available()) + writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); + return 0; } #else @@ -619,20 +658,20 @@ static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained) u32 msimask, msinr; msimask = readl_relaxed(per_cpu_int_base + - ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) - & PCI_MSI_DOORBELL_MASK; + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); + msimask &= msi_doorbell_mask(); writel(~msimask, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); - for (msinr = PCI_MSI_DOORBELL_START; - msinr < PCI_MSI_DOORBELL_END; msinr++) { + for (msinr = msi_doorbell_start(); + msinr < msi_doorbell_end(); msinr++) { unsigned int irq; if (!(msimask & BIT(msinr))) continue; - irq = msinr - PCI_MSI_DOORBELL_START; + irq = msinr - msi_doorbell_start(); generic_handle_domain_irq(armada_370_xp_msi_inner_domain, irq); } @@ -661,7 +700,7 @@ static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc) if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid))) continue; - if (irqn == 1) { + if (irqn == 0 || irqn == 1) { armada_370_xp_handle_msi_irq(NULL, true); continue; } @@ -722,6 +761,7 @@ static int armada_370_xp_mpic_suspend(void) static void armada_370_xp_mpic_resume(void) { + bool src0, src1; int nirqs; irq_hw_number_t irq; @@ -761,9 +801,18 @@ static void armada_370_xp_mpic_resume(void) /* Reconfigure doorbells for IPIs and MSIs */ writel(doorbell_mask_reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); - if (is_ipi_available() && (doorbell_mask_reg & IPI_DOORBELL_MASK)) + + if (is_ipi_available()) { + src0 = doorbell_mask_reg & IPI_DOORBELL_MASK; + src1 = doorbell_mask_reg & PCI_MSI_DOORBELL_MASK; + } else { + src0 = doorbell_mask_reg & PCI_MSI_FULL_DOORBELL_SRC0_MASK; + src1 = doorbell_mask_reg & PCI_MSI_FULL_DOORBELL_SRC1_MASK; + } + + if (src0) writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); - if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK) + if (src1) writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); if (is_ipi_available()) From patchwork Fri Jun 21 09:38:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13707179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA4FDC27C4F for ; Fri, 21 Jun 2024 09:38:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id B31CCC32781; Fri, 21 Jun 2024 09:38:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0E53EC2BBFC; Fri, 21 Jun 2024 09:38:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718962733; bh=ebsxRfG7w+7jqsb7KNkQhLDZDTRew3CMFRyjawbrcIU=; h=From:List-Id:To:Cc:Subject:Date:In-Reply-To:References:From; b=mzw4NvpH5VYO0Arp61CObhIZ6F1k0b/RYgwPvWh4MfI6ZwfvoE98zutQMX1k3mbFb 9i+HDwtrPdc5IaWJhfFGx+COdVC41mZevXz+ZO3IMLxkRYYZyVqiCRiJfMqL9w5U48 +FL7g0gBmkJuxeRDtjStmfQtCGR6y9e5iB3frm3GdgCH8+zNUhYaPtAokck7dQB8iA 4uzBqQrUUTpdNbA6VQh/VKCs5IzlG0K/Drd9nEms2v1NmxSzeKJKhbfphSaSRWO3TC zBh+vLO3BN1ZtCG2eWlJg3Q6t6rmXcOQ7nFAFKW9bTY3mhLY7XDuZL0kpjGRTPrQLW afOSd9GlXLg2w== From: =?utf-8?q?Marek_Beh=C3=BAn?= List-Id: To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , Arnd Bergmann , soc@kernel.org, linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v3 5/5] irqchip/armada-370-xp: Use atomic_io_modify() instead of another spinlock Date: Fri, 21 Jun 2024 11:38:32 +0200 Message-ID: <20240621093832.23319-6-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240621093832.23319-1-kabel@kernel.org> References: <20240621093832.23319-1-kabel@kernel.org> MIME-Version: 1.0 Use the dedicated atomic_io_modify() instead of hardcoded spin_lock() + readl() + writel() + spin_unlock() sequence. This allows us to drop the irq_controller_lock spinlock from the driver. Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn --- drivers/irqchip/irq-armada-370-xp.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index ada257aeba78..dce2b80bf439 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -512,24 +512,18 @@ static __init void armada_xp_ipi_init(struct device_node *node) set_smp_ipi_range(base_ipi, IPI_DOORBELL_END); } -static DEFINE_RAW_SPINLOCK(irq_controller_lock); - static int armada_xp_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force) { irq_hw_number_t hwirq = irqd_to_hwirq(d); - unsigned long reg, mask; int cpu; /* Select a single core from the affinity mask which is online */ cpu = cpumask_any_and(mask_val, cpu_online_mask); - mask = 1UL << cpu_logical_map(cpu); - raw_spin_lock(&irq_controller_lock); - reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); - reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask; - writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); - raw_spin_unlock(&irq_controller_lock); + atomic_io_modify(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq), + ARMADA_370_XP_INT_SOURCE_CPU_MASK, + BIT(cpu_logical_map(cpu))); irq_data_update_effective_affinity(d, cpumask_of(cpu));