From patchwork Fri Jun 21 16:39:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan Brattlof X-Patchwork-Id: 13707831 X-Patchwork-Delegate: viresh.linux@gmail.com Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD37EDDC4; Fri, 21 Jun 2024 16:39:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718987995; cv=none; b=Zsx+XN539MAPoWIzaSXqAXog5/cEcaSneawYgkJniarGPMefNLCleBHiOtl98mEUGlY91H3mrCgS9lT+AW9CCfV164dNGS35zgtf3R+OW48YgH0hDqNm5BYzNE8HQeAUHeQt/v54xqckKQWVCbbq92fSPc1t+NVHziiUXb9fk3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718987995; c=relaxed/simple; bh=aa/UAapxLYnd05XCY2z3WEmwO81o6wpHMQ8kV6F0g0I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=CnE8UgawjOgv7oAmTVPz/maf6rJlb58so5Aq1USfl7ACL0RH9s24hwC8izPjZ3iMVi3QeQgv6DyVLkOMGlb94opwGkqEWhuOTt9ig3WvD0wiVwIsZ2cq6XWuzWbweNcb55J+TkQBNnxmfVSQ/n+kK0PryJfsfVUW8odrGKndTjI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=xXqMOJbQ; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xXqMOJbQ" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45LGdkmQ051111; Fri, 21 Jun 2024 11:39:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718987986; bh=Nbx1zYtIRV0RSr575R1x17x1xodoPxpczYOw9GvbXdY=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=xXqMOJbQJClgv/d1+xH7wJtUFANyVqkZLr4j39TBGQgDKefWjoMYblFPMobY7HLET RqyDnNtoUnl4nTo9UCn5RBke4EuF3G/zNOX035twyxZW1fuySGiPif4h3o4/N1+Qb5 /lY05TGlQY6jpzeKB97Ife0KxsI6+I7utdT5k5jE= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45LGdkap085566 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 21 Jun 2024 11:39:46 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 21 Jun 2024 11:39:46 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jun 2024 11:39:46 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45LGdkvI080074; Fri, 21 Jun 2024 11:39:46 -0500 From: Bryan Brattlof Date: Fri, 21 Jun 2024 11:39:37 -0500 Subject: [PATCH v3 1/5] cpufreq: ti: update OPP table for AM62Ax SoCs Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240621-ti-opp-updates-v3-1-d857be6dac8b@ti.com> References: <20240621-ti-opp-updates-v3-0-d857be6dac8b@ti.com> In-Reply-To: <20240621-ti-opp-updates-v3-0-d857be6dac8b@ti.com> To: "Rafael J. Wysocki" , Viresh Kumar , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo CC: Vibhore Vardhan , , , , , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3367; i=bb@ti.com; h=from:subject:message-id; bh=aa/UAapxLYnd05XCY2z3WEmwO81o6wpHMQ8kV6F0g0I=; b=owNCWmg5MUFZJlNZ9e+uwwAAZn///n99sz/8P2+td14f/+v3Hv96++bzr+9//J25ijr2//wwA Rs2g7UGQGgAAAAAA0aaAAepoAAAAGgaaDQyABo0DQAADR6jIeKaeGp6oc0hiBpiZNNBkaGjI0G1 ABpoNNDQBpk0yDQZAADTRpkyAMjQGEBkaBk00DRoY7UP1NJkYQHqD1BhBkaBoMjIDQ00ANNBkDI AAANAAaZADIDIGQyGmgDRgAdI+kHh3gCL0SBNmoYPlwqCePNVt8TaCPoyFFZBEUtK3iEYk07LWg UYbX5KF7SanEYIWJ8GMWqM3qbBHyaHcAtfJSjGSyrGNgcG2s7mO4EdezwyVAW0VrciHt+r5OM/G p453nwjvrnpPJuk/+sVZjj7/HhYSNOwRdJpZffjjkWmI9ACqT5w61TiIFuzpLUXuPt6qbCdCNab VnObohPlSpRr4q6/gDD3FYA1XylrJcr8Wdiaj8sWsEn9XscZTMX1a3FPCcAcmDEl+tnKm/zbZc3 O49DiL3mRTgSYoM8Ugv/x1+uSTirm2Ws/VU1+yoVOQv8C/obAGRkbRnfyO/Wif3hIT+6eYfJ0Tp ZwpkoLQsQXDphJViuos51JbGImpYlHmA12bjPWSd8anjHsAJAzABzFCgxgnNiECU8EQLlQgClpB d4P+LuSKcKEh699dhg= X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 As the AM62Ax SoC family matures more speed grades are being defined. These new grades unfortunately no longer align with the AM62x SoC family. Define a new table with new OPP speed grade limits for the AM62Ax Reviewed-by: Dhruva Gole Signed-off-by: Bryan Brattlof --- drivers/cpufreq/ti-cpufreq.c | 59 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index 714ed53753fa5..51cac31f776f5 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -47,6 +47,28 @@ #define AM625_SUPPORT_S_MPU_OPP BIT(1) #define AM625_SUPPORT_T_MPU_OPP BIT(2) +enum { + AM62A7_EFUSE_M_MPU_OPP = 13, + AM62A7_EFUSE_N_MPU_OPP, + AM62A7_EFUSE_O_MPU_OPP, + AM62A7_EFUSE_P_MPU_OPP, + AM62A7_EFUSE_Q_MPU_OPP, + AM62A7_EFUSE_R_MPU_OPP, + AM62A7_EFUSE_S_MPU_OPP, + /* + * The V, U, and T speed grade numbering is out of order + * to align with the AM625 more uniformly. I promise I know + * my ABCs ;) + */ + AM62A7_EFUSE_V_MPU_OPP, + AM62A7_EFUSE_U_MPU_OPP, + AM62A7_EFUSE_T_MPU_OPP, +}; + +#define AM62A7_SUPPORT_N_MPU_OPP BIT(0) +#define AM62A7_SUPPORT_R_MPU_OPP BIT(1) +#define AM62A7_SUPPORT_V_MPU_OPP BIT(2) + #define VERSION_COUNT 2 struct ti_cpufreq_data; @@ -112,6 +134,32 @@ static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data, return BIT(efuse); } +static unsigned long am62a7_efuse_xlate(struct ti_cpufreq_data *opp_data, + unsigned long efuse) +{ + unsigned long calculated_efuse = AM62A7_SUPPORT_N_MPU_OPP; + + switch (efuse) { + case AM62A7_EFUSE_V_MPU_OPP: + case AM62A7_EFUSE_U_MPU_OPP: + case AM62A7_EFUSE_T_MPU_OPP: + case AM62A7_EFUSE_S_MPU_OPP: + calculated_efuse |= AM62A7_SUPPORT_V_MPU_OPP; + fallthrough; + case AM62A7_EFUSE_R_MPU_OPP: + case AM62A7_EFUSE_Q_MPU_OPP: + case AM62A7_EFUSE_P_MPU_OPP: + case AM62A7_EFUSE_O_MPU_OPP: + calculated_efuse |= AM62A7_SUPPORT_R_MPU_OPP; + fallthrough; + case AM62A7_EFUSE_N_MPU_OPP: + case AM62A7_EFUSE_M_MPU_OPP: + calculated_efuse |= AM62A7_SUPPORT_N_MPU_OPP; + } + + return calculated_efuse; +} + static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data, unsigned long efuse) { @@ -234,6 +282,15 @@ static struct ti_cpufreq_soc_data am625_soc_data = { .multi_regulator = false, }; +static struct ti_cpufreq_soc_data am62a7_soc_data = { + .efuse_xlate = am62a7_efuse_xlate, + .efuse_offset = 0x0, + .efuse_mask = 0x07c0, + .efuse_shift = 0x6, + .rev_offset = 0x0014, + .multi_regulator = false, +}; + /** * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC * @opp_data: pointer to ti_cpufreq_data context @@ -337,7 +394,7 @@ static const struct of_device_id ti_cpufreq_of_match[] = { { .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, }, { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, }, { .compatible = "ti,am625", .data = &am625_soc_data, }, - { .compatible = "ti,am62a7", .data = &am625_soc_data, }, + { .compatible = "ti,am62a7", .data = &am62a7_soc_data, }, { .compatible = "ti,am62p5", .data = &am625_soc_data, }, /* legacy */ { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, }, From patchwork Fri Jun 21 16:39:38 2024 Content-Type: text/plain; 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Fri, 21 Jun 2024 11:39:46 -0500 From: Bryan Brattlof Date: Fri, 21 Jun 2024 11:39:38 -0500 Subject: [PATCH v3 2/5] cpufreq: ti: update OPP table for AM62Px SoCs Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240621-ti-opp-updates-v3-2-d857be6dac8b@ti.com> References: <20240621-ti-opp-updates-v3-0-d857be6dac8b@ti.com> In-Reply-To: <20240621-ti-opp-updates-v3-0-d857be6dac8b@ti.com> To: "Rafael J. Wysocki" , Viresh Kumar , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo CC: Vibhore Vardhan , , , , , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2681; i=bb@ti.com; h=from:subject:message-id; bh=OnjgNJDFxiPKZgZGyPgGQPGW1SV4Zx/0dKqTvtZJ1N0=; b=owNCWmg5MUFZJlNZoUljNAAAaf////7ffrt3/n7+9tJvXzSOr9t39b5//cs3fL/7yfbZ/++wA Rs2gxQAA0AyPUDQAAMgaAZABoABoAAGQDQ0B6gA2oNMQAGjQPU009EbTJqIAaaDQDQyZAaAAAxq ZNND1AGgGTTQGQZDCG1D0IDQ0aBkMgaA0eoDQGgBgyg000aDEaADTJiaNA00MhoAA0wgGQDJhBo AyAA0MTQAaBpo0GajRoyZMgAQJzh5Sv10QZIFFR1dBizrHgGlWSJ/JQGj0FiiZG1OC04yJAGFO5 4yg7PVk6cFz5DoGuqyi2ep/UtqoAhw/jpLtQWuDNVcsPHlzzGJYLKzD2QhAhSXem8b3qFyQloir MFGBZAPeo8CZvshdRcwnPC/zt88nwCYA+rFCIEyjDRoPuDXEsJuyRrOM2JZc3rxpOKWGSlH0JaN vwtTfUG0kCE2FwG9QmOLDh9UpJHx85Hu6S4ZOn4SAvCm8aIrmAqnxws+ncwD5ELNlgOyXLVRn8z y5LDvkg2ZHAH/aPpgGOI9uP2Wsr0E7dvIFCtVYawi9dFf7JDQ0y5jzXOtRsPNctEFvLEU9puBK9 EWNAM/uSaFDMdoMJPoPoG0DTMNq+QRQ0cwLvp4abDBMnV6dKUyQx6v7sByGJhi9kqSQisJkICiw IVIUZ/xdyRThQkKFJYzQA== X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 More speed grades for the AM62Px SoC family have been defined which unfortunately no longer align with the AM62x table. So create a new table with these new speed grades defined for the AM62Px Reviewed-by: Dhruva Gole Signed-off-by: Bryan Brattlof --- drivers/cpufreq/ti-cpufreq.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index 51cac31f776f5..49ee25cc4a105 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -69,6 +69,13 @@ enum { #define AM62A7_SUPPORT_R_MPU_OPP BIT(1) #define AM62A7_SUPPORT_V_MPU_OPP BIT(2) +#define AM62P5_EFUSE_O_MPU_OPP 15 +#define AM62P5_EFUSE_S_MPU_OPP 19 +#define AM62P5_EFUSE_U_MPU_OPP 21 + +#define AM62P5_SUPPORT_O_MPU_OPP BIT(0) +#define AM62P5_SUPPORT_U_MPU_OPP BIT(2) + #define VERSION_COUNT 2 struct ti_cpufreq_data; @@ -134,6 +141,23 @@ static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data, return BIT(efuse); } +static unsigned long am62p5_efuse_xlate(struct ti_cpufreq_data *opp_data, + unsigned long efuse) +{ + unsigned long calculated_efuse = AM62P5_SUPPORT_O_MPU_OPP; + + switch (efuse) { + case AM62P5_EFUSE_U_MPU_OPP: + case AM62P5_EFUSE_S_MPU_OPP: + calculated_efuse |= AM62P5_SUPPORT_U_MPU_OPP; + fallthrough; + case AM62P5_EFUSE_O_MPU_OPP: + calculated_efuse |= AM62P5_SUPPORT_O_MPU_OPP; + } + + return calculated_efuse; +} + static unsigned long am62a7_efuse_xlate(struct ti_cpufreq_data *opp_data, unsigned long efuse) { @@ -291,6 +315,15 @@ static struct ti_cpufreq_soc_data am62a7_soc_data = { .multi_regulator = false, }; +static struct ti_cpufreq_soc_data am62p5_soc_data = { + .efuse_xlate = am62p5_efuse_xlate, + .efuse_offset = 0x0, + .efuse_mask = 0x07c0, + .efuse_shift = 0x6, + .rev_offset = 0x0014, + .multi_regulator = false, +}; + /** * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC * @opp_data: pointer to ti_cpufreq_data context @@ -395,7 +428,7 @@ static const struct of_device_id ti_cpufreq_of_match[] = { { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, }, { .compatible = "ti,am625", .data = &am625_soc_data, }, { .compatible = "ti,am62a7", .data = &am62a7_soc_data, }, - { .compatible = "ti,am62p5", .data = &am625_soc_data, }, + { .compatible = "ti,am62p5", .data = &am62p5_soc_data, }, /* legacy */ { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, }, { .compatible = "ti,omap3630", .data = &omap36xx_soc_data, }, From patchwork Fri Jun 21 16:39:39 2024 Content-Type: text/plain; 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Fri, 21 Jun 2024 11:39:46 -0500 From: Bryan Brattlof Date: Fri, 21 Jun 2024 11:39:39 -0500 Subject: [PATCH v3 3/5] dt-bindings: mfd: syscon: add TI's opp table compatible Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240621-ti-opp-updates-v3-3-d857be6dac8b@ti.com> References: <20240621-ti-opp-updates-v3-0-d857be6dac8b@ti.com> In-Reply-To: <20240621-ti-opp-updates-v3-0-d857be6dac8b@ti.com> To: "Rafael J. Wysocki" , Viresh Kumar , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo CC: Vibhore Vardhan , , , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1057; i=bb@ti.com; h=from:subject:message-id; bh=ta4Z9ycYD1Ka/6WLR31T6TPcPYgv4UQQ32/jEd+kzMk=; b=owNCWmg5MUFZJlNZCy37FQAAX////7978vt5/771mz/vOQjS403q/d+1znPd49vf+93t7+ewA RswjEgANANAAA00AAGjRpoGgDQ0DQDQ0NNqaAD1AGgDI0ZMj1PUAPSZkmaZIcmhkDJkDQGj9UaA BpoGgyaMjQ0AMRoBoB6gA09R6hkaabUyZABoANGBGBAOTT0I0xDQYTTQ0MRpoMCZGTQNAyNNADT JoMNRoMgwgNDJoMgA0ADRkAAAAbgpQ0ELgI2MjiprQKiMBijFGZAaESmdLW4gqm1QgyP3VQ0c0O B1d/sC3x+DjHft8OTTEkZSNFzurCuOi35RWIAKOQUiIZQomgj5FAn7GGNS2iInSBalUhYhKk4ZF KptG7nSyn5bxV4Lzsu/jqcRrz2s/D6DFeTWGd/JenwQGlrBK4UBZKoPJz06KsN6zbstNp7WtEwC sA6u7fEJ65W0MuP4apfxoTIT8f0PAskneaHlc/TwIwzJQhvzlgxL6hbZYPBCB0iL0WTA495eqpH 8vhTQKk0B5XEdg8yCJaJOKKFcJEYSfgL2yko0KH8aq6PWhqJn2ZgW/eggNMUowRPP4h8jXGT5bV 4MBlbJZkE8jIswW7H7UsmrZvcjuAXkU4m/iWHCIlcFN2eMSIWUdo15bnozjcgECw83PoylI9/Rg Tf4u5IpwoSAWW/YqA== X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The JTAG_USER_ID_USERCODE efuse address, which is located inside the WKUP_CTRL_MMR0 range holds information to identify the speed grades of various components on TI's K3 SoCs. Add a compatible to allow the cpufreq driver to obtain the data to limit the maximum frequency for the CPUs under Linux control. Signed-off-by: Bryan Brattlof Acked-by: Conor Dooley --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 7ed12a938baa3..d1ed7d33d163b 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -87,6 +87,7 @@ properties: - rockchip,rk3588-qos - rockchip,rv1126-qos - starfive,jh7100-sysmain + - ti,am62-opp-efuse-table - ti,am62-usb-phy-ctrl - ti,am62p-cpsw-mac-efuse - ti,am654-dss-oldi-io-ctrl From patchwork Fri Jun 21 16:39:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan Brattlof X-Patchwork-Id: 13707836 X-Patchwork-Delegate: viresh.linux@gmail.com Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBA1F16A924; Fri, 21 Jun 2024 16:39:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718988000; cv=none; b=fd1B2vs4lsOwK8PfCP+O34Fzb4cavNG2ZSjB+4qpOS99lPL1IEYou0O20newt0/syEqgQu+9iptv/NkdIymvL6+wEKHUG8F/AD4zTf9VSo6IvKjYxDwO14VovF1ig03OEFsy17/EYDg0D7tCVcFMTMpAlo8GAUU0RKcATZp4Apc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718988000; c=relaxed/simple; bh=bsU/uSufwYkHHioRdRIW2VKG45iABEGGxk+o7JmN7xk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=pBp1u800BwW8PbUnmJ2YTOey6U9ZU/vlWWwtaKTk/yer4QIKzSectXKjyNw08/bvb3lHpHYmK9DIyQiajnBBiPNNQkhzQahYcqPOZKzh/etVZjk0uxy20PFeQ6SsmTJOvtHt03kEHOi0SOC82JeNem2qHYM7mu+BNaaL5xPkuuU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=DLUUr7hb; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="DLUUr7hb" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45LGdk19091076; Fri, 21 Jun 2024 11:39:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718987986; bh=41la4WrGvritz6KJ0djgZf2nYLv9pbYtJnXCQHs8xKk=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=DLUUr7hbfGFuWFyA1blV2g6hcXOXBgr9hNFi42qBYJR68vOPI6x5y79pB+9yFG5Zr vhybN/UzDn/z86IsgCWfL0b5K5G6ptrXqzozuW48Yg1r/dU31M9yloICAFysmSgRJR YqtwQaNzIt6bkFKGUtdAu9Muh43KREjCp0VEO2Ss= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45LGdkgw085574 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 21 Jun 2024 11:39:46 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 21 Jun 2024 11:39:46 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 21 Jun 2024 11:39:46 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45LGdkZK057984; Fri, 21 Jun 2024 11:39:46 -0500 From: Bryan Brattlof Date: Fri, 21 Jun 2024 11:39:40 -0500 Subject: [PATCH v3 4/5] DONOTMERGE: arm64: dts: ti: k3-am62p: add in opp tables Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240621-ti-opp-updates-v3-4-d857be6dac8b@ti.com> References: <20240621-ti-opp-updates-v3-0-d857be6dac8b@ti.com> In-Reply-To: <20240621-ti-opp-updates-v3-0-d857be6dac8b@ti.com> To: "Rafael J. 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Signed-off-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 6 ++++ arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 9 ++++++ arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 47 +++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi index c71d9624ea277..8392c8cde2cd4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi @@ -19,6 +19,11 @@ chipid: chipid@14 { bootph-all; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + usb0_phy_ctrl: syscon@4008 { compatible = "ti,am62-usb-phy-ctrl", "syscon"; reg = <0x4008 0x4>; @@ -28,6 +33,7 @@ usb1_phy_ctrl: syscon@4018 { compatible = "ti,am62-usb-phy-ctrl", "syscon"; reg = <0x4018 0x4>; }; + }; wkup_uart0: serial@2b300000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 6983ec1b57cbd..08956ac1eaead 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -128,6 +128,15 @@ led-0 { }; }; + opp-table { + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + tlv320_mclk: clk-0 { #clock-cells = <0>; compatible = "fixed-clock"; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi index 41f479dca4555..140587d02e88e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi @@ -47,6 +47,7 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 135 0>; }; @@ -62,6 +63,7 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 136 0>; }; @@ -77,6 +79,7 @@ cpu2: cpu@2 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 137 0>; }; @@ -92,10 +95,54 @@ cpu3: cpu@3 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 138 0>; }; }; + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; + }; + }; + l2_0: l2-cache0 { compatible = "cache"; cache-unified; From patchwork Fri Jun 21 16:39:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan Brattlof X-Patchwork-Id: 13707835 X-Patchwork-Delegate: viresh.linux@gmail.com Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 974DB1684AD; Fri, 21 Jun 2024 16:39:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718988000; cv=none; b=O2m0FGSQMNei9CUQ+5UAZwX2NjjL+TVN3H6I1G7d6nxGksend/a5qZbffRee9ED9egX6TPOCvNZNXwawdEIRrj0go+GNd1y9eW+NQb2K80/NfDOBa/eCQOOT8VCyj1pxoPjn3frZi8+nYTpmDPYPmHZinpbCwSgfe1NSp1e9V+4= ARC-Message-Signature: i=1; a=rsa-sha256; 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Fri, 21 Jun 2024 11:39:46 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45LGdkLB057989; Fri, 21 Jun 2024 11:39:46 -0500 From: Bryan Brattlof Date: Fri, 21 Jun 2024 11:39:41 -0500 Subject: [PATCH v3 5/5] DONOTMERGE: arm64: dts: ti: k3-am62a: add in opp table Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240621-ti-opp-updates-v3-5-d857be6dac8b@ti.com> References: <20240621-ti-opp-updates-v3-0-d857be6dac8b@ti.com> In-Reply-To: <20240621-ti-opp-updates-v3-0-d857be6dac8b@ti.com> To: "Rafael J. Wysocki" , Viresh Kumar , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo CC: Vibhore Vardhan , , , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3806; i=bb@ti.com; h=from:subject:message-id; bh=hWo1gVxlWo8njHZbS2+ISUJ4MaU/Z08cT/W2pZCsCxE=; b=owNCWmg5MUFZJlNZePdFTQAAZn////9v/+fr/cz+zxG/l6san/7qz/X17+vLU0+89xNp//ewA Rs21kABiMgDTQ0aAAaA0wmmmjRpoDCaADQyAAyYQaZDCADQYjCAPUYjIyb1EHqaMIA0GhoAANDR owhoDQaGhoAA0aGmgyGho09IA9ENNBpoeiNHqYyIGQaNDNSPUMnqNGg0NPSMgHqDTQaaBo0ABoA DQAaAAAADQADQaeoNAaeoeoD1PU9TNQMMcTgTLHM7eN6CfPu7Dj3lCeHPLTtFdDxro+OwRa/5uy O0LQOZUMKp4WYy6t/fUZ98garnzMFFSG8Xes20ot2UoZ5oQDEXPVA8zjM6dGSVjiuA+DO9X4ZnE NkBUcl24TP0ACmUZXKu4M5Gd+hkrZXm0ut3BAOjMcsuhXbFZVxq3mQ9bEZz3lSa1997fHX5nQ0U B0+UK8+xQA787wRoOxgmsLz44DXTuv/F/7hYLJrRu+RbgMFPsnRZPMesSESUsdJZ4DE0haQjSki CazNMvijCgstlyslLaMwBZEeYiEI4rljzW+BeW8w9VebXLOWthRCiZDR0KEC3DuAnmmiEX+ECvV N+ODLE3BYkP3QLSQamAaye2ClXNLdigFMfnI+MBWUKTKJEYZf20tq4soonZ/v1DH4ppvEBYoiwA Upwj04DigC7kinChIPHuipo X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To help reduce power consumption, reduce the frequency of the CPU cores when they sit idle by specifying their supported OPP entries. Signed-off-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 5 +++ arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 9 +++++ arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 51 +++++++++++++++++++++++++++++ 3 files changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index 98043e9aa316b..bf16b29c3953b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -13,6 +13,11 @@ wkup_conf: syscon@43000000 { #size-cells = <1>; ranges = <0x00 0x00 0x43000000 0x20000>; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + chipid: chipid@14 { compatible = "ti,am654-chipid"; reg = <0x14 0x4>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index f241637a5642a..852a066585d6d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -59,6 +59,15 @@ wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { }; }; + opp-table { + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + vmain_pd: regulator-0 { /* TPS25750 PD CONTROLLER OUTPUT */ compatible = "regulator-fixed"; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi index f86a23404e6dd..6c99221beb6bd 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi @@ -48,6 +48,8 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 135 0>; }; cpu1: cpu@1 { @@ -62,6 +64,8 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 136 0>; }; cpu2: cpu@2 { @@ -76,6 +80,8 @@ cpu2: cpu@2 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 137 0>; }; cpu3: cpu@3 { @@ -90,6 +96,51 @@ cpu3: cpu@3 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 138 0>; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; }; };