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([178.197.219.137]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4248179d3basm105465515e9.4.2024.06.23.05.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Jun 2024 05:00:28 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 1/3] dt-bindings: display/msm/gpu: constrain clocks in top-level Date: Sun, 23 Jun 2024 14:00:24 +0200 Message-ID: <20240623120026.44198-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 We expect each schema with variable number of clocks, to have the widest constrains in top-level "properties:". This is more readable and also makes binding stricter, if there is no "if:then:" block for given variant. Signed-off-by: Krzysztof Kozlowski Acked-by: Conor Dooley --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 40b5c6bd11f8..253e68d92779 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -32,9 +32,13 @@ properties: - pattern: '^amd,imageon-200\.[0-1]$' - const: amd,imageon - clocks: true + clocks: + minItems: 2 + maxItems: 7 - clock-names: true + clock-names: + minItems: 2 + maxItems: 7 reg: minItems: 1 From patchwork Sun Jun 23 12:00:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13708582 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5E9A18133D for ; Sun, 23 Jun 2024 12:00:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719144035; cv=none; b=XKbmvGUD8Qulw9WqglN4age6t5cCefzBzGY59+bn1Xl8A+EATV/PGm1KBDUHix/HD9cYMdMVjwL+0kxqUsXLPTPSmrfm1paGxn8AOQ/pNvTfd+S1I/+UMuRLjtsli0e9SkN5mRIbSxWy8XZ/tn7HV4Dfw3NEaJlJvoqigkxc7e8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719144035; c=relaxed/simple; bh=w7QmicMOY3gkCg20Sf6J+bR20DHpDJ/1/bdy0XRaFQE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Nno1TI9oXqGk4BNxh92vkxcvl9hau6DHA9gv2pc04rF2OCP9XtcQOkb11H5DVI1qb1sYiKjBHrxSdQs2f6U1e2HpjOorQGRIELGkqM6GU0QYIUHCtgO9busZ2xE8AYByliNuogBp/BB4IuTdfqh1428jNKr7WuyGXlAdkIJm454= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=necivQJv; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="necivQJv" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-4217990f997so25304505e9.2 for ; Sun, 23 Jun 2024 05:00:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719144031; x=1719748831; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D5pRySu+ARf8jWv+YeotUn57i8P3KF+qPMZ7wIjslP8=; b=necivQJvFommC63knwOs+2OKBfec0oP7Fm6NH/8S0fbaBl8cxNpGekpZZuKxTlBgTb 0iJ4H4HsOdPVmLINmqpMzTiV4W0PFVBFcXAKBGQ1mGHffRhR+hRHY6TZjbL0YwGm+Rn9 dF4rjHCEqlgMDCooytESL6NYl5M/W1Ipkq4WMXJoO4H/+CdyKbKtf3Onm8DsZSPV7tLh 8bTclQ40SbE6WyKIPf9kOPfDjqPZK+lP+o/fJ1fNILNtyKCYrZp0JjV0Kt0iyTkWAfqa ObtHgTwsL0ztvpZnD4SjCglOjPX7rqQdY9UnwKy4/P7SiXgYABeeq67Lw/JCdlZ5fSYs G5rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719144031; x=1719748831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D5pRySu+ARf8jWv+YeotUn57i8P3KF+qPMZ7wIjslP8=; b=XIYrUgGNuDF0DmvbHywTmbY7lHf3j6n/wHl//j573cZGJ9IfCEzDH/k8yNnwz0vCVU +wODn62qg03qDxXYVqqMLlrAjEIaQJ/E2Q4/b4XkOlLaooj2MUVSvBd0D5VWfhOadp6y tQg7FdDfJ1Y4/VP86WwLdV48VLY9ky/Jhw+q7jyK0NrG0ty1mk3gItijhkkG6cG+Hl60 aY2oAROhOy+25wMIuMKZ2n9vceu9bEMiDlFmBsNUKJNl8e+eYA6TX1+fAuX0qevBPdUd gVVt/H1PqF6YLmgG+NWjyE8R5OEK9K3T46B505L6pnLEa4DkELxv/sESJ5aKtaJbnwf+ HfmA== X-Forwarded-Encrypted: i=1; AJvYcCVfiqxTCdCFDEZph98jgg2WfOrd5VMQD81DEfMcPDR1OViYit730Vp0XytKRbNEq9c1Xa+UoKc95SVRvQqA7VO8khMyIRrIr/Fo1kvFbw== X-Gm-Message-State: AOJu0YyB8ZgOBm6fwqnuN5DcmtJZ1bIV6U588A2kbGEtUSyvapD8xreE R/WsYU33ij7fC1XmX7tEfBWKofcHgoctTv4io6MC3FnpRN8WyJ5gbaoDqOo+5vs= X-Google-Smtp-Source: AGHT+IEXP7AJ8wGYP4P3O8ghUgKEsx/NMem41iq5obFqMs7hv1GsRgZtKTmlmuq84/7vHtVQVzL0xQ== X-Received: by 2002:a7b:c4d3:0:b0:421:7c1e:5d70 with SMTP id 5b1f17b1804b1-42489e3ab62mr20397615e9.16.1719144031293; Sun, 23 Jun 2024 05:00:31 -0700 (PDT) Received: from krzk-bin.. ([178.197.219.137]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4248179d3basm105465515e9.4.2024.06.23.05.00.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Jun 2024 05:00:30 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 2/3] dt-bindings: display/msm/gpu: define reg-names in top-level Date: Sun, 23 Jun 2024 14:00:25 +0200 Message-ID: <20240623120026.44198-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240623120026.44198-1-krzysztof.kozlowski@linaro.org> References: <20240623120026.44198-1-krzysztof.kozlowski@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 All devices should (and actually do) have same order of entries, if possible. That's the case for reg/reg-names, so define the reg-names in top-level to enforce that. Signed-off-by: Krzysztof Kozlowski Acked-by: Conor Dooley --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 253e68d92779..baea1946c65d 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -46,7 +46,10 @@ properties: reg-names: minItems: 1 - maxItems: 3 + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc interrupts: maxItems: 1 From patchwork Sun Jun 23 12:00:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13708583 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F669181CEA for ; Sun, 23 Jun 2024 12:00:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719144037; cv=none; b=NxWfXtp4OWK9w6u0VtlUBUKSTbDW2ZhEO6HYA7szBVcc40wq6KlEiZqIXMZI0Yn39yQRgCWrTjjMjIkpLv+kbf3IH+EnRtE2EA6vG1RZYCmfi13B3hZQGckCdHT4eIeir4ewmOF7hEtcyZHJYGWJyRbV11CYOQMsyqP4M4dSAeg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719144037; c=relaxed/simple; bh=ZkimSwvr82NPcbaA0foj0eXzI4jvTaBVQ88EJATB1tM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c6HEycXnRKe0PcOuVaqhIdTCXcp0Sk/v7+lxLlHk9/ur4wh1fePSzW4+7fbBajI7i+/7+H/vTdaHYrHGMHy7SxJxOWWy3RmuukHlm9OLzgdYnD9kcRvZ7l1EKMqDovUfZKA9tASrjyJDxv0hjEfeUD5Qpl1Uz1m5XeCSfu59+uY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=wqqMvFoK; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="wqqMvFoK" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4217926991fso30554525e9.3 for ; Sun, 23 Jun 2024 05:00:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719144033; x=1719748833; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ecK+toW3Ns4ZNrqgQybbNewCzjgaGGXdUaWN+FWF27c=; b=wqqMvFoK8jJWfr9t0LsWpsLYdW3UQOXfjzw9jiehORzP6bvgLq9PtCaOtmFnsIcPfs q3zb1gaKvdz+/uNWWBdHdijtxJaP7eDDb+xsSwSKWaYMQcnlskRkxoUyNrsrFIYUFznP clGuSs4UtUo6OCnb371HjXFhVLh7sRwo/ZTv7s90e5E8WhnjqUCJNo3UKAeAmB6oPyVk iPO1cFCZbFtZQRBOlknTdNZbpXKJCtPWGeWXvpcMWQoseXzVxnfPob0ZuFfAXiRDMcfu kAMh5PLhtuosEjw8Ve7klAS3rXSITv+AnSspJjzP83kdnS3KdnRhqhY74i471uWSuPhp /0yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719144033; x=1719748833; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ecK+toW3Ns4ZNrqgQybbNewCzjgaGGXdUaWN+FWF27c=; b=RUq2ODhqPvILYf+/jfVYzuzizFkMiMLP1Zclq+5X+evYqOf+iqGJ7v1mMw6zwImoB1 PnHATvXpYua9hSpjUHDzqH4WN0wi4SOmxGH2uOtr7KNk4jtDV24zYpDwZtXEq4rlvogK hvWx6S3mOuz/UMAtcWs7Q+/kXewFn2SDsRQJ2leG2loXK+zsDGffEIJwggstZ3JisvHx KEDF4DLGXl2dWS2xkwFEvtMA7veK/FgGcRO6roZfEdJkxxLr9I0pHkhfIk2Wok8KCsRA YGJINlk8oBwZyAMxs0dnH6XbPfNUiiP1KQETFo9k+xlA/PXqdqdthC3QbRs6uZJhe3b6 VAWg== X-Forwarded-Encrypted: i=1; AJvYcCVyq5QTFwyCIifWA6bwvdhl2LqiDOItQrw3IIfaZ33VvVkse5Oz3vRxA7MjTACtgKccMU/AvFzsxr3LkjrAEppQj09NqKzUawAFUatK2A== X-Gm-Message-State: AOJu0YyRqsL+wuxJEuUfqMFZTtjBB5hQFfvUP+rsfax6mYEjc/X7iJLh T7ZYv0Z+31qGSEHE3fKizfxqzfoQgDQ5XRz/vdzAQqb/ol2Tv/UNFm1Dti+4YGQ= X-Google-Smtp-Source: AGHT+IGH65kKS7M6vcnw+GFLjPcYiLfNI3yhUCA7KwnzudEhnrCZRo0tzHlu9MxebLYKwwKlOaegOQ== X-Received: by 2002:a05:600c:3c93:b0:424:9024:d468 with SMTP id 5b1f17b1804b1-4249024d4e1mr4347895e9.17.1719144032825; Sun, 23 Jun 2024 05:00:32 -0700 (PDT) Received: from krzk-bin.. ([178.197.219.137]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4248179d3basm105465515e9.4.2024.06.23.05.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Jun 2024 05:00:32 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 3/3] dt-bindings: display/msm/gpu: constrain reg/reg-names per variant Date: Sun, 23 Jun 2024 14:00:26 +0200 Message-ID: <20240623120026.44198-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240623120026.44198-1-krzysztof.kozlowski@linaro.org> References: <20240623120026.44198-1-krzysztof.kozlowski@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 MMIO address space is known per each variant of Adreno GPU, so we can constrain the reg/reg-names entries for each variant. There is no DTS for A619, so that part is not accurate but could be corrected later. Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/msm/gpu.yaml | 87 +++++++++++++++++-- 1 file changed, 79 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index baea1946c65d..e83f13123fc9 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -130,6 +130,22 @@ required: additionalProperties: false allOf: + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$' + then: + properties: + reg: + minItems: 3 + + reg-names: + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc + - if: properties: compatible: @@ -164,6 +180,13 @@ allOf: minItems: 2 maxItems: 7 + reg: + maxItems: 1 + + reg-names: + items: + - const: kgsl_3d0_reg_memory + required: - clocks - clock-names @@ -196,11 +219,12 @@ allOf: - const: xo description: GPUCC clocksource clock + reg: + maxItems: 1 + reg-names: - minItems: 1 items: - const: kgsl_3d0_reg_memory - - const: cx_dbgc required: - clocks @@ -217,12 +241,59 @@ allOf: clocks: false clock-names: false - reg-names: - minItems: 1 - items: - - const: kgsl_3d0_reg_memory - - const: cx_mem - - const: cx_dbgc + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-640.1 + - qcom,adreno-680.1 + then: + properties: + reg: + maxItems: 1 + + reg-names: + items: + - const: kgsl_3d0_reg_memory + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-619.0 + - qcom,adreno-630.2 + then: + properties: + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-618.0 + - qcom,adreno-635.0 + - qcom,adreno-690.0 + - qcom,adreno-730.1 + then: + properties: + reg: + minItems: 3 + + reg-names: + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc examples: - |