From patchwork Mon Jun 24 07:10:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13709080 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF05EC2BD05 for ; Mon, 24 Jun 2024 07:12:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=7QQp0ll7mULHxC80OBumXN8x5vwlpC7MjkT/JCmD22E=; b=sA5pPudUSR61kcAhJwm3azKW90 VYB7QdYyYddZQGpr1FwIVCvaYqL5XvOLJS29X4Ih9JIi6uKGFKaOPb5XOAiTwq8tUjeZcNRex9gQh eLCk0UkhXiuyjySO+kYe2gjKsqa8Fwze0Od6wcphbQaypOySYCpGCQRq1RqEVk4gBK/TjyhjKXoYQ ZjDHqax+ixoNTtHwAau5B2j6/qE7S+228w18gkXuQeXymaxVNecz3k0nkYBPNrDnRsdFlN11JECTe agkoJjMKCC2SIeESsMJazdRui313IQ1zFmnf0ji+MXXzzle7tZZD4a7msi3KhFPKHNqlPcNuLrl0t e855be/Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sLdsb-0000000Fpmn-1YcJ; Mon, 24 Jun 2024 07:12:45 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sLdsT-0000000FpkC-2wcV for linux-arm-kernel@lists.infradead.org; Mon, 24 Jun 2024 07:12:39 +0000 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45NEdBwo027079; Mon, 24 Jun 2024 09:12:23 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= 7QQp0ll7mULHxC80OBumXN8x5vwlpC7MjkT/JCmD22E=; b=b+eZTLPozRZezVUI +H9TGuB8K749xxqRMe/tP6YWQ7N7DlqsNKIPoAAGfWFDgJ4V6iuPqZ9UH6bvsswk 8Ud9196dE76iWQ6Ml1GYDt/bB1UlKJq2RY/x1Ao4AoqrXBN5zBnbeBzXGXjeLnsR X2kScg410kuR2yMAaoQAWNowIttyqIltBkInlAynUgsltcZDvIw+C9OyF8//dtTa j/vHPFo4f0wsbtxMQhvS53Hs3SYI7TkP+K2At9QOECk4b+oXBEz/EO0ihA9L9A2N hWQLZbE3PnxqmkLk/cUpmio8FE8FXJ/qJh8yNeTXd5G4NKV5SWGTKHjMmynbZK5B n0w3Hg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ywngd5f8q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Jun 2024 09:12:23 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 45E0540044; Mon, 24 Jun 2024 09:12:16 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id DCFED2115F0; Mon, 24 Jun 2024 09:11:03 +0200 (CEST) Received: from localhost (10.48.86.164) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 24 Jun 2024 09:11:03 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [net-next,PATCH v3 1/2] dt-bindings: net: add STM32MP25 compatible in documentation for stm32 Date: Mon, 24 Jun 2024 09:10:51 +0200 Message-ID: <20240624071052.118042-2-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240624071052.118042-1-christophe.roullier@foss.st.com> References: <20240624071052.118042-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.48.86.164] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-24_06,2024-06-21_01,2024-05-17_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240624_001238_043970_A68D3203 X-CRM114-Status: UNSURE ( 9.96 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org New STM32 SOC have 2 GMACs instances. GMAC IP version is SNPS 5.30 Signed-off-by: Christophe Roullier Reviewed-by: Conor Dooley Reviewed-by: Marek Vasut --- Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index f6e5e0626a3f..bf23838fe6e8 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -23,12 +23,17 @@ select: - st,stm32-dwmac - st,stm32mp1-dwmac - st,stm32mp13-dwmac + - st,stm32mp25-dwmac required: - compatible properties: compatible: oneOf: + - items: + - enum: + - st,stm32mp25-dwmac + - const: snps,dwmac-5.20 - items: - enum: - st,stm32mp1-dwmac @@ -121,8 +126,9 @@ allOf: compatible: contains: enum: - - st,stm32mp1-dwmac - st,stm32-dwmac + - st,stm32mp1-dwmac + - st,stm32mp25-dwmac then: properties: st,syscon: From patchwork Mon Jun 24 07:10:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13709081 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26E06C2D0D1 for ; Mon, 24 Jun 2024 07:12:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=FfInngTJboIkP5t9ZhXSngJj6R6y0Dwxri0WZ4Omhyc=; b=wj5vrT7bPXD+7C/D4c06Hmf5Hx Ue1aAJSUYyysykLbKwK47QfV7QZNmnxs67sRERw7vJPQ7sTjWimEz8wpOKPQ1kyMdklbCh+rjIoMG QQV6KySqhSuNCZf6dsR7qadFtYG7DLMiEbP8Eem43zLFJ5rIrNc7139nBp2aE1pZ9wMK2kFA7Q/7K 8EMGUo5/5fusIv82NYEmnAIbBs9fbaqYosGGPJsUmMUbY1nppEaLXDx59s8jULNggN/+ZcahvHpW2 9db23p68EeblpOjehMaALvzhG5bKmSnYakJQ+GRexYyhUPoIYgcfwOxVYG02huaZKSL/yVcLaSOUG ZBHxxlQg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sLdsZ-0000000FpmF-2tGP; Mon, 24 Jun 2024 07:12:43 +0000 Received: from mx07-00178001.pphosted.com ([185.132.182.106]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sLdsS-0000000Fpk5-3wWn for linux-arm-kernel@lists.infradead.org; Mon, 24 Jun 2024 07:12:38 +0000 Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45NKSa8b021217; Mon, 24 Jun 2024 09:12:23 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= FfInngTJboIkP5t9ZhXSngJj6R6y0Dwxri0WZ4Omhyc=; b=dVF0nzWeoOzlYjZY OsZJStVpGDNP8FeDAAki95q29qTLN4wuAYPTM49HoYutCl6EdY/gkHqFALwC7LRG EU3WsqFMEgiAn/BRbcrl1jtoa4vTByDeIAC9jPDhJp7b/4VJQxb3WbgxHXk+GAaC cV1lLpAuY3zSSWLiIWk12fHZDiV39hjV7JI7PTklcDm3ao87paq/pjjVpTFLdI71 vvVX2q5zFXWxKnFsGPtW4cEe4PmVZKSqIELDh2rcaibDJMvLFX9cWXlKZD++ifif bfOw7hjIIoQkM3Nefa1dAe+rvgsJ27XBzfjQCOg90WwxYefeBJB30OXbl8YdpVMS P01uDg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ywm1g5vrt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Jun 2024 09:12:23 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 45D564002D; Mon, 24 Jun 2024 09:12:16 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B20D52115FA; Mon, 24 Jun 2024 09:11:04 +0200 (CEST) Received: from localhost (10.48.86.164) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 24 Jun 2024 09:11:03 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [net-next,PATCH v3 2/2] net: stmmac: dwmac-stm32: stm32: add management of stm32mp25 for stm32 Date: Mon, 24 Jun 2024 09:10:52 +0200 Message-ID: <20240624071052.118042-3-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240624071052.118042-1-christophe.roullier@foss.st.com> References: <20240624071052.118042-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.48.86.164] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-24_06,2024-06-21_01,2024-05-17_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240624_001237_295978_6AA83137 X-CRM114-Status: GOOD ( 18.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add Ethernet support for STM32MP25. STM32MP25 is STM32 SOC with 2 GMACs instances. GMAC IP version is SNPS 5.3x. GMAC IP configure with 2 RX and 4 TX queue. DMA HW capability register supported RX Checksum Offload Engine supported TX Checksum insertion supported Wake-Up On Lan supported TSO supported Signed-off-by: Christophe Roullier Reviewed-by: Simon Horman Reviewed-by: Marek Vasut --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 80 ++++++++++++++++++- 1 file changed, 77 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index b2db0e26c4e4..23cf0a5b047f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -53,7 +53,18 @@ #define SYSCFG_MCU_ETH_SEL_MII 0 #define SYSCFG_MCU_ETH_SEL_RMII 1 -/* STM32MP1 register definitions +/* STM32MP2 register definitions */ +#define SYSCFG_MP2_ETH_MASK GENMASK(31, 0) + +#define SYSCFG_ETHCR_ETH_PTP_CLK_SEL BIT(2) +#define SYSCFG_ETHCR_ETH_CLK_SEL BIT(1) +#define SYSCFG_ETHCR_ETH_REF_CLK_SEL BIT(0) + +#define SYSCFG_ETHCR_ETH_SEL_MII 0 +#define SYSCFG_ETHCR_ETH_SEL_RGMII BIT(4) +#define SYSCFG_ETHCR_ETH_SEL_RMII BIT(6) + +/* STM32MPx register definitions * * Below table summarizes the clock requirement and clock sources for * supported phy interface modes. @@ -104,7 +115,7 @@ struct stm32_ops { int (*parse_data)(struct stm32_dwmac *dwmac, struct device *dev); bool clk_rx_enable_in_suspend; - bool is_mp13; + bool is_mp13, is_mp2; u32 syscfg_clr_off; }; @@ -277,8 +288,55 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat) dwmac->mode_mask, val); } +static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat) +{ + struct stm32_dwmac *dwmac = plat_dat->bsp_priv; + u32 reg = dwmac->mode_reg; + int val = 0; + + switch (plat_dat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + /* ETH_REF_CLK_SEL bit in SYSCFG register is not applicable in MII mode */ + break; + case PHY_INTERFACE_MODE_RMII: + val = SYSCFG_ETHCR_ETH_SEL_RMII; + if (dwmac->enable_eth_ck) { + /* Internal clock ETH_CLK of 50MHz from RCC is used */ + val |= SYSCFG_ETHCR_ETH_REF_CLK_SEL; + } + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + val = SYSCFG_ETHCR_ETH_SEL_RGMII; + fallthrough; + case PHY_INTERFACE_MODE_GMII: + if (dwmac->enable_eth_ck) { + /* Internal clock ETH_CLK of 125MHz from RCC is used */ + val |= SYSCFG_ETHCR_ETH_CLK_SEL; + } + break; + default: + dev_err(dwmac->dev, "Mode %s not supported", + phy_modes(plat_dat->mac_interface)); + /* Do not manage others interfaces */ + return -EINVAL; + } + + dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); + + /* Select PTP (IEEE1588) clock selection from RCC (ck_ker_ethxptp) */ + val |= SYSCFG_ETHCR_ETH_PTP_CLK_SEL; + + /* Update ETHCR (set register) */ + return regmap_update_bits(dwmac->regmap, reg, + SYSCFG_MP2_ETH_MASK, val); +} + static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) { + struct stm32_dwmac *dwmac = plat_dat->bsp_priv; int ret; ret = stm32mp1_select_ethck_external(plat_dat); @@ -289,7 +347,10 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) if (ret) return ret; - return stm32mp1_configure_pmcr(plat_dat); + if (!dwmac->ops->is_mp2) + return stm32mp1_configure_pmcr(plat_dat); + else + return stm32mp2_configure_syscfg(plat_dat); } static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) @@ -365,6 +426,9 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac, return err; } + if (dwmac->ops->is_mp2) + return 0; + dwmac->mode_mask = SYSCFG_MP1_ETH_MASK; err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask); if (err) { @@ -586,10 +650,20 @@ static struct stm32_ops stm32mp13_dwmac_data = { .clk_rx_enable_in_suspend = true }; +static struct stm32_ops stm32mp25_dwmac_data = { + .set_mode = stm32mp1_set_mode, + .suspend = stm32mp1_suspend, + .resume = stm32mp1_resume, + .parse_data = stm32mp1_parse_data, + .is_mp2 = true, + .clk_rx_enable_in_suspend = true +}; + static const struct of_device_id stm32_dwmac_match[] = { { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data}, { .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data}, { .compatible = "st,stm32mp13-dwmac", .data = &stm32mp13_dwmac_data}, + { .compatible = "st,stm32mp25-dwmac", .data = &stm32mp25_dwmac_data}, { } }; MODULE_DEVICE_TABLE(of, stm32_dwmac_match);