From patchwork Mon Jun 24 12:49:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13709437 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C896F13CFB6; Mon, 24 Jun 2024 12:50:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719233411; cv=none; b=o/4m2vM4Q65r79ZHm0Bh9YAL469aqKdCMH49m1ENrd5+fni1De1KRM3qsrNv+mlqEAxoNt0IjNtcEOROzn1HKculn4w66oM/RHUYV9tB+QPjZI7GE+M31lt/1+TBSpxiJ86rBfNPTLgh6lmazR0Kjpf0zmJG6aM0XuYPovba3IQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719233411; c=relaxed/simple; bh=kazmdC/cLGmIsaW+TEKeeGpN3GwONcFkU1ULaXVaWeg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Og9cG24p0+patwb8iYYl2xB5cotAjHKzvGyot2zUoEkgCrMXOsXs7SkMwHev4rlhx5IK0dckAKI7522JPXjYD5D8r3E9E0J7esur9YrXh4Y+1aTTnEDn/i2jhUB3Eq/NyJ3AH9qE4EZ0iLNWmtiBCY4xfa2g4Ta655z1zrUya78= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=T4neDO81; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="T4neDO81" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-4248e28de9eso9996375e9.2; Mon, 24 Jun 2024 05:50:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719233408; x=1719838208; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p0m6UNyRnajMw6xAJ7LWWvSa2adAG/lm7tOiNtbOtpw=; b=T4neDO81gXzv6Kye1vW61WMWoI6q2iwRiWcS4W9EE/brPFz4LtMqnfgGG4jSIRbUBh mdvYxHitUSjqNjURUkyEbxquqUj+nfNldvUBoJjapvcmyRqV5wy8tsgaE+YpRZ3DJsv7 0u6KxyUUrPdtN5PVawNHv2ivg/AQeDbIJeJD068OQNNVDhCIYWh6H6q/VfReEXe89I9b D/lrcMme3Eb1SksBAkJbI053MEkrrqeGX7Nk2JQywC/Zwsq8pEMKcBGbiqRSHA27lfau pTuSECIOdwLZcGYsIHn/kZq02fPUbvsCgi6pPr4cAPwPhyHPFvST500JNet03xtaalPu BNxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719233408; x=1719838208; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p0m6UNyRnajMw6xAJ7LWWvSa2adAG/lm7tOiNtbOtpw=; b=XOUszS9bJiDlPyiRBqdNipllrFBTjhLToE+EJ00EayTWJtIzoxBFJESOD7Wk2JvAyu rRrvyQKmNInmcHWhXDRbBzsyB61FwA6lbvXvs2lxop1i2DLuHgdEwEPh1MAq8jOk+nvA rC/Xe+7Y/9H1Rq2s+pbiZEKeWV9LMW98XHwPHmLi0qvO5R+h5sHZ8EEAuPAntryYK8zi ZdukwjT90ZEPEjXefozJLhO2yw+nrvQ9f4hj42HkKhcCZxEAy6ehSVpq5waENxDHGQfT VCJlif18J6qZYh6OsKlc34uiTqnd1bMSMZ/gQatMkrR5eJI63SlIJmMcp53yUKWfgeQO EqXQ== X-Forwarded-Encrypted: i=1; AJvYcCVobgvEwewsITYCyDwC0IAlKc5OdnIMLGZ3FLlVtbizqlfVEBoJkKdMEBWXBZm8MhvR+4ld2hFTO55GIBsFfLZZZ1a+yf8OgjLHJjBJmjbPPIgst+tzZAuydI3wIui8evkBCt5t+TJgO9rYlTYjxPOVMAhbDoVkBkMi3P6SmqL/hZEdkQ== X-Gm-Message-State: AOJu0YxTlDunzN0mJc0Ps6MOEwjhC4xNyZHYyNkfeMdxP5AG6hjBlzPN +Zl5g9J04eRcYSgoR7EoXJNJfZ6f8W5sMxH6poPfbYVD160249/a X-Google-Smtp-Source: AGHT+IGy5cmaBr5ntYugOtnY+Liivf8C7QSQCOSQ75qzG8qIRq2obmka5A5zHOX3y+wIec0VYl0TAg== X-Received: by 2002:a05:600c:4451:b0:422:62db:5a02 with SMTP id 5b1f17b1804b1-4248cc586ddmr37382835e9.32.1719233407669; Mon, 24 Jun 2024 05:50:07 -0700 (PDT) Received: from spiri.. ([5.14.146.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4247d208b60sm174127905e9.37.2024.06.24.05.50.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 05:50:07 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , David Lechner Subject: [PATCH v6 1/6] iio: adc: ad7192: use devm_regulator_get_enable_read_voltage Date: Mon, 24 Jun 2024 15:49:36 +0300 Message-Id: <20240624124941.113010-2-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624124941.113010-1-alisa.roman@analog.com> References: <20240624124941.113010-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: David Lechner This makes use of the new devm_regulator_get_enable_read_voltage() function to reduce boilerplate code. Error messages have changed slightly since there are now fewer places where we print an error. The rest of the logic of selecting which supply to use as the reference voltage remains the same. Also 1000 is replaced by MILLI in a few places for consistency. Signed-off-by: David Lechner Signed-off-by: Alisa-Dariana Roman --- drivers/iio/adc/ad7192.c | 103 ++++++++++++++------------------------- 1 file changed, 36 insertions(+), 67 deletions(-) diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index c7fb51a90e87..334ab90991d4 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -200,8 +200,6 @@ struct ad7192_chip_info { struct ad7192_state { const struct ad7192_chip_info *chip_info; - struct regulator *avdd; - struct regulator *vref; struct clk *mclk; u16 int_vref_mv; u32 aincom_mv; @@ -1189,18 +1187,12 @@ static const struct ad7192_chip_info ad7192_chip_info_tbl[] = { }, }; -static void ad7192_reg_disable(void *reg) -{ - regulator_disable(reg); -} - static int ad7192_probe(struct spi_device *spi) { struct device *dev = &spi->dev; struct ad7192_state *st; struct iio_dev *indio_dev; - struct regulator *aincom; - int ret; + int ret, avdd_mv; if (!spi->irq) return dev_err_probe(dev, -ENODEV, "Failed to get IRQ\n"); @@ -1218,72 +1210,49 @@ static int ad7192_probe(struct spi_device *spi) * Newer firmware should provide a zero volt fixed supply if wired to * ground. */ - aincom = devm_regulator_get_optional(dev, "aincom"); - if (IS_ERR(aincom)) { - if (PTR_ERR(aincom) != -ENODEV) - return dev_err_probe(dev, PTR_ERR(aincom), - "Failed to get AINCOM supply\n"); - - st->aincom_mv = 0; - } else { - ret = regulator_enable(aincom); - if (ret) - return dev_err_probe(dev, ret, - "Failed to enable specified AINCOM supply\n"); - - ret = devm_add_action_or_reset(dev, ad7192_reg_disable, aincom); - if (ret) - return ret; - - ret = regulator_get_voltage(aincom); - if (ret < 0) - return dev_err_probe(dev, ret, - "Device tree error, AINCOM voltage undefined\n"); - st->aincom_mv = ret / MILLI; + ret = devm_regulator_get_enable_read_voltage(dev, "aincom"); + if (ret < 0 && ret != -ENODEV) + return dev_err_probe(dev, ret, "Failed to get AINCOM voltage\n"); + + st->aincom_mv = ret == -ENODEV ? 0 : ret / MILLI; + + /* AVDD can optionally be used as reference voltage */ + ret = devm_regulator_get_enable_read_voltage(dev, "avdd"); + if (ret == -ENODEV || ret == -EINVAL) { + int ret2; + + /* + * We get -EINVAL if avdd is a supply with unknown voltage. We + * still need to enable it since it is also a power supply. + */ + ret2 = devm_regulator_get_enable(dev, "avdd"); + if (ret2) + return dev_err_probe(dev, ret2, + "Failed to enable AVDD supply\n"); + } else if (ret < 0) { + return dev_err_probe(dev, ret, "Failed to get AVDD voltage\n"); } - st->avdd = devm_regulator_get(dev, "avdd"); - if (IS_ERR(st->avdd)) - return PTR_ERR(st->avdd); - - ret = regulator_enable(st->avdd); - if (ret) - return dev_err_probe(dev, ret, - "Failed to enable specified AVdd supply\n"); - - ret = devm_add_action_or_reset(dev, ad7192_reg_disable, st->avdd); - if (ret) - return ret; + avdd_mv = ret == -ENODEV || ret == -EINVAL ? 0 : ret / MILLI; ret = devm_regulator_get_enable(dev, "dvdd"); if (ret) return dev_err_probe(dev, ret, "Failed to enable specified DVdd supply\n"); - st->vref = devm_regulator_get_optional(dev, "vref"); - if (IS_ERR(st->vref)) { - if (PTR_ERR(st->vref) != -ENODEV) - return PTR_ERR(st->vref); - - ret = regulator_get_voltage(st->avdd); - if (ret < 0) - return dev_err_probe(dev, ret, - "Device tree error, AVdd voltage undefined\n"); - } else { - ret = regulator_enable(st->vref); - if (ret) - return dev_err_probe(dev, ret, - "Failed to enable specified Vref supply\n"); - - ret = devm_add_action_or_reset(dev, ad7192_reg_disable, st->vref); - if (ret) - return ret; - - ret = regulator_get_voltage(st->vref); - if (ret < 0) - return dev_err_probe(dev, ret, - "Device tree error, Vref voltage undefined\n"); + /* + * This is either REFIN1 or REFIN2 depending on adi,refin2-pins-enable. + * If this supply is not present, fall back to AVDD as reference. + */ + ret = devm_regulator_get_enable_read_voltage(dev, "vref"); + if (ret == -ENODEV) { + if (avdd_mv == 0) + return dev_err_probe(dev, -ENODEV, + "No reference voltage available\n"); + } else if (ret < 0) { + return ret; } - st->int_vref_mv = ret / 1000; + + st->int_vref_mv = ret == -ENODEV ? avdd_mv : ret / MILLI; st->chip_info = spi_get_device_match_data(spi); indio_dev->name = st->chip_info->name; From patchwork Mon Jun 24 12:49:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13709438 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 178BD13CFB6; Mon, 24 Jun 2024 12:50:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719233417; cv=none; b=QDdM553EaqNDavmV/9pUeBFGJWGz7LXSNwjK1hZieMStfodL4nbMymENUveDoVIDWUCyrSXsoPZU18ALXJUc8RFBsMTKzj2jwYAPm3tjRgcxvn3Kkhijt09cijzxyJbz1vsTEEyohqKMX1ZIkUJompy8u1FYqXSUO8dRseK13Bc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719233417; c=relaxed/simple; bh=Bu8F+l13HHuz2d/P/HSpMq3O34R6YheN5LcYoDmAWDo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=U7JEn2ZfUStAUFkNd7j2EUvj7bBysUdEJf0Vrw9Ww4/iRtHMnSp8poxp+pt+nhgNilOUSUKATgXQTKvvJHKMCaI9bfsXx6GW7zLz1F92BWZqrelxesq/1tmfxJqZ6ysIalMVWLh16x/4caukALKxXCHUQ4KDXGA44Xs2ZfagGaY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=T9lK34yC; arc=none smtp.client-ip=209.85.221.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="T9lK34yC" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-35f2c9e23d3so3283328f8f.0; Mon, 24 Jun 2024 05:50:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719233414; x=1719838214; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LOfPkYxWy6ZUkypcBlYLtOXF3/JTIBRyQPldNQhVo1E=; b=T9lK34yC0l0GIYxSHmIyH9J9UY1MfVD7GDwa664rK1iKiEYYPSmlDu5PYI2jatQX+F 2Tm0HfcZeyPjC05w2dEVUMWemETZvxIVCDPTI6l/neAHKSkTglfrrtluiVsJAMO6H375 svKZ+1kiwYLwJHobHLG3MXCf/UQSbvCLv3WIXxqOhdXMGd9aXW3FugtAAsGN4d4IVBCg 3VuDXT0PTxowaRVeoEUUnSpWIDY8PuSvcrwxEdXxJZLHMG0as0CB2E/J5PZHdbaqGQUx oGBU7poJ7hqO3+JGrNjMAy5XnSPTgFMTL9o7aHLRCo+SucsAvRaXFq8SFC17yYK1vqYt TS7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719233414; x=1719838214; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LOfPkYxWy6ZUkypcBlYLtOXF3/JTIBRyQPldNQhVo1E=; b=l2QlDWe22o9eCDw1jq3DSXT2r0YKuw0V1Oh2l/gLME75sKTA6LLbvWNYh3Wh548H7c BltSbp2EcQm9SpMpFZcJv9pIO4wb4hgno1OinGnsI7UFbwvcUPhW4VlhHhCUeHFCcrFi nT7+TrgB2Hs9QQ7RW11+Dj9ifxVAYqE1g+uU6o5psvDf4dAsCXw+QwV8LO+hRwk5pGzy xbR6UIGrfbFwZIio6ZRc0uGGgg0ztEcXXEygfE20LqfzRGkqD3Pr2fUbX1PXUpeeyMHK /h07u6OmdrzBUR8/5+JqpEFl0HqdwSJIQjIehOY4qu3nK2SG4iWVnRlRO94bDxnrYPA6 /DYg== X-Forwarded-Encrypted: i=1; AJvYcCXMimQIsdsVnXzQC/Ll0wMTubJswBmynWFE02ixSsPBNpCjZCaUWdP0vx0FNlknyUZw+wokPvjEFKNF3yssfWPxV+socIL2d2RghKg62pIou4Im900c8uR67XGfbZuy6Fpw+YdHO4QU7z9FdvUcpipLZqipf7vcm3pk8A0fosKQCL4uOA== X-Gm-Message-State: AOJu0YwiD0NmFUqBRL8ZoN350Jof0MUiJWOsKQHJSzVjjipkeWVxzk4P Im/RHNb2XyahjFrihLYL4bd64miZtUptMvRD80t73vULrt7KTJ9jpJ8zew== X-Google-Smtp-Source: AGHT+IHvUlvMMpqCEaRYN3JwnyLslaAEjgabuVMm5es0bzJddB74tXWAgN4rN/dnc8cC0vnt6mNN+Q== X-Received: by 2002:adf:f68c:0:b0:362:23d5:3928 with SMTP id ffacd0b85a97d-366e3293282mr4456753f8f.17.1719233414097; Mon, 24 Jun 2024 05:50:14 -0700 (PDT) Received: from spiri.. ([5.14.146.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4247d208b60sm174127905e9.37.2024.06.24.05.50.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 05:50:13 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Subject: [PATCH v6 2/6] dt-bindings: iio: adc: ad7192: Update clock config Date: Mon, 24 Jun 2024 15:49:37 +0300 Message-Id: <20240624124941.113010-3-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624124941.113010-1-alisa.roman@analog.com> References: <20240624124941.113010-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 There are actually 4 configuration modes of clock source for AD719X devices. Either a crystal can be attached externally between MCLK1 and MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 pin. The other 2 modes make use of the 4.92MHz internal clock. To configure external clock as either a crystal or a CMOS-compatible clock, changing the register settings is necessary. Therefore, add clock name xtal alongside mclk. By selecting one or the other, the register is configured. The presence of an external clock source is optional, not required. When both clocks and clock-names properties are present, an external clock source is used. If the intention is to use the internal clock, both properties should be absent. Modify required properties accordingly. Signed-off-by: Alisa-Dariana Roman Reviewed-by: Conor Dooley --- .../bindings/iio/adc/adi,ad7192.yaml | 22 ++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml index a03da9489ed9..c3adc32684cf 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml @@ -39,11 +39,15 @@ properties: clocks: maxItems: 1 - description: phandle to the master clock (mclk) + description: + Optionally, either a crystal can be attached externally between MCLK1 and + MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 + pin. 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([5.14.146.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4247d208b60sm174127905e9.37.2024.06.24.05.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 05:50:17 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Subject: [PATCH v6 3/6] iio: adc: ad7192: Update clock config Date: Mon, 24 Jun 2024 15:49:38 +0300 Message-Id: <20240624124941.113010-4-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624124941.113010-1-alisa.roman@analog.com> References: <20240624124941.113010-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 There are actually 4 configuration modes of clock source for AD719X devices. Either a crystal can be attached externally between MCLK1 and MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 pin. The other 2 modes make use of the 4.92MHz internal clock. Removed properties adi,int-clock-output-enable and adi,clock-xtal were undocumented. Use cleaner alternative of configuring external clock by using clock names mclk and xtal. Removed functionality of AD7192_CLK_INT_CO restored in complementary patch. Signed-off-by: Alisa-Dariana Roman --- drivers/iio/adc/ad7192.c | 56 ++++++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index 334ab90991d4..940517df5429 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -396,25 +396,37 @@ static inline bool ad7192_valid_external_frequency(u32 freq) freq <= AD7192_EXT_FREQ_MHZ_MAX); } -static int ad7192_clock_select(struct ad7192_state *st) +static const char *const ad7192_clock_names[] = { + "xtal", + "mclk" +}; + +static int ad7192_clock_setup(struct ad7192_state *st) { struct device *dev = &st->sd.spi->dev; - unsigned int clock_sel; - - clock_sel = AD7192_CLK_INT; + int ret; - /* use internal clock */ - if (!st->mclk) { - if (device_property_read_bool(dev, "adi,int-clock-output-enable")) - clock_sel = AD7192_CLK_INT_CO; + ret = device_property_match_property_string(dev, "clock-names", + ad7192_clock_names, + ARRAY_SIZE(ad7192_clock_names)); + if (ret < 0) { + st->clock_sel = AD7192_CLK_INT; + st->fclk = AD7192_INT_FREQ_MHZ; } else { - if (device_property_read_bool(dev, "adi,clock-xtal")) - clock_sel = AD7192_CLK_EXT_MCLK1_2; - else - clock_sel = AD7192_CLK_EXT_MCLK2; + st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret; + + st->mclk = devm_clk_get_enabled(dev, ad7192_clock_names[ret]); + if (IS_ERR(st->mclk)) + return dev_err_probe(dev, PTR_ERR(st->mclk), + "Failed to get mclk\n"); + + st->fclk = clk_get_rate(st->mclk); + if (!ad7192_valid_external_frequency(st->fclk)) + return dev_err_probe(dev, -EINVAL, + "External clock frequency out of bounds\n"); } - return clock_sel; + return 0; } static int ad7192_setup(struct iio_dev *indio_dev, struct device *dev) @@ -1275,21 +1287,9 @@ static int ad7192_probe(struct spi_device *spi) if (ret) return ret; - st->fclk = AD7192_INT_FREQ_MHZ; - - st->mclk = devm_clk_get_optional_enabled(dev, "mclk"); - if (IS_ERR(st->mclk)) - return PTR_ERR(st->mclk); - - st->clock_sel = ad7192_clock_select(st); - - if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 || - st->clock_sel == AD7192_CLK_EXT_MCLK2) { - st->fclk = clk_get_rate(st->mclk); - if (!ad7192_valid_external_frequency(st->fclk)) - return dev_err_probe(dev, -EINVAL, - "External clock frequency out of bounds\n"); - } + ret = ad7192_clock_setup(st); + if (ret) + return ret; ret = ad7192_setup(indio_dev, dev); if (ret) From patchwork Mon Jun 24 12:49:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13709440 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF49713D88C; Mon, 24 Jun 2024 12:50:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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([5.14.146.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4247d208b60sm174127905e9.37.2024.06.24.05.50.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 05:50:21 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Subject: [PATCH v6 4/6] dt-bindings: iio: adc: ad7192: Add clock provider Date: Mon, 24 Jun 2024 15:49:39 +0300 Message-Id: <20240624124941.113010-5-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624124941.113010-1-alisa.roman@analog.com> References: <20240624124941.113010-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Internal clock of AD719X devices can be made available on MCLK2 pin. Add clock provider to support this functionality. The clock source can be either provided externally or the internal clock is used. Pair of clocks and clock-names property is mutally exclusive with #clock-cells property. Modify second example to showcase the mode where internal clock is used. Signed-off-by: Alisa-Dariana Roman Reviewed-by: Conor Dooley --- .../devicetree/bindings/iio/adc/adi,ad7192.yaml | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml index c3adc32684cf..384bff7e9bb7 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml @@ -42,13 +42,17 @@ properties: description: Optionally, either a crystal can be attached externally between MCLK1 and MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 - pin. If absent, internal 4.92MHz clock is used. + pin. If absent, internal 4.92MHz clock is used, which can be made + available on MCLK2 pin. clock-names: enum: - xtal - mclk + "#clock-cells": + const: 0 + interrupts: maxItems: 1 @@ -169,6 +173,12 @@ allOf: required: - clocks - clock-names + - oneOf: + - required: + - clocks + - clock-names + - required: + - "#clock-cells" unevaluatedProperties: false @@ -214,8 +224,7 @@ examples: spi-max-frequency = <1000000>; spi-cpol; spi-cpha; - clocks = <&ad7192_mclk>; - clock-names = "mclk"; + #clock-cells = <0>; interrupts = <25 0x2>; interrupt-parent = <&gpio>; aincom-supply = <&aincom>; From patchwork Mon Jun 24 12:49:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13709441 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6168B13DBA0; Mon, 24 Jun 2024 12:50:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719233429; cv=none; b=hLy3qI48kPxZcBHUYEI1j0JNPN2Fw2d9NqGPnYUkIRg+SBN3zMPAjWQo39kmyQIZgvb4U4mJY3OZG7IFWuQK55kBLy0bDKA0GudYXRcD1+jJttBUhWwPcZ1SnEXmUP3vYK7OJdA/5ege0jc25B0jvrdMecc8CsJ2dg/MZBwLlSo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719233429; c=relaxed/simple; bh=pWCyGoSwbSVi51UcYwjzYptyAKhEQbLVCZhUW0i1vc8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QX44KwCmlJ+uU96oBqRUIAUKnhWEDufR2rrK1Zq/feP9LTjrcer8s4vsU2B4KmbAj+pxKPfJeRh1A6bek5i5JkJqnwgrz+z6MZS/wmr+tQpFEwuW8MfPwE4JL4k8pI+23jbjgKjtZ48ZuIB0gqmm3ip/LV/vsWoIp1EVXAIgifo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=CCnDgBuH; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CCnDgBuH" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-421bb51d81aso35695255e9.3; Mon, 24 Jun 2024 05:50:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719233426; x=1719838226; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qIFPwPUe239jQzWzpuE4uB77KNgGi1q0uRESeNjXXyI=; b=CCnDgBuHbmriKslf8YSCRqeP1Ur9Xvsaph1pbH+KgS8ZgmEjt5x7kBPB/N+YkTkjCG K3l2VJyxfB0u2bBxIIsgR+HwGw3EwGWFvihpSLI1vGlgDXcYPAQTaqIkOr9o77y59SNR bvjLqPiEwZBOU1tPaRgtOKlwE3o5Ix8LaJM8vXRhvU1YZfTOToTK751Y+K1/wXFdRlfH waxznc3YUqjr2UoZJMzFWd7lm0466VFs0hOwRQ1tG9QCrALKiZajL8CEBfwVts3loF5x fN2QGjpJ9aShAlZSijvcXhOF6NvGBwlUs2PNw6GWb8Cj/r7ir2e37uBPK5w4DI+BnZ/+ Ntjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719233426; x=1719838226; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qIFPwPUe239jQzWzpuE4uB77KNgGi1q0uRESeNjXXyI=; b=ocFrAp2cAwAndFYzAIq6xBfDtJLKhVBaU73bliGmrncSBA7QDinN4Y3xzESSIZ9fDh v/Vlc/ymmKnUOC2GmLyanqKNjU2IqqERUipHtm4+uqdy+mVJ2RLYa6rGn0nrok8X0Egv MunU/MlrMBqvkio5aeOB/VrjwvFxbA0Z/w7/pjJYeXcI8TgW4zrCaQw3pnPM65pxC921 j0pph5um5HwgI8vPbMN6sb3Jedi0ucAQHXlKCKyB3p4OqVUNrtJx2lHRd/PJUf5IOA5m yGL6xU/woNjlqLFYB8lfA87GVd0w4qK5NnQr5P6A+5RaHgQ5ioG/f0WnkD0Ghpms/CyO E9RQ== X-Forwarded-Encrypted: i=1; AJvYcCUvpr29yXyD55q9zui+y/Rk65WNm9ebgIDmNdsEG3DeVNz3lcGBw+48U4J8QG9vDVNZCSU0aybJHQluM4SpMCXAeLhZun27D8dyWiyIGiQHBXK9ZkJv69wPt5LTnDcZWqqPkxOpSeUIuHQwtO8gd+LWMiPLKalpXGRHopnbmn9FZfpOzA== X-Gm-Message-State: AOJu0YyUS8tvsY7UybTyDFhfJ93cm7y69yD2KuQnQCaA76LziIAzW7tl gy7Tbd9BsK6CXbLjML4x9/SrRMoFYXVxMCl/YEtmQwzWDXUbhuBV X-Google-Smtp-Source: AGHT+IHmyjK36pKqyTQWC5GhQhakJszDnv0awVLvhIavnLVLWesTt9RnwQUJraKItpMARSmboP0XLg== X-Received: by 2002:a05:600c:3209:b0:424:7d42:fd7a with SMTP id 5b1f17b1804b1-4248cc2b71cmr29101425e9.15.1719233425580; Mon, 24 Jun 2024 05:50:25 -0700 (PDT) Received: from spiri.. ([5.14.146.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4247d208b60sm174127905e9.37.2024.06.24.05.50.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 05:50:25 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Subject: [PATCH v6 5/6] iio: adc: ad7192: Add clock provider Date: Mon, 24 Jun 2024 15:49:40 +0300 Message-Id: <20240624124941.113010-6-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624124941.113010-1-alisa.roman@analog.com> References: <20240624124941.113010-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Internal clock of AD719X devices can be made available on MCLK2 pin. Add clock provider to support this functionality. Signed-off-by: Alisa-Dariana Roman Reviewed-by: Alexandru Ardelean --- drivers/iio/adc/ad7192.c | 89 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index 940517df5429..90763c14679d 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -201,6 +202,7 @@ struct ad7192_chip_info { struct ad7192_state { const struct ad7192_chip_info *chip_info; struct clk *mclk; + struct clk_hw int_clk_hw; u16 int_vref_mv; u32 aincom_mv; u32 fclk; @@ -401,6 +403,88 @@ static const char *const ad7192_clock_names[] = { "mclk" }; +static struct ad7192_state *clk_hw_to_ad7192(struct clk_hw *hw) +{ + return container_of(hw, struct ad7192_state, int_clk_hw); +} + +static unsigned long ad7192_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return AD7192_INT_FREQ_MHZ; +} + +static int ad7192_clk_output_is_enabled(struct clk_hw *hw) +{ + struct ad7192_state *st = clk_hw_to_ad7192(hw); + + return st->clock_sel == AD7192_CLK_INT_CO; +} + +static int ad7192_clk_prepare(struct clk_hw *hw) +{ + struct ad7192_state *st = clk_hw_to_ad7192(hw); + int ret; + + st->mode &= ~AD7192_MODE_CLKSRC_MASK; + st->mode |= AD7192_CLK_INT_CO; + + ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); + if (ret) + return ret; + + st->clock_sel = AD7192_CLK_INT_CO; + + return 0; +} + +static void ad7192_clk_unprepare(struct clk_hw *hw) +{ + struct ad7192_state *st = clk_hw_to_ad7192(hw); + int ret; + + st->mode &= ~AD7192_MODE_CLKSRC_MASK; + st->mode |= AD7192_CLK_INT; + + ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); + if (ret) + return; + + st->clock_sel = AD7192_CLK_INT; +} + +static const struct clk_ops ad7192_int_clk_ops = { + .recalc_rate = ad7192_clk_recalc_rate, + .is_enabled = ad7192_clk_output_is_enabled, + .prepare = ad7192_clk_prepare, + .unprepare = ad7192_clk_unprepare, +}; + +static int ad7192_register_clk_provider(struct ad7192_state *st) +{ + struct device *dev = &st->sd.spi->dev; + struct clk_init_data init = {}; + int ret; + + if (!IS_ENABLED(CONFIG_COMMON_CLK)) + return 0; + + init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk", + fwnode_get_name(dev_fwnode(dev))); + if (!init.name) + return -ENOMEM; + + init.ops = &ad7192_int_clk_ops; + + st->int_clk_hw.init = &init; + ret = devm_clk_hw_register(dev, &st->int_clk_hw); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &st->int_clk_hw); +} + static int ad7192_clock_setup(struct ad7192_state *st) { struct device *dev = &st->sd.spi->dev; @@ -412,6 +496,11 @@ static int ad7192_clock_setup(struct ad7192_state *st) if (ret < 0) { st->clock_sel = AD7192_CLK_INT; st->fclk = AD7192_INT_FREQ_MHZ; + + ret = ad7192_register_clk_provider(st); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register clock provider\n"); } else { st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret; From patchwork Mon Jun 24 12:49:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13709442 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E29213DDDC; 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([5.14.146.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4247d208b60sm174127905e9.37.2024.06.24.05.50.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 05:50:29 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Subject: [PATCH v6 6/6] MAINTAINERS: Update AD7192 driver maintainer Date: Mon, 24 Jun 2024 15:49:41 +0300 Message-Id: <20240624124941.113010-7-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624124941.113010-1-alisa.roman@analog.com> References: <20240624124941.113010-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Alexandru Tachici has not been active. Also the email address included is not reachable anymore. I was assigned to work on the driver instead. Remove Alexandru Tachici and add myself as maintainer of AD7192 driver. Signed-off-by: Alisa-Dariana Roman --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 9517093d889d..ab1e82fd3b76 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1217,7 +1217,7 @@ F: Documentation/devicetree/bindings/iio/adc/adi,ad7091r* F: drivers/iio/adc/ad7091r* ANALOG DEVICES INC AD7192 DRIVER -M: Alexandru Tachici +M: Alisa-Dariana Roman L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers