From patchwork Mon Jun 24 13:42:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 13709536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 161A7C2BD09 for ; Mon, 24 Jun 2024 13:43:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Message-ID:Date:Subject:Cc:To:From:Reply-To: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=2DPHEkgZ7R75Xt+0qmmV1YKtyxYw1BQWMR5WZofqK1Q=; b=A2KsIze9PRlB9cfkdB35FgIf5v BKIvn2jbLqYKTdfZag05ubH6UyH5RLK4ypxU1HS5m7pgtm5fHG7uRSJvGCcPtzfN77qx/s71w3Qil Q90V0hT9nWExR6YtqXob/pDC7b2o8XsuAo+n6c3jnF5g6VIB9VRD/1nmCxTGu48irQBwoD1dmEx2d HFc5kkc8vnEfomDsCVYbEN99LI6EpKECDELXWBteWLTj0dZJOxgOLXT62885GlFuBD/cAj1aNst0I Nl5vx1AzXVUNHUIHJ0QEhS36E8EY1C0j/SIew/sjTh5++Yki17QbJQOLM1Kj16RQ1f+Jskn6Tgm2P 1U3CGQ3w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sLjyS-0000000GyPa-3SmU; Mon, 24 Jun 2024 13:43:12 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sLjyM-0000000GyNc-0HYu for linux-arm-kernel@lists.infradead.org; Mon, 24 Jun 2024 13:43:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1719236586; x=1750772586; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=2DPHEkgZ7R75Xt+0qmmV1YKtyxYw1BQWMR5WZofqK1Q=; b=DuquO1bwn3vkA4PqBviofdtZGPxZO3fKq3duNFxMfd+gOJziNh/4f+lG gFw+ednynKeJAI+SqsyhbtRHyUL1TiJKylK4k36oRqhGi7H7LRmnAKDGD Q5QgSfdM0I1zbKdx3W6BqzbcLqOSj15ky7/os30Rol1J+N71l4YW8fv+o 8lzEG+hMD6bN5CZXBY3SSKLpE7hN0USXfP8N3icNTpsE7WjA7VYsAlmg+ 66ARb5wx2VMgw04WQPjMnOydHIEDsEfLHpHcZkENWmTCkkbzCulNp9Gxs 7xm/9vlpjjaCkxgMAGxzsO6EW/dfAJPOgi8fwBjgpgjk9OaI8DM7+ehv+ Q==; X-CSE-ConnectionGUID: wY/cFS7CQ56DOqf3NYz12Q== X-CSE-MsgGUID: H3t8Ipp5QT6b/JoFLHFnRw== X-IronPort-AV: E=Sophos;i="6.08,262,1712613600"; d="scan'208";a="37554370" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 24 Jun 2024 15:43:01 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8D72A16747D; Mon, 24 Jun 2024 15:42:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1719236577; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding; bh=2DPHEkgZ7R75Xt+0qmmV1YKtyxYw1BQWMR5WZofqK1Q=; b=Ji7jBq/41bMdkMDoOq/Z4Ac7GQYB6gz80EiXxEwzlvYJ+ZB6YOfkONVgIX3ZbO1cw/n84k z/7DSb0eD622sgOnfIJ50oUz1pGJYGuMO3A4DUeEcev6UDSr7igANNBwzr7GANr+GbW7M1 BUEQRkq1+I+EpdoNJztrAkZswSmZkMWCeTH20AFCWwuok2lpsK1nY0rwKhMYQzx6VoCAgR PRBjPWjLwJUMszK1kvizZUf90Np/h2RzpzAC4vh6tEN6GVjO5mU1c61CjE2RhUERdyO2xR tr9VXaWKUctMTmIEoi0H4USgEFAqBYIDvq6lRC7WFfPsH2y905YXj702Mox2vQ== From: Matthias Schiffer To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@ew.tq-group.com, Matthias Schiffer Subject: [PATCH v2] arm64: dts: ti: k3-am642-tqma64xxl-mbax4xxl: add PRU Ethernet support Date: Mon, 24 Jun 2024 15:42:35 +0200 Message-ID: <20240624134235.202243-1-matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240624_064306_929314_CC28F9D5 X-CRM114-Status: GOOD ( 12.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add PRU Ethernet controller and PHY nodes, as it was previously done for the AM64x EVM Device Trees. Signed-off-by: Matthias Schiffer --- v2: - Dropped binding change patch - Moved prueth device node to DTS toplevel, matching the AM64x EVM - Update firmware filenames to match EVM .../dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts index 1f4dc5ad1696a..204f5e48a9c63 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -24,6 +24,8 @@ / { aliases { ethernet0 = &cpsw_port1; + ethernet1 = &icssg1_emac0; + ethernet2 = &icssg1_emac1; i2c1 = &mcu_i2c0; mmc1 = &sdhci1; serial0 = &mcu_uart0; @@ -71,6 +73,66 @@ led-1 { }; }; + icssg1_eth: icssg1-eth { + compatible = "ti,am642-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&pru_icssg1_rgmii1_pins>, <&pru_icssg1_rgmii2_pins>; + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + sram = <&oc_sram>; + firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf"; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + ti,mii-g-rt = <&icssg1_mii_g_rt>; + ti,mii-rt = <&icssg1_mii_rt>; + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + icssg1_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg1_phy0c>; + phy-mode = "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + icssg1_emac1: port@1 { + reg = <1>; + phy-handle = <&icssg1_phy03>; + phy-mode = "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + fan0: pwm-fan { compatible = "pwm-fan"; pinctrl-names = "default"; @@ -154,6 +216,42 @@ &epwm5 { status = "okay"; }; +&icssg1_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pru_icssg1_mdio_pins>; + status = "okay"; + + /* phy-mode is fixed up to rgmii-rxid by prueth driver to account for + * the SoC integration, so the only rx-internal-delay and no + * tx-internal-delay is set for the PHYs. + */ + + icssg1_phy03: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + reset-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + ti,rx-fifo-depth = ; + ti,tx-fifo-depth = ; + ti,rx-internal-delay = ; + ti,clk-output-sel = ; + }; + + icssg1_phy0c: ethernet-phy@c { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0xc>; + reset-gpios = <&main_gpio1 51 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + ti,rx-fifo-depth = ; + ti,tx-fifo-depth = ; + ti,rx-internal-delay = ; + ti,clk-output-sel = ; + }; +}; + + &main_gpio0 { pinctrl-names = "default"; pinctrl-0 = <&main_gpio0_digital_pins>,