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([2804:7f0:b401:1758:3e7c:3fff:fe7a:e83b]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-706666e9708sm4974942b3a.121.2024.06.24.11.09.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 11:09:29 -0700 (PDT) From: Gustavo Romero To: qemu-devel@nongnu.org, peter.maydell@linaro.org, richard.henderson@linaro.org Cc: philmd@linaro.org, alex.bennee@linaro.org, gustavo.romero@linaro.org Subject: [PATCH v3 1/3] target/arm: Fix indentation Date: Mon, 24 Jun 2024 18:09:13 +0000 Message-Id: <20240624180915.4528-2-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624180915.4528-1-gustavo.romero@linaro.org> References: <20240624180915.4528-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=gustavo.romero@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Fix comment indentation adding a missing space. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/tcg/cpu64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 0899251eef..71e1bfcd4e 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1167,7 +1167,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = cpu->isar.id_aa64isar2; t = FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */ - t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ + t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ cpu->isar.id_aa64isar2 = t; From patchwork Mon Jun 24 18:09:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Romero X-Patchwork-Id: 13709955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C382CC2BD09 for ; Mon, 24 Jun 2024 18:10:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sLo8K-0002an-I3; Mon, 24 Jun 2024 14:09:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sLo8G-0002aP-9f for qemu-devel@nongnu.org; Mon, 24 Jun 2024 14:09:37 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sLo8E-0005Vs-Ln for qemu-devel@nongnu.org; Mon, 24 Jun 2024 14:09:36 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-70667943931so1495787b3a.0 for ; Mon, 24 Jun 2024 11:09:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719252573; x=1719857373; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PeBqa9wCvLcPCNESG68oA900Bm6fWP80a5dR02zC61U=; b=L+5E4Yil/kqaKoDKacCVsSdOEyvG05MCBi8JYKPNBBB602a2Qto+tBJeEV9ZYxFKTL D4IWKIpMXADBQCHilzp0C/T4jbXNM10GnBeoKucp9OrnrnI+aVTcseT2aS4fz+/+9uDk Eo1xKrYAxZY9uM2H2yE3RNexv6nHmEaTrlf8+u+n52oFuhCDaPZfLkK9+gY0Vf0Au2Nk 8iWcD/fgRvIf/B2gisPA7N1nwhnP3RdeFvv3eh+Wd+rd7mH9EdFmaval8xm27t/6dENW tiHCuu/ejRFR/K10L92BIL6Akf0V9El/nAixQE6GCM3l3QEoYGaz0yTtUnoyScT2wDWx 7Uag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719252573; x=1719857373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PeBqa9wCvLcPCNESG68oA900Bm6fWP80a5dR02zC61U=; b=ffmskbdqX68lTpie5fDtcjASsPcr7e7sfqnwyCLSt+uGS4+iUiMILf5VXhxXMFOGVh rjOf7steYms3gWKEOkZjr5wBUuER+5jZa7JHrIER6Rolyqbhb8pP407b1+kCZJmOPyDp /5vMNALYDwJ7Nj2pesIBQ5PPtU6j/06tVzp2a4mdc+m6WBmEU8W09MlYGtnZg7ChbWPV cSmQ1L0i3E+JBPkPR/Aba+QD2wHg7MBi/jOGNdqotNpitV0pyQ+jVLsPR0Wn2ptTwpCF 1OfgzHmv8y246ne+qLVNkaoXE/FalkhFNFSv6k1/X1TbCnfn7/5OGTYTvb1/JF2gSo1I 5y3A== X-Gm-Message-State: AOJu0Yz0IAQ26Y8IC+msqMKl+I8gI1nhVbtH5TOgHU5lsCid7oIkETiJ i7lFd9SjEk4YJqhv8pHMnpGQcpxmMqv2EhSy/rnJxbk35NMlqZx9UFroscHgLj8r0IjBCDTdw2i P X-Google-Smtp-Source: AGHT+IGCGK6Cj2pLM9Jpmdvm8YTLKDOpTxyuMvdj+n6VjFYHrGFx3jqSKfzzzINB0QOW/PYDCAmc2w== X-Received: by 2002:aa7:8517:0:b0:706:6f18:839d with SMTP id d2e1a72fcca58-706745be097mr5080272b3a.14.1719252572972; Mon, 24 Jun 2024 11:09:32 -0700 (PDT) Received: from amd.. ([2804:7f0:b401:1758:3e7c:3fff:fe7a:e83b]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-706666e9708sm4974942b3a.121.2024.06.24.11.09.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 11:09:32 -0700 (PDT) From: Gustavo Romero To: qemu-devel@nongnu.org, peter.maydell@linaro.org, richard.henderson@linaro.org Cc: philmd@linaro.org, alex.bennee@linaro.org, gustavo.romero@linaro.org Subject: [PATCH v3 2/3] target/arm: Move initialization of debug ID registers Date: Mon, 24 Jun 2024 18:09:14 +0000 Message-Id: <20240624180915.4528-3-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624180915.4528-1-gustavo.romero@linaro.org> References: <20240624180915.4528-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=gustavo.romero@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move the initialization of the debug ID registers to aa32_max_features, which is used to set the 32-bit ID registers. This ensures that the debug ID registers are consistently set for the max CPU in a single place. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/tcg/cpu32.c | 31 ++++++++++++++++++++++++++++--- 2 files changed, 30 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3841359d0f..d8eb986a04 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2299,6 +2299,8 @@ FIELD(DBGDEVID, DOUBLELOCK, 20, 4) FIELD(DBGDEVID, AUXREGS, 24, 4) FIELD(DBGDEVID, CIDMASK, 28, 4) +FIELD(DBGDEVID1, PCSROFFSET, 0, 4) + FIELD(MVFR0, SIMDREG, 0, 4) FIELD(MVFR0, FPSP, 4, 4) FIELD(MVFR0, FPDP, 8, 4) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index bdd82d912a..28a5c033bb 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -87,6 +87,34 @@ void aa32_max_features(ARMCPU *cpu) t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_dfr0 = t; + /* Debug ID registers. */ + + /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ + t = 0x00008000; + t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1); + t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); + t = FIELD_DP32(t, DBGDIDR, VERSION, 6); /* Armv8 debug */ + t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); + t = FIELD_DP32(t, DBGDIDR, BRPS, 5); + t = FIELD_DP32(t, DBGDIDR, WRPS, 3); + cpu->isar.dbgdidr = t; + + t = 0; + t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); + t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); + t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); + t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); + t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); + t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); + t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0); + t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0); + cpu->isar.dbgdevid = t; + + /* Bits[31:4] are RES0. */ + t = 0; + t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); + cpu->isar.dbgdevid1 = t; + t = cpu->isar.id_dfr1; t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ cpu->isar.id_dfr1 = t; @@ -955,9 +983,6 @@ static void arm_max_initfn(Object *obj) cpu->isar.id_isar4 = 0x00011142; cpu->isar.id_isar5 = 0x00011121; cpu->isar.id_isar6 = 0; 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([2804:7f0:b401:1758:3e7c:3fff:fe7a:e83b]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-706666e9708sm4974942b3a.121.2024.06.24.11.09.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 11:09:35 -0700 (PDT) From: Gustavo Romero To: qemu-devel@nongnu.org, peter.maydell@linaro.org, richard.henderson@linaro.org Cc: philmd@linaro.org, alex.bennee@linaro.org, gustavo.romero@linaro.org Subject: [PATCH v3 3/3] target/arm: Enable FEAT_Debugv8p8 for -cpu max Date: Mon, 24 Jun 2024 18:09:15 +0000 Message-Id: <20240624180915.4528-4-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624180915.4528-1-gustavo.romero@linaro.org> References: <20240624180915.4528-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=gustavo.romero@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Enable FEAT_Debugv8p8 for max CPU. This feature is out of scope for QEMU since it concerns the external debug interface for JTAG, but is mandatory in Armv8.8 implementations, hence it is reported as supported in the ID registers. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu32.c | 6 +++--- target/arm/tcg/cpu64.c | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 1a06a5feb6..3ab6e72667 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -41,6 +41,7 @@ the following architecture extensions: - FEAT_Debugv8p1 (Debug with VHE) - FEAT_Debugv8p2 (Debug changes for v8.2) - FEAT_Debugv8p4 (Debug changes for v8.4) +- FEAT_Debugv8p8 (Debug changes for v8.8) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_DoubleFault (Double Fault Extension) - FEAT_E0PD (Preventing EL0 access to halves of address maps) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 28a5c033bb..20c2737f17 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -82,8 +82,8 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 = t; t = cpu->isar.id_dfr0; - t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ - t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ + t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_dfr0 = t; @@ -93,7 +93,7 @@ void aa32_max_features(ARMCPU *cpu) t = 0x00008000; t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1); t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); - t = FIELD_DP32(t, DBGDIDR, VERSION, 6); /* Armv8 debug */ + t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); t = FIELD_DP32(t, DBGDIDR, BRPS, 5); t = FIELD_DP32(t, DBGDIDR, WRPS, 3); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 71e1bfcd4e..fe232eb306 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1253,7 +1253,7 @@ void aarch64_max_tcg_initfn(Object *obj) cpu->isar.id_aa64zfr0 = t; t = cpu->isar.id_aa64dfr0; - t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ cpu->isar.id_aa64dfr0 = t;