From patchwork Mon Jun 24 19:10:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13709975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26672C30653 for ; Mon, 24 Jun 2024 19:10:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6F34D10E22E; Mon, 24 Jun 2024 19:10:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="DkoOPGho"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7894310E18C for ; Mon, 24 Jun 2024 19:10:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719256238; x=1750792238; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=NU85qjc/EGoQILAfmgViN/x6t7b/gDJsf66WGjK0CbE=; b=DkoOPGhodHB/IG7BPBSMQkShrqo472JkV4X9ZKgrsm8lynLyCzJH3E57 GGQcEzpU5Ky26fst6YRK8bMEYzUaWXBq3+uU6VDpC9N400R2SOWygdrqe bOWfbihAI9VJgpRdnCLiAGoVxmsgDoM8LsBoqp6vgPuQauQOItmmxXxJU iFHEagkXTbPj0I0QBGJCBXm/6Dl5W3p5kb88ZjUAk1BPSoC8Vf01ptktK 2OkPgw5QjCpkHwoHCR7Baf0xaSNRpjPRKzQXKWmVCoc+OgE/SE/vjGjWm SZ5kRsvCluogn4ATA6fHAIEXTGZsBxm8fVcmWKwHSYKn453hR8wmj1uEh w==; X-CSE-ConnectionGUID: O6yxlHK/SuCmiZX2ngOKvg== X-CSE-MsgGUID: zoniCI9yTPa2dylvO3XpUw== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16374105" X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="16374105" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2024 12:10:38 -0700 X-CSE-ConnectionGUID: yigAWLJGRnSKzKy+Pqyf9w== X-CSE-MsgGUID: jHe8lxbESwWYT5tguFdrGw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="43371908" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jun 2024 12:10:36 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 24 Jun 2024 22:10:35 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 01/14] drm/i915: Calculate vblank delay more accurately Date: Mon, 24 Jun 2024 22:10:19 +0300 Message-ID: <20240624191032.27333-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240624191032.27333-1-ville.syrjala@linux.intel.com> References: <20240624191032.27333-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Calculate the vblank delay in the vblank evasion code correctly for interlaced modes. The current code assumes that we won't be using an interlaced mode. That assumption is actually valid since we've defeatured interlaced scanout in commit f71c9b7bc35f ("drm/i915/display: Prune Interlace modes for Display >=12") for DSB capable platforms. However the feature is still present in the hardware, and if we ever find the need to re-enable it seems better to calculate the vblank delay correctly. Signed-off-by: Ville Syrjälä Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_vblank.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 5b065e1cd4e4..f183e0d4b2ba 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -652,7 +652,8 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, */ if (intel_color_uses_dsb(new_crtc_state) || new_crtc_state->update_m_n || new_crtc_state->update_lrr) - evade->min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; + evade->min -= intel_mode_vblank_start(adjusted_mode) - + intel_mode_vdisplay(adjusted_mode); } /* must be called with vblank interrupt already enabled! */ From patchwork Mon Jun 24 19:10:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13709976 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67947C2BD09 for ; Mon, 24 Jun 2024 19:10:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DD42F10E238; Mon, 24 Jun 2024 19:10:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ioPLIktO"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 40A8E10E54D for ; Mon, 24 Jun 2024 19:10:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719256241; x=1750792241; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=++ES/L4zdO2/+kYkdBAAjFx7yk7ZNb8spCDmGdekn6Y=; b=ioPLIktOvg26nCKAhwADmcBV9SfHkGwN9LWNryjs+Da+dpwRBrHB2St/ bVd8JMGkxNEIwPYLcTsjB/bzmtsI9WMM3C++HvLLx5L1a8TJxgamtvmGP 6C0E4BROa2KZzgaF7QJDnvun+FdYqLk7TN+KbjznoKhIb5IPmhX50SZWN /GMZl/DDABeaa0tVl2WCKZqIr49tuYVKyOboWvd0LXLxw9xHIpGERLARj 4WBX9aHfGD54GkjZaNksyq60XA2oaM3XxdwBME7YSuHKrIQMmqdQjgMWl 629aI3MUG3YmkRgepjPo9oOMD1b+HhkQLBFtXrFME4YRXoG3G8YorAp2C w==; X-CSE-ConnectionGUID: uOL008f9QDSKfcwc/5LPzg== X-CSE-MsgGUID: gkeQoSs+RsWqz5XenxZtbg== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16374115" X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="16374115" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2024 12:10:41 -0700 X-CSE-ConnectionGUID: 13vf2YbLRiqHvyXTedtB3Q== X-CSE-MsgGUID: qeJvQjpdQU6KWwpzz7TrNw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="43371912" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jun 2024 12:10:39 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 24 Jun 2024 22:10:38 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 02/14] drm/i915: Make vrr_{enabling, disabling}() usable outside intel_display.c Date: Mon, 24 Jun 2024 22:10:20 +0300 Message-ID: <20240624191032.27333-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240624191032.27333-1-ville.syrjala@linux.intel.com> References: <20240624191032.27333-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Give vrr_enabling() and vrr_disabling() slightly fancier names, and pass in the whole atomic state so that they'll be easier to use. We'll need to call at least the disabling part from the DSB code soon enough (so that we can do vblank evasions/etc. correctly on the DSB). Signed-off-by: Ville Syrjälä Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_display.c | 26 +++++++++++++------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c2c388212e2e..01a5faa3fea5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1014,9 +1014,14 @@ static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state, old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; } -static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, - const struct intel_crtc_state *new_crtc_state) +static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state, + struct intel_crtc *crtc) { + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + if (!new_crtc_state->hw.active) return false; @@ -1026,9 +1031,14 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, vrr_params_changed(old_crtc_state, new_crtc_state))); } -static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, - const struct intel_crtc_state *new_crtc_state) +static bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, + struct intel_crtc *crtc) { + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + if (!old_crtc_state->hw.active) return false; @@ -1181,7 +1191,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; - if (vrr_disabling(old_crtc_state, new_crtc_state)) { + if (intel_crtc_vrr_disabling(state, crtc)) { intel_vrr_disable(old_crtc_state); intel_crtc_update_active_timings(old_crtc_state, false); } @@ -6830,8 +6840,6 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - const struct intel_crtc_state *old_crtc_state = - intel_atomic_get_old_crtc_state(state, crtc); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); @@ -6844,7 +6852,7 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, !intel_crtc_needs_modeset(new_crtc_state)) skl_detach_scalers(new_crtc_state); - if (vrr_enabling(old_crtc_state, new_crtc_state)) + if (intel_crtc_vrr_enabling(state, crtc)) intel_vrr_enable(new_crtc_state); } @@ -6944,7 +6952,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, * * FIXME Should be synchronized with the start of vblank somehow... */ - if (vrr_enabling(old_crtc_state, new_crtc_state) || + if (intel_crtc_vrr_enabling(state, crtc) || new_crtc_state->update_m_n || new_crtc_state->update_lrr) intel_crtc_update_active_timings(new_crtc_state, new_crtc_state->vrr.enable); From patchwork Mon Jun 24 19:10:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13709977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EFB19C2BD09 for ; Mon, 24 Jun 2024 19:10:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A7B210E54F; Mon, 24 Jun 2024 19:10:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="O0K2zJGL"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id F34AF10E54D for ; Mon, 24 Jun 2024 19:10:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719256244; x=1750792244; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=hS6fAeHbHTzZ85C0kwH1Dw8XxtaMGid1FCyeoPhMBoo=; b=O0K2zJGLWXg5qS/NbQeD0JWGeMetNsdXnT/tzCUtU8hQ2dG81ZWQPoE4 JwzNk/DcCF3GYMv7hrMULuddtpiT1BRVBCZ1Xin1GL2Tjptq4BE5iHHcb di3a7F/mfJD8XisjTO8XFQm72w8ioRLTusNfb/Pvc8OlZq5zxq9AmnYfY /Vd1cuOuB6T3QSPh7GQ+7MrZ31754WogtXvuE5dEPV58CJFP4ADGI5Oky qp0fK3BFHEyUs90/ePx3gR6X0nMDMaQluBnbWBuFCJQsCKKCWxeEkITUj mhhgh8/OCZ6F4rCX6OR5w3f1K/gvc57krBRdYsAMDjI5q0gxjOkv0SjJV w==; X-CSE-ConnectionGUID: H8fN3LZdRjeeWkiLaZnFsw== X-CSE-MsgGUID: xgjyePGSQoSwlvcvrxTCrw== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16374122" X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="16374122" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2024 12:10:43 -0700 X-CSE-ConnectionGUID: YpNx0P0WQgKPHSD95gwiZA== X-CSE-MsgGUID: dXfa7VQgTD+c+cTttKT4Yg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="43371916" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jun 2024 12:10:41 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 24 Jun 2024 22:10:41 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 03/14] drm/i915/dsb: Hook up DSB error interrupts Date: Mon, 24 Jun 2024 22:10:21 +0300 Message-ID: <20240624191032.27333-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240624191032.27333-1-ville.syrjala@linux.intel.com> References: <20240624191032.27333-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Enable all DSB error/fault interrupts so that we can see if anything goes terribly wrong. Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_display_irq.c | 17 ++++++ drivers/gpu/drm/i915/display/intel_dsb.c | 58 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dsb.h | 6 ++ drivers/gpu/drm/i915/i915_reg.h | 4 ++ 4 files changed, 85 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 5219ba295c74..7169db984651 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -14,6 +14,7 @@ #include "intel_display_trace.h" #include "intel_display_types.h" #include "intel_dp_aux.h" +#include "intel_dsb.h" #include "intel_fdi_regs.h" #include "intel_fifo_underrun.h" #include "intel_gmbus.h" @@ -1143,6 +1144,17 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); + if (HAS_DSB(dev_priv)) { + if (iir & GEN12_DSB_INT(INTEL_DSB_0)) + intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_0); + + if (iir & GEN12_DSB_INT(INTEL_DSB_1)) + intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_1); + + if (iir & GEN12_DSB_INT(INTEL_DSB_2)) + intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_2); + } + if (iir & GEN8_PIPE_VBLANK) intel_handle_vblank(dev_priv, pipe); @@ -1718,6 +1730,11 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) de_port_masked |= DSI0_TE | DSI1_TE; } + if (HAS_DSB(dev_priv)) + de_pipe_masked |= GEN12_DSB_INT(INTEL_DSB_0) | + GEN12_DSB_INT(INTEL_DSB_1) | + GEN12_DSB_INT(INTEL_DSB_2); + de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | gen8_de_pipe_underrun_mask(dev_priv) | diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 2ab3765f6c06..ded696363258 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -339,6 +339,42 @@ static u32 dsb_chicken(struct intel_crtc *crtc) return DSB_SKIP_WAITS_EN; } +static u32 dsb_error_int_status(struct intel_display *display) +{ + struct drm_i915_private *i915 = to_i915(display->drm); + u32 errors; + + errors = DSB_GTT_FAULT_INT_STATUS | + DSB_RSPTIMEOUT_INT_STATUS | + DSB_POLL_ERR_INT_STATUS; + + /* + * All the non-existing status bits operate as + * normal r/w bits, so any attempt to clear them + * will just end up setting them. Never do that so + * we won't mistake them for actual error interrupts. + */ + if (DISPLAY_VER(i915) >= 14) + errors |= DSB_ATS_FAULT_INT_STATUS; + + return errors; +} + +static u32 dsb_error_int_en(struct intel_display *display) +{ + struct drm_i915_private *i915 = to_i915(display->drm); + u32 errors; + + errors = DSB_GTT_FAULT_INT_EN | + DSB_RSPTIMEOUT_INT_EN | + DSB_POLL_ERR_INT_EN; + + if (DISPLAY_VER(i915) >= 14) + errors |= DSB_ATS_FAULT_INT_EN; + + return errors; +} + static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, int dewake_scanline) { @@ -363,6 +399,10 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id), dsb_chicken(crtc)); + intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id), + dsb_error_int_status(display) | DSB_PROG_INT_STATUS | + dsb_error_int_en(display)); + intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id), intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf)); @@ -430,6 +470,9 @@ void intel_dsb_wait(struct intel_dsb *dsb) dsb->free_pos = 0; dsb->ins_start_offset = 0; intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), 0); + + intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id), + dsb_error_int_status(display) | DSB_PROG_INT_STATUS); } /** @@ -513,3 +556,18 @@ void intel_dsb_cleanup(struct intel_dsb *dsb) intel_dsb_buffer_cleanup(&dsb->dsb_buf); kfree(dsb); } + +void intel_dsb_irq_handler(struct intel_display *display, + enum pipe pipe, enum intel_dsb_id dsb_id) +{ + struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(display->drm), pipe); + u32 tmp, errors; + + tmp = intel_de_read_fw(display, DSB_INTERRUPT(pipe, dsb_id)); + intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb_id), tmp); + + errors = tmp & dsb_error_int_status(display); + if (errors) + drm_err(display->drm, "[CRTC:%d:%s] / DSB %d error interrupt: 0x%x\n", + crtc->base.base.id, crtc->base.name, dsb_id, errors); +} diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index bb42749f2ea4..84fc2f8434d1 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -13,8 +13,11 @@ struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; +struct intel_display; struct intel_dsb; +enum pipe; + enum intel_dsb_id { INTEL_DSB_0, INTEL_DSB_1, @@ -41,4 +44,7 @@ void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank); void intel_dsb_wait(struct intel_dsb *dsb); +void intel_dsb_irq_handler(struct intel_display *display, + enum pipe pipe, enum intel_dsb_id dsb_id); + #endif diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0e3d79227e3c..49a9761ca313 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2515,6 +2515,10 @@ #define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */ #define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */ #define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */ +#define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */ +#define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */ +#define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */ +#define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id)) #define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */ #define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */ #define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */ From patchwork Mon Jun 24 19:10:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13709979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7AAC4C2BD09 for ; Mon, 24 Jun 2024 19:11:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AE3A610E54D; Mon, 24 Jun 2024 19:11:01 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="iauHbr7G"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6DEB410E54D for ; Mon, 24 Jun 2024 19:11:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719256260; x=1750792260; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wXBqttQ0LB1p2oR2fMehcf/uL/moWYX7sX8PTRqHuDY=; b=iauHbr7GN7gsP0xI5oIQpcSsr7KwJF3Cno7IDzeAUJPQvBz6f2REAjDO PamTLqm6ToHIoiCETI5HrgPDuzPEvCpZ2Ov+Ts4ZPKZ3pWOEz4PEai76a K5o69L6D7cTF0cvqDrumhaez02dWyU1Povk/gyTkmD0FDIFnwoSRG4sOY 2O58Xgky+O6ddjoJzm4eBywgQV1ONYtcqjqAHFZxn6ZDB/QB0TeaBeafV rBqtXAbwGrjafekfWSTPnNi7c8Xcr6A25vcEx4aGD0WvPLAfCiQ8acGdH Xgye20bNytbRkP7p04ajgKHeg4/1TA1JXr7tVQqUiotBjQGnLeERvDg3W w==; X-CSE-ConnectionGUID: +gjGCZNdSse7SuCN15L5QQ== X-CSE-MsgGUID: brVvJJemSPWrnUtnPKMgig== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16374172" X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="16374172" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2024 12:10:47 -0700 X-CSE-ConnectionGUID: gVRqgtYoRxmS0bIBQeyQcg== X-CSE-MsgGUID: 5G6ZTe0BQXyCFJNCO23djQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="43371947" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jun 2024 12:10:44 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 24 Jun 2024 22:10:44 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH 04/14] drm/i915/dsb: Convert dewake_scanline to a hw scanline number earlier Date: Mon, 24 Jun 2024 22:10:22 +0300 Message-ID: <20240624191032.27333-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240624191032.27333-1-ville.syrjala@linux.intel.com> References: <20240624191032.27333-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Currently we switch from out software idea of a scanline to the hw's idea of a scanline during the commit phase in _intel_dsb_commit(). While that is slightly easier due to fastsets fiddling with the timings, we'll also need to generate proper hw scanline numbers already when emitting DSB scanline wait instructions. So this approach won't do in the future. Switch to hw scanline numbers earlier. Also intel_dsb_dewake_scanline() itself already makes some assumptions about VRR that don't take into account VRR toggling during fastsets, so technically delaying the sw->hw conversion doesn't even help us. The other reason for delaying the conversion was that we are using intel_get_crtc_scanline() during intel_dsb_commit() which gives us the current sw scanline. But this is pretty low level stuff anyway so just using raw PIPEDSL reads seems fine here, and that of course gives us the hw scanline directly, reducing the need to do so many conversions. v2: Return the non-hw scanline from intel_dsb_dewake_scanline() Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 21 ++++++++++++--------- drivers/gpu/drm/i915/display/intel_vblank.c | 9 ++++----- drivers/gpu/drm/i915/display/intel_vblank.h | 3 ++- 3 files changed, 18 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index ded696363258..cee33c66a26b 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -6,6 +6,7 @@ #include "i915_drv.h" #include "i915_irq.h" +#include "i915_reg.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_types.h" @@ -42,7 +43,7 @@ struct intel_dsb { */ unsigned int ins_start_offset; - int dewake_scanline; + int hw_dewake_scanline; }; /** @@ -376,7 +377,7 @@ static u32 dsb_error_int_en(struct intel_display *display) } static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, - int dewake_scanline) + int hw_dewake_scanline) { struct intel_crtc *crtc = dsb->crtc; struct intel_display *display = to_intel_display(crtc->base.dev); @@ -406,10 +407,8 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id), intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf)); - if (dewake_scanline >= 0) { - int diff, hw_dewake_scanline; - - hw_dewake_scanline = intel_crtc_scanline_to_hw(crtc, dewake_scanline); + if (hw_dewake_scanline >= 0) { + int diff, position; intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id), DSB_ENABLE_DEWAKE | @@ -419,7 +418,9 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, * Force DEwake immediately if we're already past * or close to racing past the target scanline. */ - diff = dewake_scanline - intel_get_crtc_scanline(crtc); + position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK; + + diff = hw_dewake_scanline - position; intel_de_write_fw(display, DSB_PMCTRL_2(pipe, dsb->id), (diff >= 0 && diff < 5 ? DSB_FORCE_DEWAKE : 0) | DSB_BLOCK_DEWAKE_EXTENSION); @@ -441,7 +442,7 @@ void intel_dsb_commit(struct intel_dsb *dsb, { _intel_dsb_commit(dsb, wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0, - wait_for_vblank ? dsb->dewake_scanline : -1); + wait_for_vblank ? dsb->hw_dewake_scanline : -1); } void intel_dsb_wait(struct intel_dsb *dsb) @@ -529,7 +530,9 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, dsb->size = size / 4; /* in dwords */ dsb->free_pos = 0; dsb->ins_start_offset = 0; - dsb->dewake_scanline = intel_dsb_dewake_scanline(crtc_state); + + dsb->hw_dewake_scanline = + intel_crtc_scanline_to_hw(crtc_state, intel_dsb_dewake_scanline(crtc_state)); return dsb; diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index f183e0d4b2ba..56c8033eec4c 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -284,13 +284,12 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) return (position + vtotal + crtc->scanline_offset) % vtotal; } -int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline) +int intel_crtc_scanline_to_hw(const struct intel_crtc_state *crtc_state, + int scanline) { - const struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); - const struct drm_display_mode *mode = &vblank->hwmode; - int vtotal = intel_mode_vtotal(mode); + int vtotal = intel_mode_vtotal(&crtc_state->hw.adjusted_mode); - return (scanline + vtotal - crtc->scanline_offset) % vtotal; + return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal; } /* diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h index 7e526f6861e4..45a4a961aaab 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.h +++ b/drivers/gpu/drm/i915/display/intel_vblank.h @@ -40,6 +40,7 @@ void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc); void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc); void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state, bool vrr_enable); -int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline); +int intel_crtc_scanline_to_hw(const struct intel_crtc_state *crtc_state, + int scanline); #endif /* __INTEL_VBLANK_H__ */ From patchwork Mon Jun 24 19:10:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13709978 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38D05C2D0D1 for ; Mon, 24 Jun 2024 19:11:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7049010E55F; Mon, 24 Jun 2024 19:11:01 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ZAcS3OKo"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id A524E10E54D for ; Mon, 24 Jun 2024 19:11:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719256260; x=1750792260; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=TNplp1OY6uhMrJdTrr5eYNlGGY9E0NEVUJjh3wo2Urs=; b=ZAcS3OKoQ+JKvE2RrBVn72yYJwPRYPo3WdPU3QqWHUlKb6Wpeca85bGD xXyf/DqnYLhbaLOXGvvAf3UGDZqvV8WWagelj1mJLJG8Lu3Ls0eiW2/x9 UD382O/bn18/zq96p4teNTgzG5ojh1S8dXXs/2FdGOxJfRW4n834XRgtJ D6IdxIX7BfyQolI6vYFIbrHDlwL8+ksYEQ62ftq3YPX9w1zfpb3h9mCBG PJw/WziQzwtng2eUirXU7eMuyJjGH9F3HQc9jwEsFpv3HRWMnJkxpV73d 8pru+2mpE5yJSxEKJm1OW8e2u0e1c6f8ws748U4V64XWUk9gJTArvUP/R w==; X-CSE-ConnectionGUID: Q+wh6QQWR/SCfrlVzN0GpA== X-CSE-MsgGUID: YtVYMxupTiCo7U2S98xtFg== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16374176" X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="16374176" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2024 12:10:49 -0700 X-CSE-ConnectionGUID: JTelRLmxRGWSsxi/N+IJGg== X-CSE-MsgGUID: 8IKuRo5GRg+0D0861OkSZA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="43371950" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jun 2024 12:10:47 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 24 Jun 2024 22:10:47 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 05/14] drm/i915/dsb: Shuffle code around Date: Mon, 24 Jun 2024 22:10:23 +0300 Message-ID: <20240624191032.27333-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240624191032.27333-1-ville.syrjala@linux.intel.com> References: <20240624191032.27333-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Relocate intel_dsb_dewake_scanline() and dsb_chicken() upwards in the file. I need to reuse these while emitting DSB commands, and I'd like to keep the DSB command emission stuff more or less grouped together in the file. Also drop the intel_ prefix from intel_dsb_dewake_scanline() since it's all internal stuff and thus doesn't need so much namespacing. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 56 ++++++++++++------------ 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index cee33c66a26b..d3e5e5263603 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -83,6 +83,33 @@ struct intel_dsb { #define DSB_OPCODE_POLL 0xA /* see DSB_REG_VALUE_MASK */ +static int dsb_dewake_scanline(const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + unsigned int latency = skl_watermark_max_latency(i915, 0); + int vblank_start; + + if (crtc_state->vrr.enable) + vblank_start = intel_vrr_vmin_vblank_start(crtc_state); + else + vblank_start = intel_mode_vblank_start(adjusted_mode); + + return max(0, vblank_start - intel_usecs_to_scanlines(adjusted_mode, latency)); +} + +static u32 dsb_chicken(struct intel_crtc *crtc) +{ + if (crtc->mode_flags & I915_MODE_FLAG_VRR) + return DSB_SKIP_WAITS_EN | + DSB_CTRL_WAIT_SAFE_WINDOW | + DSB_CTRL_NO_WAIT_VBLANK | + DSB_INST_WAIT_SAFE_WINDOW | + DSB_INST_NO_WAIT_VBLANK; + else + return DSB_SKIP_WAITS_EN; +} + static bool assert_dsb_has_room(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; @@ -313,33 +340,6 @@ void intel_dsb_finish(struct intel_dsb *dsb) intel_dsb_buffer_flush_map(&dsb->dsb_buf); } -static int intel_dsb_dewake_scanline(const struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - unsigned int latency = skl_watermark_max_latency(i915, 0); - int vblank_start; - - if (crtc_state->vrr.enable) - vblank_start = intel_vrr_vmin_vblank_start(crtc_state); - else - vblank_start = intel_mode_vblank_start(adjusted_mode); - - return max(0, vblank_start - intel_usecs_to_scanlines(adjusted_mode, latency)); -} - -static u32 dsb_chicken(struct intel_crtc *crtc) -{ - if (crtc->mode_flags & I915_MODE_FLAG_VRR) - return DSB_SKIP_WAITS_EN | - DSB_CTRL_WAIT_SAFE_WINDOW | - DSB_CTRL_NO_WAIT_VBLANK | - DSB_INST_WAIT_SAFE_WINDOW | - DSB_INST_NO_WAIT_VBLANK; - else - return DSB_SKIP_WAITS_EN; -} - static u32 dsb_error_int_status(struct intel_display *display) { struct drm_i915_private *i915 = to_i915(display->drm); @@ -532,7 +532,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, dsb->ins_start_offset = 0; dsb->hw_dewake_scanline = - intel_crtc_scanline_to_hw(crtc_state, intel_dsb_dewake_scanline(crtc_state)); + intel_crtc_scanline_to_hw(crtc_state, dsb_dewake_scanline(crtc_state)); return dsb; From patchwork Mon Jun 24 19:10:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13709982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9A75C30653 for ; Mon, 24 Jun 2024 19:11:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A97810E563; Mon, 24 Jun 2024 19:11:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ihcTFZPU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id E94DB10E54D for ; Mon, 24 Jun 2024 19:11:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719256261; x=1750792261; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=d5d0tr7n9ChamjmzG+RW0yZXrTZwWzwnhBh1H5KMAF8=; b=ihcTFZPU+dNAjz8ceMMua0AQGbfIJEh2VGEct2nnCnIimlJ9oM+axPbg LrsLj5EWXKOJ9IXzbGzvrDzBwVLrEconTrztJxwgbR22XIAnmRc3g0GzK MsAikQlc7HqtiEGqbPbz5Up7GwyDB66bG2b1j4dABX8NqSiocxcgKaGwA PDiFBSiUAa/gFxe6VzTBbPNepwsU7ffLSsARFFm80N5RkjQnTvEdfbkxB LAt86bkMakM1iMZojDOi1ex+Jpp+74n9uUXJqYpJXvT+HcWqkL1Jyz/B9 9Xc7gCa6Qy+7OAwFyQLJoJzruF61dRUSZivo/A2MKSAVgeOBWZUgrPj2d g==; X-CSE-ConnectionGUID: SJtA/jQITemw1vnex4N1Ag== X-CSE-MsgGUID: 1/xFITpoRh246zfzI5IHUQ== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16374183" X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="16374183" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2024 12:10:52 -0700 X-CSE-ConnectionGUID: 1yUhgovNQ+Gg5mQVIbcpEA== X-CSE-MsgGUID: hDtO53zMQoqiKZiDRFxYEQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="43371952" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jun 2024 12:10:50 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 24 Jun 2024 22:10:49 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 06/14] drm/i915/dsb: Fix dewake scanline Date: Mon, 24 Jun 2024 22:10:24 +0300 Message-ID: <20240624191032.27333-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240624191032.27333-1-ville.syrjala@linux.intel.com> References: <20240624191032.27333-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Currently we calculate the DEwake scanline based on the delayed vblank start, while in reality it should be computed based on the undelayed vblank start (as that is where the DSB actually starts). Currently it doesn't really matter as we don't have any vblank delay configured, but that may change in the future so let's be accurate in what we do. We can also remove the max() as intel_crtc_scanline_to_hw() can deal with negative numbers, which there really shouldn't be anyway. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index d3e5e5263603..e871af5517b5 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -86,16 +86,10 @@ struct intel_dsb { static int dsb_dewake_scanline(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; unsigned int latency = skl_watermark_max_latency(i915, 0); - int vblank_start; - if (crtc_state->vrr.enable) - vblank_start = intel_vrr_vmin_vblank_start(crtc_state); - else - vblank_start = intel_mode_vblank_start(adjusted_mode); - - return max(0, vblank_start - intel_usecs_to_scanlines(adjusted_mode, latency)); + return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode) - + intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, latency); } static u32 dsb_chicken(struct intel_crtc *crtc) From patchwork Mon Jun 24 19:10:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13709980 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A79AC2D0D1 for ; Mon, 24 Jun 2024 19:11:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D509710E560; Mon, 24 Jun 2024 19:11:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="G7FNjgjk"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2AD8310E55F for ; Mon, 24 Jun 2024 19:11:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719256261; x=1750792261; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=rfpMxVZbfsiy3Tl/htCeBysVjM2rYFKFIgDt4nfCbyU=; b=G7FNjgjkP1J9R3KaeimAjxBzHjeaTkVEaBJeh8p5b2rfa3JGezQGTkva qowrdfVy7VZ5iq+9qW3kWsteuVePInz2TqflaFw0BQCNFK3MW7ZovlB9x MeOXqwqqGI/N6kRegmBnWV7Hwm2qSiQmYuTvqXA4zBIWzMEESPLUYEHYv 83mBdVdbrRhTfWxihebRb6Q9HT0RlzqD6JsDYX6YJH927L88kW5Bth9qx Mvv+sqi3ahpUOqPEe9BvdXqveHvQOUwDeh3OMYjR6gIt0uGpYirgsTmLC VGaj4wBWOuL4s4W70By7SDDIW54Yrlm/3mTQckUOHanJ9YdJwyr3n+IOy Q==; X-CSE-ConnectionGUID: 0vSdyceGRZ6n+NdUp6bK6w== X-CSE-MsgGUID: 9CBFPug6TACnPLG+GOLE8A== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16374192" X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="16374192" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2024 12:10:55 -0700 X-CSE-ConnectionGUID: qYu0mYkITI2NRBSAPDYh2A== X-CSE-MsgGUID: nSM2zkzvRh2khKEu8IhDyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="43371964" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jun 2024 12:10:53 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 24 Jun 2024 22:10:52 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 07/14] drm/i915/dsb: Account for VRR properly in DSB scanline stuff Date: Mon, 24 Jun 2024 22:10:25 +0300 Message-ID: <20240624191032.27333-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240624191032.27333-1-ville.syrjala@linux.intel.com> References: <20240624191032.27333-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä When determining various scanlines for DSB use we should take into account whether VRR is active at the time when the DSB uses said scanline information. For now all DSB scanline usage occurs prior to the actual commit, so we only need to care about the state of VRR at that time. I've decided to move intel_crtc_scanline_to_hw() in its entirety to the DSB code as it will also need to know the actual state of VRR in order to do its job 100% correctly. TODO: figure out how much of this could be moved to some more generic place and perhaps be shared with the CPU vblank evasion code/etc... Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 +- drivers/gpu/drm/i915/display/intel_display.h | 3 + drivers/gpu/drm/i915/display/intel_dsb.c | 65 ++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_vblank.c | 10 +-- drivers/gpu/drm/i915/display/intel_vblank.h | 3 +- 5 files changed, 67 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 01a5faa3fea5..592483651b3c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1031,8 +1031,8 @@ static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state, vrr_params_changed(old_crtc_state, new_crtc_state))); } -static bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, - struct intel_crtc *crtc) +bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, + struct intel_crtc *crtc) { const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index b0cf6ca70952..b21d9578d5db 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -532,6 +532,9 @@ void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state); void intel_update_watermarks(struct drm_i915_private *i915); +bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, + struct intel_crtc *crtc); + /* modesetting */ int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, const char *reason, u8 pipe_mask); diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index e871af5517b5..b362a3050c7f 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -83,15 +83,72 @@ struct intel_dsb { #define DSB_OPCODE_POLL 0xA /* see DSB_REG_VALUE_MASK */ -static int dsb_dewake_scanline(const struct intel_crtc_state *crtc_state) +static bool pre_commit_is_vrr_active(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + + /* VRR will be enabled afterwards, if necessary */ + if (intel_crtc_needs_modeset(new_crtc_state)) + return false; + + /* VRR will have been disabled during intel_pre_plane_update() */ + return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, crtc); +} + +static const struct intel_crtc_state * +pre_commit_crtc_state(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + + /* + * During fastsets/etc. the transcoder is still + * running with the old timings at this point. + */ + if (intel_crtc_needs_modeset(new_crtc_state)) + return new_crtc_state; + else + return old_crtc_state; +} + +static int dsb_vtotal(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); + + if (pre_commit_is_vrr_active(state, crtc)) + return crtc_state->vrr.vmax; + else + return intel_mode_vtotal(&crtc_state->hw.adjusted_mode); +} + +static int dsb_dewake_scanline(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); + struct drm_i915_private *i915 = to_i915(state->base.dev); unsigned int latency = skl_watermark_max_latency(i915, 0); return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode) - intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, latency); } +static int dsb_scanline_to_hw(struct intel_atomic_state *state, + struct intel_crtc *crtc, int scanline) +{ + const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); + int vtotal = dsb_vtotal(state, crtc); + + return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal; +} + static u32 dsb_chicken(struct intel_crtc *crtc) { if (crtc->mode_flags & I915_MODE_FLAG_VRR) @@ -489,8 +546,6 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, unsigned int max_cmds) { struct drm_i915_private *i915 = to_i915(state->base.dev); - const struct intel_crtc_state *crtc_state = - intel_atomic_get_new_crtc_state(state, crtc); intel_wakeref_t wakeref; struct intel_dsb *dsb; unsigned int size; @@ -526,7 +581,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, dsb->ins_start_offset = 0; dsb->hw_dewake_scanline = - intel_crtc_scanline_to_hw(crtc_state, dsb_dewake_scanline(crtc_state)); + dsb_scanline_to_hw(state, crtc, dsb_dewake_scanline(state, crtc)); return dsb; diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 56c8033eec4c..71abc7354c3b 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -190,7 +190,7 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) return scanline; } -static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state) +int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); @@ -284,14 +284,6 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) return (position + vtotal + crtc->scanline_offset) % vtotal; } -int intel_crtc_scanline_to_hw(const struct intel_crtc_state *crtc_state, - int scanline) -{ - int vtotal = intel_mode_vtotal(&crtc_state->hw.adjusted_mode); - - return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal; -} - /* * The uncore version of the spin lock functions is used to decide * whether we need to lock the uncore lock or not. This is only diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h index 45a4a961aaab..6d7336256982 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.h +++ b/drivers/gpu/drm/i915/display/intel_vblank.h @@ -40,7 +40,6 @@ void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc); void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc); void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state, bool vrr_enable); -int intel_crtc_scanline_to_hw(const struct intel_crtc_state *crtc_state, - int scanline); +int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VBLANK_H__ */ From patchwork Mon Jun 24 19:10:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13709981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 481F4C2BD09 for ; Mon, 24 Jun 2024 19:11:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6F06910E562; Mon, 24 Jun 2024 19:11:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MMUfCI+3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6A25A10E54D for ; Mon, 24 Jun 2024 19:11:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719256261; x=1750792261; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=0RPY5F20KfoXzQFkiGusMSMUEJTTEnuMF4mf+BkDkg8=; b=MMUfCI+3JeEV/25ybN1wMQp9HU4QdOHPI7/Pe+eoQ/ZimoF/MTXp1cn+ Y2FhFhXTU2lSrxM6rYawurOpicCUm3CaIbTQkDP3QaBg39hsd2pnBJQhb +BE/I0Ic9a4sgdFXWLn/GO8PGhcaiS8NROy2MKWh35A1T2BQFGCWnPORz g+KTvrtsGuO6GG0jdr9tCvc5hF41QIx0YvAxgrHwI82X1bClRtZryM4no epLxdxkIZeFBh67W6wdz7U19ixojEZZcVXPM0vjPDFMHoNaPCoEMcFX/v fakgBrh/40CyMQyoOEaBp80g1F0BqkmGMuGvBGYhTxpL7CFKvE52Bq3at Q==; X-CSE-ConnectionGUID: r+gallCxTR2HlCEdI6g/lQ== X-CSE-MsgGUID: +CLTNl+jSgudbPfLTqpxSQ== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16374197" X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="16374197" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2024 12:10:58 -0700 X-CSE-ConnectionGUID: 3cT9TZYmTL+oclX84ZQqaA== X-CSE-MsgGUID: Wzel9H/MS32FWueH8HEQhQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="43371974" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jun 2024 12:10:56 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 24 Jun 2024 22:10:55 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 08/14] drm/i915/dsb: Precompute DSB_CHICKEN Date: Mon, 24 Jun 2024 22:10:26 +0300 Message-ID: <20240624191032.27333-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240624191032.27333-1-ville.syrjala@linux.intel.com> References: <20240624191032.27333-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Adjust the code that determines the correct DSB_CHICKEN value to be usable for use within DSB commands themselves. Ie. precompute it based on our knowledge of what the hardware state (VRR vs. not mainly) will be at the time of the commit. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index b362a3050c7f..81937908c798 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -43,6 +43,7 @@ struct intel_dsb { */ unsigned int ins_start_offset; + u32 chicken; int hw_dewake_scanline; }; @@ -149,9 +150,10 @@ static int dsb_scanline_to_hw(struct intel_atomic_state *state, return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal; } -static u32 dsb_chicken(struct intel_crtc *crtc) +static u32 dsb_chicken(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - if (crtc->mode_flags & I915_MODE_FLAG_VRR) + if (pre_commit_is_vrr_active(state, crtc)) return DSB_SKIP_WAITS_EN | DSB_CTRL_WAIT_SAFE_WINDOW | DSB_CTRL_NO_WAIT_VBLANK | @@ -449,7 +451,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, ctrl | DSB_ENABLE); intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id), - dsb_chicken(crtc)); + dsb->chicken); intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id), dsb_error_int_status(display) | DSB_PROG_INT_STATUS | @@ -580,6 +582,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, dsb->free_pos = 0; dsb->ins_start_offset = 0; + dsb->chicken = dsb_chicken(state, crtc); dsb->hw_dewake_scanline = dsb_scanline_to_hw(state, crtc, dsb_dewake_scanline(state, crtc)); From patchwork Mon Jun 24 19:10:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13709983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B793EC2D0D1 for ; Mon, 24 Jun 2024 19:11:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A9B510E565; Mon, 24 Jun 2024 19:11:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kWb8jyeJ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id B934210E561 for ; Mon, 24 Jun 2024 19:11:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719256261; x=1750792261; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ynqI+z+wdo/aBIaoCKqR1wRelbGjrvD+tuFW0wcPotM=; b=kWb8jyeJiLLVbsS1oQYDfctzl5WaotjK8ICpDALIeppyzQ4x1gIcJcoG SvFC5mVKxt37OTuej0HdC8w5kPKnxLGzSIx6CrqCn2ykGwvJ3Hmv8Q3G+ fVIsNBzmscJrrj7kHpzxm+VLI5c1Y1maiZXQO+vDmfvPbh5IXeWW9hUBO dbUWktI70aSwlAEgvNQOv31F4gJIEb22qXeVONOk9YtiF3KSdSKxIIy2P rpKbFMsOeIc8kMHxdODp8w3gfx1onIumyuihSLjkIEwgIOdsisw+1CwAA sTfqtAmihb56AvoUPhZXhKymxKYMlmv3F+oF4MMDXDagbKuJ6+PDT5d/H w==; X-CSE-ConnectionGUID: LhWK5L0WRVaMW1uFyhDGlQ== X-CSE-MsgGUID: GnevOihOQOCoMl0W9fVMsg== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16374206" X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="16374206" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2024 12:11:00 -0700 X-CSE-ConnectionGUID: pcHIS77JQLqZPFuEH5VFMQ== X-CSE-MsgGUID: PyTFROnwQ7mtDOfQE1rLKg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="43371979" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jun 2024 12:10:58 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 24 Jun 2024 22:10:58 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 09/14] drm/i915/dsb: Introduce intel_dsb_wait_scanline_{in, out}() Date: Mon, 24 Jun 2024 22:10:27 +0300 Message-ID: <20240624191032.27333-10-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240624191032.27333-1-ville.syrjala@linux.intel.com> References: <20240624191032.27333-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Add functions to emit a DSB scanline window wait instructions. We can either wait for the scanline to be IN the window or OUT of the window. The hardware doesn't handle wraparound so we must manually deal with it by swapping the IN range to the inverse OUT range, or vice versa. Also add a bit of paranoia to catch the edge case of waiting for the entire frame. That doesn't make sense since an IN wait would be a nop, and an OUT wait would imply waiting forever. Most of the time this also results in both scanline ranges (original and inverted) to have lower=upper+1 which is nonsense from the hw POV. For now we are only handling the case where the scanline wait happens prior to latching the double buffered registers during the commit (which might change the timings due to LRR/VRR/etc.) Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 73 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dsb.h | 6 ++ 2 files changed, 79 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 81937908c798..092cf082ac39 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -362,6 +362,79 @@ void intel_dsb_nonpost_end(struct intel_dsb *dsb) intel_dsb_noop(dsb, 4); } +static void intel_dsb_emit_wait_dsl(struct intel_dsb *dsb, + u32 opcode, int lower, int upper) +{ + u64 window = ((u64)upper << DSB_SCANLINE_UPPER_SHIFT) | + ((u64)lower << DSB_SCANLINE_LOWER_SHIFT); + + intel_dsb_emit(dsb, lower_32_bits(window), + (opcode << DSB_OPCODE_SHIFT) | + upper_32_bits(window)); +} + +static void intel_dsb_wait_dsl(struct intel_atomic_state *state, + struct intel_dsb *dsb, + int lower_in, int upper_in, + int lower_out, int upper_out) +{ + struct intel_crtc *crtc = dsb->crtc; + + lower_in = dsb_scanline_to_hw(state, crtc, lower_in); + upper_in = dsb_scanline_to_hw(state, crtc, upper_in); + + lower_out = dsb_scanline_to_hw(state, crtc, lower_out); + upper_out = dsb_scanline_to_hw(state, crtc, upper_out); + + if (upper_in >= lower_in) + intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_IN, + lower_in, upper_in); + else if (upper_out >= lower_out) + intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, + lower_out, upper_out); + else + drm_WARN_ON(crtc->base.dev, 1); /* assert_dsl_ok() should have caught it already */ +} + +static void assert_dsl_ok(struct intel_atomic_state *state, + struct intel_dsb *dsb, + int start, int end) +{ + struct intel_crtc *crtc = dsb->crtc; + int vtotal = dsb_vtotal(state, crtc); + + /* + * Waiting for the entire frame doesn't make sense, + * (IN==don't wait, OUT=wait forever). + */ + drm_WARN(crtc->base.dev, (end - start + vtotal) % vtotal == vtotal - 1, + "[CRTC:%d:%s] DSB %d bad scanline window wait: %d-%d (vt=%d)\n", + crtc->base.base.id, crtc->base.name, dsb->id, + start, end, vtotal); +} + +void intel_dsb_wait_scanline_in(struct intel_atomic_state *state, + struct intel_dsb *dsb, + int start, int end) +{ + assert_dsl_ok(state, dsb, start, end); + + intel_dsb_wait_dsl(state, dsb, + start, end, + end + 1, start - 1); +} + +void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, + struct intel_dsb *dsb, + int start, int end) +{ + assert_dsl_ok(state, dsb, start, end); + + intel_dsb_wait_dsl(state, dsb, + end + 1, start - 1, + start, end); +} + static void intel_dsb_align_tail(struct intel_dsb *dsb) { u32 aligned_tail, tail; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index 84fc2f8434d1..d0737cefb393 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -39,6 +39,12 @@ void intel_dsb_reg_write_masked(struct intel_dsb *dsb, void intel_dsb_noop(struct intel_dsb *dsb, int count); void intel_dsb_nonpost_start(struct intel_dsb *dsb); void intel_dsb_nonpost_end(struct intel_dsb *dsb); +void intel_dsb_wait_scanline_in(struct intel_atomic_state *state, + struct intel_dsb *dsb, + int lower, int upper); +void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, + struct intel_dsb *dsb, + int lower, int upper); void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank); From patchwork Mon Jun 24 19:10:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13709987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF964C30653 for ; Mon, 24 Jun 2024 19:11:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E813610E568; Mon, 24 Jun 2024 19:11:16 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="AJGYFQX0"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id B84C710E55A for ; Mon, 24 Jun 2024 19:11:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719256263; x=1750792263; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=lRIczeG+eZlcCjWqMkiHeZpeMNw13K+qD/9uFRiFsjc=; b=AJGYFQX09IFDcSoYlCOwB+Ht4rwiUwvWu8uU7X1esimMv+n4+hV6Th1l GJ69MaFGjt74awT4WrZi2UN0Cu1gLst4EZHD+U5rNDSm7+H+1HGGyJDOh fss+4sDpd640fyeVsXl931WS9lxyZBDAC8QYLKPaKRxgV0w/hXgnIWRTj q6wyxOmISnH5bRWfq/YOcpQmZlB6+L2oQ/A/4YC4mU9w3GwPsH/jaCv3p uDLy5eyuJRiE8O5xWhTZwrKWewObMTKCRbTV1tlJ6TtqKXUWot7ZUnr1T W+Qz35QftNQXo0JYneTzBB/A43msqdVENMxMFdvJKK8PwnCdaB94WYh/J Q==; X-CSE-ConnectionGUID: 8U5fK/ZnQwKBQgzMbL98rA== X-CSE-MsgGUID: 2rjKMc0bSwKDdXwB9ZijCw== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16374212" X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="16374212" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2024 12:11:03 -0700 X-CSE-ConnectionGUID: /AcrrhfiTICkGycq+ea/WA== X-CSE-MsgGUID: bhwfXNUeRwevSrgojgltvQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="43371983" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jun 2024 12:11:01 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 24 Jun 2024 22:11:00 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 10/14] drm/i915/dsb: Introduce intel_dsb_chain() Date: Mon, 24 Jun 2024 22:10:28 +0300 Message-ID: <20240624191032.27333-11-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240624191032.27333-1-ville.syrjala@linux.intel.com> References: <20240624191032.27333-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä In order to handle the DEwake tricks without involving the CPU we need a mechanism by which one DSB can start another one. Add a basic function to do so. We'll extend it later with additional code to actually deal with DEwake. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 42 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dsb.h | 3 ++ 2 files changed, 45 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 092cf082ac39..4c0519c41f16 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -502,6 +502,48 @@ static u32 dsb_error_int_en(struct intel_display *display) return errors; } +static void _intel_dsb_chain(struct intel_atomic_state *state, + struct intel_dsb *dsb, + struct intel_dsb *chained_dsb, + u32 ctrl) +{ + struct intel_display *display = to_intel_display(state->base.dev); + struct intel_crtc *crtc = dsb->crtc; + enum pipe pipe = crtc->pipe; + u32 tail; + + if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id)) + return; + + tail = chained_dsb->free_pos * 4; + if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) + return; + + intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id), + ctrl | DSB_ENABLE); + + intel_dsb_reg_write(dsb, DSB_CHICKEN(pipe, chained_dsb->id), + dsb_chicken(state, crtc)); + + intel_dsb_reg_write(dsb, DSB_INTERRUPT(pipe, chained_dsb->id), + dsb_error_int_status(display) | DSB_PROG_INT_STATUS | + dsb_error_int_en(display)); + + intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id), + intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf)); + + intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id), + intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf) + tail); +} + +void intel_dsb_chain(struct intel_atomic_state *state, + struct intel_dsb *dsb, + struct intel_dsb *chained_dsb) +{ + _intel_dsb_chain(state, dsb, chained_dsb, + 0); +} + static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, int hw_dewake_scanline) { diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index d0737cefb393..e59fd7da0fc0 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -45,6 +45,9 @@ void intel_dsb_wait_scanline_in(struct intel_atomic_state *state, void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, struct intel_dsb *dsb, int lower, int upper); +void intel_dsb_chain(struct intel_atomic_state *state, + struct intel_dsb *dsb, + struct intel_dsb *chained_dsb); void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank); From patchwork Mon Jun 24 19:10:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13709984 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9A29BC3065A for ; Mon, 24 Jun 2024 19:11:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CB5AF10E567; Mon, 24 Jun 2024 19:11:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="SiT+GxMV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6CBBF10E55A for ; Mon, 24 Jun 2024 19:11:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719256266; x=1750792266; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=AHOla9D94d/8H3tkkUzBIgwyf4afBeVnOpUvxJ9HnIY=; b=SiT+GxMVOodItvR0w2FrRd3amZjsMxo19x39IBuF2E6yNLENEhGDyUyP K1LWarMV4gWqHAivqDG3Pp3RPZmphqXbQC7CjVZoqmfAusGFjWMZs4kP5 OjWSUomcFpF6Rd6mW103jfupyZ8er3QhE+v6WXCssID0A5/+6XD59BjEr Xf7yus8JGslj/gvhZHnohV61JmeV6hYgeJtZvbYk60CStrB8xOyB+plKn /njDJ5Pi/av6JvHaWkT1v8fJTxZez9rXsPpExO20uuYCclIq+VbqlF8hA Ux93mjUMhpFEk/m1KjPYew454PG1pwROWalafPzwOWiA9kDah4RfVKSgf A==; X-CSE-ConnectionGUID: mkVeZjkDT76M+dj6ef7eTw== X-CSE-MsgGUID: Jrotvg6fTMmy/utF/pEaNA== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16374223" X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="16374223" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2024 12:11:06 -0700 X-CSE-ConnectionGUID: G3DSymlKSZWNbLhFkzb5vQ== X-CSE-MsgGUID: 5HtMrtLARrC+qtcKLRH9mQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="43371994" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jun 2024 12:11:04 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 24 Jun 2024 22:11:03 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 11/14] drm/i915/dsb: Allow intel_dsb_chain() to use DSB_WAIT_FOR_VBLANK Date: Mon, 24 Jun 2024 22:10:29 +0300 Message-ID: <20240624191032.27333-12-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240624191032.27333-1-ville.syrjala@linux.intel.com> References: <20240624191032.27333-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Allow intel_dsb_chain() to start the chained DSB at start of the undelaye vblank. This is slightly more involved than simply setting the bit as we must use the DEwake mechanism to eliminate pkgC latency. And DSB_ENABLE_DEWAKE itself is problematic in that it allows us to configure just a single scanline, and if the current scanline is already past that DSB_ENABLE_DEWAKE won't do anything, rendering the whole thing moot. The current workaround involves checking the pipe's current scanline with the CPU, and if it looks like we're about to miss the configured DEwake scanline we set DSB_FORCE_DEWAKE to immediately assert DEwake. This is somewhat racy since the hardware is making progress all the while we're checking it on the CPU. We can make things less racy by chaining two DSBs and handling the DSB_FORCE_DEWAKE stuff entirely without CPU involvement: 1. CPU starts the first DSB immediately 2. First DSB configures the second DSB, including its dewake_scanline 3. First DSB starts the second w/ DSB_WAIT_FOR_VBLANK 4. First DSB asserts DSB_FORCE_DEWAKE 5. First DSB waits until we're outside the dewake_scanline-vblank_start window 6. First DSB deasserts DSB_FORCE_DEWAKE That will guarantee that the we are fully awake when the second DSB starts to actually execute. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 43 +++++++++++++++++++++--- drivers/gpu/drm/i915/display/intel_dsb.h | 3 +- 2 files changed, 40 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 4c0519c41f16..cf710f0bf430 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -130,8 +130,8 @@ static int dsb_vtotal(struct intel_atomic_state *state, return intel_mode_vtotal(&crtc_state->hw.adjusted_mode); } -static int dsb_dewake_scanline(struct intel_atomic_state *state, - struct intel_crtc *crtc) +static int dsb_dewake_scanline_start(struct intel_atomic_state *state, + struct intel_crtc *crtc) { const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); struct drm_i915_private *i915 = to_i915(state->base.dev); @@ -141,6 +141,14 @@ static int dsb_dewake_scanline(struct intel_atomic_state *state, intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, latency); } +static int dsb_dewake_scanline_end(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); + + return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode); +} + static int dsb_scanline_to_hw(struct intel_atomic_state *state, struct intel_crtc *crtc, int scanline) { @@ -529,19 +537,44 @@ static void _intel_dsb_chain(struct intel_atomic_state *state, dsb_error_int_status(display) | DSB_PROG_INT_STATUS | dsb_error_int_en(display)); + if (ctrl & DSB_WAIT_FOR_VBLANK) { + int dewake_scanline = dsb_dewake_scanline_start(state, crtc); + int hw_dewake_scanline = dsb_scanline_to_hw(state, crtc, dewake_scanline); + + intel_dsb_reg_write(dsb, DSB_PMCTRL(pipe, chained_dsb->id), + DSB_ENABLE_DEWAKE | + DSB_SCANLINE_FOR_DEWAKE(hw_dewake_scanline)); + } + intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id), intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf)); intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id), intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf) + tail); + + if (ctrl & DSB_WAIT_FOR_VBLANK) { + /* + * Keep DEwake alive via the first DSB, in + * case we're already past dewake_scanline, + * and thus DSB_ENABLE_DEWAKE on the second + * DSB won't do its job. + */ + intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(pipe, dsb->id), + DSB_FORCE_DEWAKE, DSB_FORCE_DEWAKE); + + intel_dsb_wait_scanline_out(state, dsb, + dsb_dewake_scanline_start(state, crtc), + dsb_dewake_scanline_end(state, crtc)); + } } void intel_dsb_chain(struct intel_atomic_state *state, struct intel_dsb *dsb, - struct intel_dsb *chained_dsb) + struct intel_dsb *chained_dsb, + bool wait_for_vblank) { _intel_dsb_chain(state, dsb, chained_dsb, - 0); + wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0); } static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, @@ -699,7 +732,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, dsb->chicken = dsb_chicken(state, crtc); dsb->hw_dewake_scanline = - dsb_scanline_to_hw(state, crtc, dsb_dewake_scanline(state, crtc)); + dsb_scanline_to_hw(state, crtc, dsb_dewake_scanline_start(state, crtc)); return dsb; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index e59fd7da0fc0..c352c12aa59f 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -47,7 +47,8 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, int lower, int upper); void intel_dsb_chain(struct intel_atomic_state *state, struct intel_dsb *dsb, - struct intel_dsb *chained_dsb); + struct intel_dsb *chained_dsb, + bool wait_for_vblank); void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank); From patchwork Mon Jun 24 19:10:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13709985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9FB16C2BD09 for ; Mon, 24 Jun 2024 19:11:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B8F3510E566; Mon, 24 Jun 2024 19:11:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MPFtgg+N"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 35E4F10E563 for ; Mon, 24 Jun 2024 19:11:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719256269; x=1750792269; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=OQ5yMDj0ugWseqbk3T5EdTP6ry87kkQOzzwQn+P6Kn0=; b=MPFtgg+NgsbM0/ENs5gtSjFlxmw2QGS1wrP8gM5j0R83pTShYFRAZBf7 dn5gEgPH0TmmnmcW+qfI8miQqceFjn+5b6XQDJpQpfjVgJ7qOvQSVn9Co j4DI3NXzcctfO5oEjn/hOuBWtsizEr9GBF0Mj44ZQaCIxRcKSvZ81zKDf 5ChkvnYvSv5VCFEmxKjen5t2FHz0XAmRcm/9boDgVBQ1tQFl2X4Zyn674 h33e4YwY7MXmeSBu1PadHMnpQJ8osMBOYsPiUJqCiDTUv+d7vCXP8JKx5 Fa/z6znQNKYHuHnj+PDQyoSeWUeZtCY9KYskL1YbSNsL+5a9ZsXCbGp0V g==; X-CSE-ConnectionGUID: L1CpGj0qTyyuKA4/OFfYbw== X-CSE-MsgGUID: 7LE6b//lQomywKDMouejYg== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16374226" X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="16374226" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2024 12:11:09 -0700 X-CSE-ConnectionGUID: vvDV41kzTBWCsUPSu3pKBg== X-CSE-MsgGUID: fyrZvXKMRh2TMNk+YT5ugA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="43372000" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jun 2024 12:11:07 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 24 Jun 2024 22:11:06 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 12/14] drm/i915/dsb: Clear DSB_ENABLE_DEWAKE once the DSB is done Date: Mon, 24 Jun 2024 22:10:30 +0300 Message-ID: <20240624191032.27333-13-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240624191032.27333-1-ville.syrjala@linux.intel.com> References: <20240624191032.27333-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä In order to avoid the DSB keeping the DEwake permanently asserted we must clear DSB_PMCTRL_2.DSB_FORCE_DEWAKE once we are done. For good measure do the same for DSB_PMCTRL.DSB_ENABLE_DEWAKE. Experimentally this doens't seem to be actually necessary (unlike with DSB_FORCE_DEWAKE). That is, the DSB_ENABLE_DEWAKE doesn't seem to do anything whenever the DSB is not active. But I'd hate to waste a ton of power in case there I'm wrong and there is some way DEwake could remaing asserted. One extra register write is a small price to pay for some peace of mind. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index cf710f0bf430..fad37e7856b1 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -464,8 +464,10 @@ void intel_dsb_finish(struct intel_dsb *dsb) /* * DSB_FORCE_DEWAKE remains active even after DSB is * disabled, so make sure to clear it (if set during - * intel_dsb_commit()). + * intel_dsb_commit()). And clear DSB_ENABLE_DEWAKE as + * well for good measure. */ + intel_dsb_reg_write(dsb, DSB_PMCTRL(crtc->pipe, dsb->id), 0); intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id), DSB_FORCE_DEWAKE, 0); From patchwork Mon Jun 24 19:10:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13709986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25B7CC2BD09 for ; Mon, 24 Jun 2024 19:11:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E5F710E55A; Mon, 24 Jun 2024 19:11:16 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Xo+RLCDE"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 040A210E55A for ; Mon, 24 Jun 2024 19:11:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719256272; x=1750792272; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=i4aXizVjGhr/gqnJUEAIAJkZKqffxmgITuMbARbPlV8=; b=Xo+RLCDEoNZ1d4SpeetG5wcJ7yqB40sZWnXIESU7+g7h09ca64PYId97 3HWJ39T+HIGitu9Aw04z76sY31TAF2gfBcM3EbtAqAOPcj01Al2WorpQC i15m2x3/tunnxus+daSDgauKuEDaSmWdroCXg9PL+FkMrq+oXTWEwbp2R sbecxO43VpfnaYDq9NRsC87jM29X2AGjqgT51uiLoeNGC1TzLmf86IUT6 lN7R712QzL8ajabGIULpBNKVSZwMlAeCVvOTMvX+GR80ugdXYC4mspvgC ufQQ8Odxr6GF1B2sWntFlqPoQuYVAPLRUmVy1rGM7NzChCHChEdPFozT5 Q==; X-CSE-ConnectionGUID: pkKRdNIUTT2DyBqs3wT6ow== X-CSE-MsgGUID: f28PMUnPTiyY3WAc6Abhyw== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16374230" X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="16374230" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2024 12:11:11 -0700 X-CSE-ConnectionGUID: sDTwthYgTvyUaJ73nwjXRQ== X-CSE-MsgGUID: khrtXSXvTNuCa8Qx/2HasQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="43372004" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jun 2024 12:11:09 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 24 Jun 2024 22:11:09 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 13/14] drm/i915/dsb: s/dsb/dsb_color_vblank/ Date: Mon, 24 Jun 2024 22:10:31 +0300 Message-ID: <20240624191032.27333-14-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240624191032.27333-1-ville.syrjala@linux.intel.com> References: <20240624191032.27333-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We'll soon utilize several DSBs during the commit. To that end rename the current crtc_state->dsb to crtc_state->dsb_color_vblank to better reflect its role (color managemnent stuff programmed during vblank). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_atomic.c | 4 +-- drivers/gpu/drm/i915/display/intel_color.c | 36 +++++++++---------- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_types.h | 4 +-- 4 files changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index 76aa10b6f647..55ce71be41ec 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -276,7 +276,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) crtc_state->do_async_flip = false; crtc_state->fb_bits = 0; crtc_state->update_planes = 0; - crtc_state->dsb = NULL; + crtc_state->dsb_color_vblank = NULL; return &crtc_state->uapi; } @@ -310,7 +310,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc, { struct intel_crtc_state *crtc_state = to_intel_crtc_state(state); - drm_WARN_ON(crtc->dev, crtc_state->dsb); + drm_WARN_ON(crtc->dev, crtc_state->dsb_color_vblank); __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); intel_crtc_free_hw_state(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 7ac50aacec73..27acbf92d60f 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1313,8 +1313,8 @@ static void ilk_lut_write(const struct intel_crtc_state *crtc_state, { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - if (crtc_state->dsb) - intel_dsb_reg_write(crtc_state->dsb, reg, val); + if (crtc_state->dsb_color_vblank) + intel_dsb_reg_write(crtc_state->dsb_color_vblank, reg, val); else intel_de_write_fw(i915, reg, val); } @@ -1337,15 +1337,15 @@ static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state, * unless we either write each entry twice, * or use non-posted writes */ - if (crtc_state->dsb) - intel_dsb_nonpost_start(crtc_state->dsb); + if (crtc_state->dsb_color_vblank) + intel_dsb_nonpost_start(crtc_state->dsb_color_vblank); for (i = 0; i < 256; i++) ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i), i9xx_lut_8(&lut[i])); - if (crtc_state->dsb) - intel_dsb_nonpost_end(crtc_state->dsb); + if (crtc_state->dsb_color_vblank) + intel_dsb_nonpost_end(crtc_state->dsb_color_vblank); } static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state, @@ -1870,7 +1870,7 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - if (crtc_state->dsb) + if (crtc_state->dsb_color_vblank) return; i915->display.funcs.color->load_luts(crtc_state); @@ -1890,8 +1890,8 @@ void intel_color_commit_arm(const struct intel_crtc_state *crtc_state) i915->display.funcs.color->color_commit_arm(crtc_state); - if (crtc_state->dsb) - intel_dsb_commit(crtc_state->dsb, true); + if (crtc_state->dsb_color_vblank) + intel_dsb_commit(crtc_state->dsb_color_vblank, true); } void intel_color_post_update(const struct intel_crtc_state *crtc_state) @@ -1919,33 +1919,33 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut) return; - crtc_state->dsb = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024); - if (!crtc_state->dsb) + crtc_state->dsb_color_vblank = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024); + if (!crtc_state->dsb_color_vblank) return; i915->display.funcs.color->load_luts(crtc_state); - intel_dsb_finish(crtc_state->dsb); + intel_dsb_finish(crtc_state->dsb_color_vblank); } void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state) { - if (!crtc_state->dsb) + if (!crtc_state->dsb_color_vblank) return; - intel_dsb_cleanup(crtc_state->dsb); - crtc_state->dsb = NULL; + intel_dsb_cleanup(crtc_state->dsb_color_vblank); + crtc_state->dsb_color_vblank = NULL; } void intel_color_wait_commit(const struct intel_crtc_state *crtc_state) { - if (crtc_state->dsb) - intel_dsb_wait(crtc_state->dsb); + if (crtc_state->dsb_color_vblank) + intel_dsb_wait(crtc_state->dsb_color_vblank); } bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state) { - return crtc_state->dsb; + return crtc_state->dsb_color_vblank; } static bool intel_can_preload_luts(struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 592483651b3c..05a2a6942000 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7510,7 +7510,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * * FIXME get rid of this funny new->old swapping */ - old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); + old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank); } /* Underruns don't always raise interrupts, so check manually */ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 8713835e2307..bd079cd77bda 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1396,8 +1396,8 @@ struct intel_crtc_state { /* Only valid on TGL+ */ enum transcoder mst_master_transcoder; - /* For DSB related info */ - struct intel_dsb *dsb; + /* For DSB based color LUT updates */ + struct intel_dsb *dsb_color_vblank; u32 psr2_man_track_ctl; From patchwork Mon Jun 24 19:10:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13709988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 469BEC2D0D1 for ; Mon, 24 Jun 2024 19:11:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BE92B10E570; Mon, 24 Jun 2024 19:11:20 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="m5RodzTL"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0065B10E56B for ; Mon, 24 Jun 2024 19:11:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719256275; x=1750792275; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=a6WIxLj2XXDJ9P63HV6AQEAjPNWRlYV0BcaU5N72/x0=; b=m5RodzTLZS2ILt9RmX5YxRVmLDDGW3CEwqbCrD5dN0To8zmsPMG2Q+W4 hIwuFfysj3pxaUpRktvDGcmrEjrz0vE19UBBUB9sKSaA5oIL4bj+PCm/V cchwFOTWD5Qw/PUPXxvRqBkKxg5PuPjGZFcQw1GvQag+ojfetRuOvWqlQ DvQvqaia3KlevTvrrKmp1nNbHe1AEzNBc/uesr4pWhGTg/1BTKyRK4odk gsF15kRo92qcSDg1gCReBhy+r8ld7KJ7sYPnBfzBYfWgayR+knWrEetXJ arb/oKesHgiLmhjXCBD2v/6zFMwqxAQcRvBep7kWv9yStDYU94FmDH5GB g==; X-CSE-ConnectionGUID: kLFCp9B9SBqADBfxs5H3ZA== X-CSE-MsgGUID: OIgRDHJ6T1y8vMOPVNOYsA== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16374232" X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="16374232" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2024 12:11:14 -0700 X-CSE-ConnectionGUID: v+hc2twdQnWI1z294ozFUw== X-CSE-MsgGUID: xL4SRLTrTqGPpL2JTq10VQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,262,1712646000"; d="scan'208";a="43372009" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jun 2024 12:11:12 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 24 Jun 2024 22:11:12 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 14/14] drm/i915/dsb: Use chained DSBs for LUT programming Date: Mon, 24 Jun 2024 22:10:32 +0300 Message-ID: <20240624191032.27333-15-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240624191032.27333-1-ville.syrjala@linux.intel.com> References: <20240624191032.27333-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä In order to better handle the necessary DSB DEwake tricks let's switch over to using a chained DSB for the actual LUT programming. The CPU will start 'dsb_color_commit', which in turn will start the chained 'dsb_color_vblank'. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_atomic.c | 2 ++ drivers/gpu/drm/i915/display/intel_color.c | 32 +++++++++++++++---- drivers/gpu/drm/i915/display/intel_display.c | 1 + .../drm/i915/display/intel_display_types.h | 2 +- 4 files changed, 29 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index 55ce71be41ec..12d6ed940751 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -277,6 +277,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) crtc_state->fb_bits = 0; crtc_state->update_planes = 0; crtc_state->dsb_color_vblank = NULL; + crtc_state->dsb_color_commit = NULL; return &crtc_state->uapi; } @@ -311,6 +312,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc, struct intel_crtc_state *crtc_state = to_intel_crtc_state(state); drm_WARN_ON(crtc->dev, crtc_state->dsb_color_vblank); + drm_WARN_ON(crtc->dev, crtc_state->dsb_color_commit); __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); intel_crtc_free_hw_state(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 27acbf92d60f..5d701f48351b 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1890,8 +1890,8 @@ void intel_color_commit_arm(const struct intel_crtc_state *crtc_state) i915->display.funcs.color->color_commit_arm(crtc_state); - if (crtc_state->dsb_color_vblank) - intel_dsb_commit(crtc_state->dsb_color_vblank, true); + if (crtc_state->dsb_color_commit) + intel_dsb_commit(crtc_state->dsb_color_commit, false); } void intel_color_post_update(const struct intel_crtc_state *crtc_state) @@ -1919,26 +1919,44 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut) return; - crtc_state->dsb_color_vblank = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024); + crtc_state->dsb_color_vblank = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024); if (!crtc_state->dsb_color_vblank) return; i915->display.funcs.color->load_luts(crtc_state); intel_dsb_finish(crtc_state->dsb_color_vblank); + + crtc_state->dsb_color_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 16); + if (!crtc_state->dsb_color_commit) { + intel_dsb_cleanup(crtc_state->dsb_color_vblank); + crtc_state->dsb_color_vblank = NULL; + return; + } + + intel_dsb_chain(state, crtc_state->dsb_color_commit, + crtc_state->dsb_color_vblank, true); + + intel_dsb_finish(crtc_state->dsb_color_commit); } void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state) { - if (!crtc_state->dsb_color_vblank) - return; + if (crtc_state->dsb_color_commit) { + intel_dsb_cleanup(crtc_state->dsb_color_commit); + crtc_state->dsb_color_commit = NULL; + } - intel_dsb_cleanup(crtc_state->dsb_color_vblank); - crtc_state->dsb_color_vblank = NULL; + if (crtc_state->dsb_color_vblank) { + intel_dsb_cleanup(crtc_state->dsb_color_vblank); + crtc_state->dsb_color_vblank = NULL; + } } void intel_color_wait_commit(const struct intel_crtc_state *crtc_state) { + if (crtc_state->dsb_color_commit) + intel_dsb_wait(crtc_state->dsb_color_commit); if (crtc_state->dsb_color_vblank) intel_dsb_wait(crtc_state->dsb_color_vblank); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 05a2a6942000..d5e0fa5c78b5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7511,6 +7511,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * FIXME get rid of this funny new->old swapping */ old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank); + old_crtc_state->dsb_color_commit = fetch_and_zero(&new_crtc_state->dsb_color_commit); } /* Underruns don't always raise interrupts, so check manually */ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index bd079cd77bda..f22de0495dd7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1397,7 +1397,7 @@ struct intel_crtc_state { enum transcoder mst_master_transcoder; /* For DSB based color LUT updates */ - struct intel_dsb *dsb_color_vblank; + struct intel_dsb *dsb_color_vblank, *dsb_color_commit; u32 psr2_man_track_ctl;