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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF00003F66.mail.protection.outlook.com (10.167.248.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Mon, 24 Jun 2024 21:20:19 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Jun 2024 16:20:18 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH v2 1/5] x86/topology: Export helper to get CPU number from APIC ID Date: Mon, 24 Jun 2024 16:20:04 -0500 Message-ID: <20240624212008.663832-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624212008.663832-1-yazen.ghannam@amd.com> References: <20240624212008.663832-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F66:EE_|PH7PR12MB5807:EE_ X-MS-Office365-Filtering-Correlation-Id: ec9cd00e-084d-46d0-ded6-08dc9493738d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|376011|36860700010|82310400023|1800799021; X-Microsoft-Antispam-Message-Info: apI6SQeo9GIKEvrMoWhF2nhl6/M5RpBdfHr8YJTVFDuEl/81gosJCIFqD4BhZfRuddrRpwU7fnrYdwY1cMtfU3rhdB6Tyit25DbaT7UCPspSaecNqBZtaI/OCHDtZb7EPrdJG8srsGlRRZDCvMalzh65oezVbcm9P+GiDb4R/57DIngpPwUgrHk1Bhf78CuaoXNikMfPmOfB/X1MIwCA4B6pYIpTz5mMRRc9ql9N5HH42bVorb8+zm5F2VTo2/XqMcRaaEFpnO2RG5nByXSZgaeVi3wzvQSMlF6KlJuXlp4dgcPPzTUZEBN08UslGzigjkf7CUbzAvLmKdc+haGdvubCKnQ+YxCogQ2LfIpOaKyf2anHU9qJnJELXulRELrrarL/d6omhsQ8VTZe5NH31XalebGb/eUETP9ngIb8vaSogT4K2oxUdoKTO/23uoGf0k8AAQPtiUnxw2dWKzVXTfZvd4jHBy4B+hbpPuSWVcRw2062EKaiRZnfkLhFvjnpzyPA/M4kn+6rzgrLcvSTqC4J7ENr7RE785U1kNxkiRKqWd5Wkd1Tq2x3UptivCje3GY1tqUJrXCA3cQnVkHWVQbJX1bfqsE8IrhS05S+LUQpmxN1m1WJJQ7OUaozelvqUHsH5CyceQpY9iQ8nWLyZpCdmSaEKgzsvH0cUFISOhj7ojdQl8GgcSnxdMnHLXZuwL1dtH4JM+cO2uiL6+L8ewppwRIXFzLaCDBSJiXX0lCJwz76v1GjLfdkH46aEL+uDfj5FIV/VAVtqTSd0ZlVNJjApbSZHY2OfFoge/EF2hTxyx9HMbjoZKIxh+xcEjm+jaKC9T3VbumsYfzh5Moqt+Uf3MQ3OGcGP2ZvL3hCCCWlKvn45Y4rG/R3pN2R40XGwGgVQ70yvON8T/pbN64LjHYsYXu5VBlBvj55iIqryHkRfJak2BNJUYzyVmTDvv37ieK74egnhc/QXeb+KsBOHOcyQxgH6W729Uf3Ua7Z1Ae5cd04vt2TGMhfSNw7ZrMgAPCydWxGOuZ/MloGSSYcBQtpi1i00A4aupuTpkjUBBEMG9Nk16pLlu98kAWmGv9LAQkfOgiRCE3oz8nlAVpZd/NKNcDv93r5EhrIx1yl1Tsye/R0FI1I15UjimU9L864Ga6jgXB16sKIjisJ6Y8U99IA5MD2/8KkFBvzUNGqGk1muJZPDFgvQTrj9K37WTIJ/0OoJZreGOYNNJYlZrNRX4HfSt8QeI2l0g62IHA7z9J+zb8iSAnJN2h3fFxX+c6gSd+lNPlW4lv3r41To7FAfClx+lV+ERsY33dGuwsMNEH9skaKAJgZ2sbe1gPbOnA0ayvC1xJ3QAYB3kP5qXGOCryMgOtVrcvNK8isdVFbNa0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(376011)(36860700010)(82310400023)(1800799021);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 21:20:19.8611 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ec9cd00e-084d-46d0-ded6-08dc9493738d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5807 The need to look up a CPU number from an APIC ID is done in at least one other place outside of APIC/topology code: apei_smca_report_x86_error(). With the recent topology rework, there is now a helper function to do just this task. Export the helper so other code can use it. Also, update the name to match other exported topology_* helpers. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20240618172447.GA1387@yaz-khff2.amd.com v1->v2: * New in v2. arch/x86/include/asm/topology.h | 6 ++++++ arch/x86/kernel/cpu/topology.c | 15 ++++++++++++--- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index abe3a8f22cbd..d8c3c3c818bc 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -171,11 +171,17 @@ static inline unsigned int topology_num_threads_per_package(void) #ifdef CONFIG_X86_LOCAL_APIC int topology_get_logical_id(u32 apicid, enum x86_topology_domains at_level); +int topology_get_cpunr(u32 apic_id); #else static inline int topology_get_logical_id(u32 apicid, enum x86_topology_domains at_level) { return 0; } + +static inline int topology_get_cpunr(u32 apic_id) +{ + return -ENODEV; +} #endif #ifdef CONFIG_SMP diff --git a/arch/x86/kernel/cpu/topology.c b/arch/x86/kernel/cpu/topology.c index 621a151ccf7d..fc74578ee3bd 100644 --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -95,7 +95,15 @@ static inline u32 topo_apicid(u32 apicid, enum x86_topology_domains dom) return apicid & (UINT_MAX << x86_topo_system.dom_shifts[dom - 1]); } -static int topo_lookup_cpuid(u32 apic_id) +/** + * topology_get_cpunr - Retrieve the CPU number for the given APIC ID + * @apic_id: The APIC ID for which to lookup the CPU number + * + * Returns: + * - >= 0: The CPU number for the given APIC ID + * - -ENODEV: @apic_id does not match any known CPU + */ +int topology_get_cpunr(u32 apic_id) { int i; @@ -106,10 +114,11 @@ static int topo_lookup_cpuid(u32 apic_id) } return -ENODEV; } +EXPORT_SYMBOL_GPL(topology_get_cpunr); static __init int topo_get_cpunr(u32 apic_id) { - int cpu = topo_lookup_cpuid(apic_id); + int cpu = topology_get_cpunr(apic_id); if (cpu >= 0) return cpu; @@ -388,7 +397,7 @@ int topology_hotplug_apic(u32 apic_id, u32 acpi_id) if (!test_bit(apic_id, apic_maps[TOPO_SMT_DOMAIN].map)) return -ENODEV; - cpu = topo_lookup_cpuid(apic_id); + cpu = topology_get_cpunr(apic_id); if (cpu < 0) return -ENOSPC; From patchwork Mon Jun 24 21:20:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13710114 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2041.outbound.protection.outlook.com [40.107.92.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE3A61A070C; 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Mon, 24 Jun 2024 16:20:19 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH v2 2/5] x86/mce: Fixup APIC ID search for x86 CPER decoding Date: Mon, 24 Jun 2024 16:20:05 -0500 Message-ID: <20240624212008.663832-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624212008.663832-1-yazen.ghannam@amd.com> References: <20240624212008.663832-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F66:EE_|CH3PR12MB8657:EE_ X-MS-Office365-Filtering-Correlation-Id: bef23bcd-8ae4-4e52-a0d8-08dc949373d0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|1800799021|376011|82310400023|36860700010; X-Microsoft-Antispam-Message-Info: IpXAtdaOyK/4d3ZO2wHSOqkppb3lHLHs6TmMrc0VET9a+vAi8Radybp5DtaOa0KwkaQRwvIruMc1faq5Rf9lOp6iyHL21+3U1h4OR4wdlGRfkrrLUXDoiJ6GmxfxdyjvyyZmBJSco6cTh0WIrivgHlvriuVhzYYNO4gx0sfitPED1OG1On6TU+JuyQsbEhbzC3YTDumXduU1t374QRVWmryKON+BEUPlJoK/ZcGoj1SozhsQ4Pj2/Dt+EBKOF13aYQP1x/kNwkIuJCInTt8Qcn2EY8bGD5dQ7woJYW6SDb7l5cTCw9WKXTJA/oN2QAeQTlbOxEVV2G4S+BXZWnNdw2T9pM7xM9mVvVoCPRFmfCrVPLr9a0vHMbrOmJA406Jwi/C913coWE0WdM8c321iUwq4eja3uO9QTvHKo5UXIYDUpu2A6DjCvWxWoCPh0DpBWQf+1J61BYEC255i4qQlatneqLXyyOo0wKgp1AoM3hT6kBzo5fSvvcL5nGHw5o/EFBLPU7Q1S1Svkl0toTUtCgx8WopetLWWm967kLv467s2PeAP77+LvE0dy4ethvEEDruCEYref6WOp84bHNcs9m4hJ/SKIciRnQlLOGHMQy+Z1cuwV0RMP/yjMzpewYOEFywrgUs1JF1a1y7iWQojb1NALazJyKoOGs0wNuNG4H1HmzMHckGfbb8alOcRsfwHxKGmqjEqO7APo4K5lS5kaB+j3li+rHKAM22y5QXomKL9gI8ZnsB1si/ktcPRXmFm+IGunNUh5Yh8mBem3sJpdvknjksiWOzxL5hF29UQi4NTB1A24Dh9sX/N4VacJgTfRT0heK3XPqaO6suOtolnDFtRxmPlMz1iF3PfYpx3ERLHlWKZw+OwoktrlI5blMh8yvuuSEjEGZsqLqkDiXe4uwokK4P+tzlBh4Ppe0rZyNTCIyPR7QQjTj2BNCGE3A/6gzsOZeCgwgNMqUMhpoMiJJXRtaPm5KzHNRJCiZZeYbOw0ZVRId+3MStgLrfLOtpEetoSwelZ+wxLq1lJJySpaFaEx530i+QDdtHMA/1oPxeDKfPy8mEKVMCLLPN8bv4hGaf+MFVU72q7SMAAdId+H404E9QYgp0YuLbRWZ7ZG4BVk+gdA0hmHNhkEirdRbIwmU/NkWugKWXI0sAU6IJLxnDQ07NQ9FP/TpoVW1rjFOLuM6YJDI3Bji0ENZoib8zoQ2QIhFEjGQK/Bu/cHQcbCB+YjGSVXbA6E20Vh4Fcvrt41RyFPu1JmYJAEjb/ttYkgvkrL6xLKQQZK94FqAtpR6yLCzCRqyqzpgYVhGtOerE0p2a49WjVXmoNoAwenkku9asV8GyJ4WpX15t7qIExOwTqnPKsZFOSq3r5J46Fgds= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(1800799021)(376011)(82310400023)(36860700010);DIR:OUT;SFP:1101; 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Additionally, this now handles the case where a CPU match is not found. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20240618172447.GA1387@yaz-khff2.amd.com v1->v2: * New in v2. arch/x86/kernel/cpu/mce/apei.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index 7f7309ff67d0..59f1c9ea47f5 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -66,12 +66,16 @@ EXPORT_SYMBOL_GPL(apei_mce_report_mem_error); int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) { const u64 *i_mce = ((const u64 *) (ctx_info + 1)); - unsigned int cpu; struct mce m; + int cpu; if (!boot_cpu_has(X86_FEATURE_SMCA)) return -EINVAL; + cpu = topology_get_cpunr(lapic_id); + if (cpu < 0) + return cpu; + /* * The starting address of the register array extracted from BERT must * match with the first expected register in the register layout of @@ -99,16 +103,8 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) mce_setup(&m); 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X-Microsoft-Antispam-Message-Info: 5km3f6aRRD6ASoczDM0/Ao7aEEn2gMi0WuWczYljZqDQ0jRnOBtAp2pXue77gXkWIpyO+K7NVCRM34l64sWSbYowxe5sf5ys3AfL5qAhtGs120//V+AQz4TKCJ0VbFY4eSFRe921ulF9XrX+KixzLllSQ5HR4n8psuCYBRi++S0FY+r/IOrhi/OoyYUU8uVf1K2M9RNSbG5R5ctOCOjD5OvLvsYoPVSKfd3VELvMnxfeA6H34Qd6j3cMsSX6PGqXqBy1mdIH5hezmAcj2n4s9vu6UU3uEhXn5ZH/ZkaGK/mrLoW1WwSf/rSpJNfS/Ii7nAj+n1ka1DB+KMpZamsskElpNYCJ11oB21cCPoAywC/bRkB0UeBSzsxL55QmOy+sJcUM7GmFm5RAk3EuCvbT+LvYOvrPrist1NmX5yTj83FnOgkCwGF0TvoN9lIemN5fTOBfLR3Cp3KTHcsQpVVwmNTCm+Mitbz6GlDMZwo7DuKst/DpNmvEX12fWLbfa/sGuqJ1359BLFHcX1/qr/R7cevBefCuQrUVDfZYAi9vLXWOLGpYySzfK7XFDwrlWs9DOk0VD5MQVE6SBFlIyfyacm3Li8+aL50qPz34/JqYzoTRMUc98b4BSLT5QrNRgISTugq1ZNriKUNV5eTvyUGMsC23C060Q5CJ672JkiQE+UzOiaEJoPrOVZzLe4DvZd6YF1cHW1cRayIuuEhlPGD6X4QHffD2rI9IZXaTrJzg+YPGRMRBjweYumss6yK2aBsgz0WtRGwx9zBvywc1pwk3BMmsIBWhq/+bNiQR0dvVrtd34Tx5l0z37E0yHUDkDRQ+GdNVgvRXzo3qRMEEkvxHl9Rxiv/vUhd88WUbYPAc5HhOT5fy+L3YIbH6BFO5dQlUvysmCrCHz5OcaITU4WYsL0l3d7cBfowDeunFyso+c/OU4+EzBK/2MAjwO8iAPBnH+kbmQWpd+p6N3A+QtHCZlRUicCAaZe3F4PWP3rtKCkYZUVAf9WmxTUAnPNh7YTLornUqYpkl6U48yZK/Icdd8PX+mJrXvhuINCAOrV5PXZidoRcyjxalldTlic23SK8UsL/sVJ5zunVYVitJxAshqnPqaeDO1aTOImfHAR0zrW5cP+XR/6KF95O0RuaJFX+3SkWbpURX+WSlFJEGDrwcRREHKfp7Rxowo9GJMKG8rgbz2E4SBY0TFzyiQVDOXaMnCRccGq6awjKE4HyPkuvCjQMGu+O/NKgnbN919an3AEXTF8zu99T005PSsHnxXNpRkDAfJtwIL8b3SEt1xPhLyzJu2fyLqdv47p8UI0M7ej9k+En7rcuvnCdmgJSXXp1z4g2WX1LuYNCwJfrx37w7eE90l3TVChu8QhgIblyGBuE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(82310400023)(1800799021)(36860700010)(376011);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 21:20:21.0173 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4a119e7-6012-42bc-4d60-08dc9493743e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9413 There is no MCE "setup" done in mce_setup(). Rather this function initializes and prepares an MCE record. Rename the function to highlight what it does. No functional change is intended. Suggested-by: Borislav Petkov Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20240521125434.1555845-2-yazen.ghannam@amd.com v1->v2: * No change. arch/x86/include/asm/mce.h | 2 +- arch/x86/kernel/cpu/mce/amd.c | 2 +- arch/x86/kernel/cpu/mce/apei.c | 4 ++-- arch/x86/kernel/cpu/mce/core.c | 6 +++--- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 3ad29b128943..3b9970117a0f 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -221,7 +221,7 @@ static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) { return -EINVAL; } #endif -void mce_setup(struct mce *m); +void mce_prep_record(struct mce *m); void mce_log(struct mce *m); DECLARE_PER_CPU(struct device *, mce_device); diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 9a0133ef7e20..14bf8c232e45 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -780,7 +780,7 @@ static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) { struct mce m; - mce_setup(&m); + mce_prep_record(&m); m.status = status; m.misc = misc; diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index 59f1c9ea47f5..8e8ad63da5b6 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -44,7 +44,7 @@ void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err) else lsb = PAGE_SHIFT; - mce_setup(&m); + mce_prep_record(&m); m.bank = -1; /* Fake a memory read error with unknown channel */ m.status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 0x9f; @@ -101,7 +101,7 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) if (ctx_info->reg_arr_size < 48) return -EINVAL; - mce_setup(&m); + mce_prep_record(&m); m.extcpu = cpu; m.socketid = cpu_data(cpu).topo.pkg_id; diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index b85ec7a4ec9e..dd5192ef52e0 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -118,7 +118,7 @@ static struct irq_work mce_irq_work; BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); /* Do initial initialization of a struct mce */ -void mce_setup(struct mce *m) +void mce_prep_record(struct mce *m) { memset(m, 0, sizeof(struct mce)); m->cpu = m->extcpu = smp_processor_id(); @@ -436,11 +436,11 @@ static noinstr void mce_wrmsrl(u32 msr, u64 v) static noinstr void mce_gather_info(struct mce *m, struct pt_regs *regs) { /* - * Enable instrumentation around mce_setup() which calls external + * Enable instrumentation around mce_prep_record() which calls external * facilities. */ instrumentation_begin(); - mce_setup(m); + mce_prep_record(m); instrumentation_end(); m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); From patchwork Mon Jun 24 21:20:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13710115 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2048.outbound.protection.outlook.com [40.107.102.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BA881A08BF; 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Mon, 24 Jun 2024 16:20:20 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH v2 4/5] x86/mce: Define mce_prep_record() helpers for common and per-CPU fields Date: Mon, 24 Jun 2024 16:20:07 -0500 Message-ID: <20240624212008.663832-5-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624212008.663832-1-yazen.ghannam@amd.com> References: <20240624212008.663832-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F66:EE_|SJ0PR12MB6808:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c9cbdab-3b48-498d-0df7-08dc949374a0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|376011|1800799021|82310400023|36860700010; X-Microsoft-Antispam-Message-Info: G111Tmizt6249eTFN8uG6/19FDDuWNrCQC1NAV+7d8Ab/Q+LRqXS+MmQTxa/BX13lqU4ID8+avJpeClp09negFgmNrn/ubsO7cYZlvG63hY4LE71/M5CD6dkyOFHNFKViDM1lKn2jcac4ujmlZGP0bS7eAc8iqFCwhOIOLf/CpccfuCwrx94SG6ecZg/KjcCD6/MaP1QztqOaL6nWrStXJcmoXtGbkBB/Jta7LgfRYvy0VtO/bV5CuZ4AvbG4bjWnVj9jPknsz4hmOfwZ4R8C+ebqEW0u6BdkaSpDzmYQW2eBCvRvZNjNOAxNuoaSdlE9LJUf6KC6lAMaicfkzyG8gjpR3NNn2f+gk2HX7LAS7pnKDSqGrJVfuFh8GhtCOojezn93s5/786t6smIuOuRT7zIc0CseJ4cjZB4n5vt0nT4Mp9Yo49kRhrPRsgxCe+fUVpbB9CYlzqAulp4pz0uerHwdBLrhnQ1W0I8yyPdp6y46o9oeEtl8GNqTVofvxPvMRk5xfSNqFwW+oIrNYcXtMT+f0/X1tVdMvA5lWYeW7cm4Xi5XtFqEkNMI8mqsQIAzDe0j/UlBAx4IS0sNo1n/0vxFmYzF2d2F7W2GzMtSXl8/hQcJOHoRBEwHM+WevybaXM5fDHLh7/gqv6oPNl3jkD4UZ3cMHzAnoIrV6QPvWuUvlcd+lNDjd+n8RSYonlGfFdDDNHHstKagOqoqwZ/x+EuYiB81+QEkOnnGIqCJfvaX8BLyx6zFh6m3DssynychbOfLataZFwOSxREwqTVLz0Wef1p1GQezAPkxFVUazWo579qwdotV1gIEH+yEWc9yAv4H1NJAfRufuU1MEHvU7jjGTy8qjjhFaD1+6M1+HzONfi1xyUS0nuodV/YdXuV93bLQhj12AdkXKMOnlgiNyEX8BnehqGCws+BIn8Fdj05PX9NVcP99G8/+xHdZseHpoQUoVdw0I+r+vsnpvjbq1L2VHEfsISSHaJKIqydbovISSrCBt4iOQ6wtlKiEqvZw/vgIkHxQkgVo8dyNGfRMXxqTxCE6pOtops4dUuR4Levy24bNZlyKEdo3hh/D0OJg1t1BMfrMYzSYo7RC5838xQokIV7NmlDM94rXUJ3rdkElwNF123f4wvxCbt6C+NbekrS8Mu+mZKzdjVeWcc5YTCZRvtrJEmjIEOKa9atoiOsHm44GjZZEmPFyvBUs7xUbd3M+wOKsAAi2kjazATueec7FhBfSPckEcn9f10Nimxo0A8psmbmOIv1f3f+mtpt49wFWXLSdHSa47q72gWBB4Vu25WBpWfEGDbph15Z2rt5dXk1CWju4zTYePJLat4FafUWqxGrBirg/ZpwAeRjgFM2p/JhEj00HA/uaMGf8do= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(376011)(1800799021)(82310400023)(36860700010);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 21:20:21.6580 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c9cbdab-3b48-498d-0df7-08dc949374a0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6808 Generally, MCA information for an error is gathered on the CPU that reported the error. In this case, CPU-specific information from the running CPU will be correct. However, this will be incorrect if the MCA information is gathered while running on a CPU that didn't report the error. One example is creating an MCA record using mce_prep_record() for errors reported from ACPI. Split mce_prep_record() so that there is a helper function to gather common, i.e. not CPU-specific, information and another helper for CPU-specific information. Leave mce_prep_record() defined as-is for the common case when running on the reporting CPU. Get MCG_CAP in the global helper even though the register is per-CPU. This value is not already cached per-CPU like other values. And it does not assist with any per-CPU decoding or handling. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20240521125434.1555845-3-yazen.ghannam@amd.com v1->v2: * No change. arch/x86/kernel/cpu/mce/core.c | 34 ++++++++++++++++++++---------- arch/x86/kernel/cpu/mce/internal.h | 2 ++ 2 files changed, 25 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index dd5192ef52e0..0133f88dfffb 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -117,20 +117,32 @@ static struct irq_work mce_irq_work; */ BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); -/* Do initial initialization of a struct mce */ -void mce_prep_record(struct mce *m) +void mce_prep_record_common(struct mce *m) { memset(m, 0, sizeof(struct mce)); - m->cpu = m->extcpu = smp_processor_id(); + + m->cpuid = cpuid_eax(1); + m->cpuvendor = boot_cpu_data.x86_vendor; + m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); /* need the internal __ version to avoid deadlocks */ - m->time = __ktime_get_real_seconds(); - m->cpuvendor = boot_cpu_data.x86_vendor; - m->cpuid = cpuid_eax(1); - m->socketid = cpu_data(m->extcpu).topo.pkg_id; - m->apicid = cpu_data(m->extcpu).topo.initial_apicid; - m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); - m->ppin = cpu_data(m->extcpu).ppin; - m->microcode = boot_cpu_data.microcode; + m->time = __ktime_get_real_seconds(); +} + +void mce_prep_record_per_cpu(unsigned int cpu, struct mce *m) +{ + m->cpu = cpu; + m->extcpu = cpu; + m->apicid = cpu_data(m->extcpu).topo.initial_apicid; + m->microcode = cpu_data(m->extcpu).microcode; + m->ppin = cpu_data(m->extcpu).ppin; + m->socketid = cpu_data(m->extcpu).topo.pkg_id; +} + +/* Do initial initialization of a struct mce */ +void mce_prep_record(struct mce *m) +{ + mce_prep_record_common(m); + mce_prep_record_per_cpu(smp_processor_id(), m); } DEFINE_PER_CPU(struct mce, injectm); diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 01f8f03969e6..43c7f3b71df5 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -261,6 +261,8 @@ enum mca_msr { /* Decide whether to add MCE record to MCE event pool or filter it out. */ extern bool filter_mce(struct mce *m); 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Mon, 24 Jun 2024 21:20:22 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF00003F66.mail.protection.outlook.com (10.167.248.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Mon, 24 Jun 2024 21:20:22 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Jun 2024 16:20:20 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH v2 5/5] x86/mce: Use mce_prep_record() helpers for apei_smca_report_x86_error() Date: Mon, 24 Jun 2024 16:20:08 -0500 Message-ID: <20240624212008.663832-6-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624212008.663832-1-yazen.ghannam@amd.com> References: <20240624212008.663832-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F66:EE_|IA0PR12MB8205:EE_ X-MS-Office365-Filtering-Correlation-Id: 640a9d16-2d00-4ce3-2f9d-08dc94937523 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|82310400023|36860700010|1800799021|376011; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 21:20:22.5330 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 640a9d16-2d00-4ce3-2f9d-08dc94937523 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8205 Current AMD systems can report MCA errors using the ACPI Boot Error Record Table (BERT). The BERT entries for MCA errors will be an x86 Common Platform Error Record (CPER) with an MSR register context that matches the MCAX/SMCA register space. However, the BERT will not necessarily be processed on the CPU that reported the MCA errors. Therefore, the correct CPU number needs to be determined and the information saved in struct mce. Use the newly defined mce_prep_record_*() helpers to get the correct data. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20240521125434.1555845-4-yazen.ghannam@amd.com v1->v2: * Rebased on new changes from patches 1 and 2. arch/x86/kernel/cpu/mce/apei.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index 8e8ad63da5b6..7e60db2addec 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -101,12 +101,9 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) if (ctx_info->reg_arr_size < 48) return -EINVAL; - mce_prep_record(&m); - - m.extcpu = cpu; - m.socketid = cpu_data(cpu).topo.pkg_id; + mce_prep_record_common(&m); + mce_prep_record_per_cpu(cpu, &m); - m.apicid = lapic_id; m.bank = (ctx_info->msr_addr >> 4) & 0xFF; m.status = *i_mce; m.addr = *(i_mce + 1);