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Wysocki" , Huang Rui , Mario Limonciello Subject: [PATCH v14 1/5] cpufreq: acpi: move MSR_K7_HWCR_CPB_DIS_BIT into msr-index.h Date: Mon, 24 Jun 2024 16:33:56 -0500 Message-ID: <20240624213400.67773-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624213400.67773-1-mario.limonciello@amd.com> References: <20240624213400.67773-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|CH0PR12MB8488:EE_ X-MS-Office365-Filtering-Correlation-Id: 38fb7653-11a4-440f-31f1-08dc949567d1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|1800799021|82310400023|376011; X-Microsoft-Antispam-Message-Info: jxbwi8Upf69eutJ+RcBtbES+9okKk3p1SA/crDT5vFBOUSht5sMElZLsqrxvejFRspwRFxHxPwyJ2goInzk/ikEx+U1XrNVWzPPbV8tGqNtdotsHnR7o8Wsttb31zXPvS6HwqJrRl1FJU1hSTfg5855MWLQlvon3uEWM698Rn33aEGxjcJJxu21ZJxHnPwElXhd7Snb6NcKjgzsFELlZ/DAEWdz/1NB5ArVgG27+RbYhMYQ6QOdcqDdUPU4CMD1UactQlB21nt08qRiiTHXWQvanmRHUbX3HWiKFkkkvq5I/LQWGNSit2dlkgGnyk+qkpCM7A6lHs3FjZFQjTa6SAWKbuEqWigFZqX46Y1Z3H2aqKOgCxdCQPWP59PLkpW6SybqSwcdEl/uxb6nuJRTb8MwTpEoUxxqBcM8FkuwkD2n7hJoKa8Qg0k7g2D93KzXoPv8lNG7DWgs7AvQeMZLl+5xUFpecvYxRpNnuc3KPrhjzMszb7p8YUf9uJm3EAKxHTT2CmC4SKNhT+vhq1o+D2gjneDqku1AEuIO/30MmMXUaTLT0bcmmqgdwhgf2VFyHw09iV/BzictDfcDWtkY7iL2zp8kN41FcuaBFgAUHSOBQ980b/C5qn0N5vcp71zvjWSAmz1bkL8HHK5z4bynyPVY/2d/jdjH1r42i02Pno2ypSAIob7/on0okimf2do5wF5SXyqIR2aIpimMEEug2QFQkOoaQ3dKWeE8Hcp63Ud/an0hlLfC0gRA9d9kFQq14bVUaxxYnNzUGKmaaw0agG6DKzvQP5U+1FgP2wao6RJl8wiNDBUX+k/XKysRdQmSyySCYxx1VEM3XOPbtvlpSx/S1SkH4aeTEQdJyGDWU9ODxj7yyBlSAoyf6Qk3k7g1a7To8kSRTjfCuxFYwN7ngljqyEvlWbj2wEiH2DnEkGWGTxdQkKujc03TNpeSOUEQOoJgjSLXh5gFLmBFyaBuMrSNA00bgjbKeknbxdgfdwOqFeaTS57gFSO/dtyXFPu7Zh801hiHViBR0JpVZG9v8cZPAP+IKDo/NckTY0BIGRGvt56Ch8Cw04zoRuevvh59l9ivMJ6c3NJLNLQHgVM41MVt1mj4gA6ZJfsvA/tTnXICIKqA+zmU7taLE5rcwcUCMxc6V0dBakFWi0XU6IiPl1+LwiFScON1xNAMGX17v2aKHHNPn/ZOIARG0gNgcY+tP0bphe/+Iv2dwqVtW5/VyrjH7+OVSD332HttcNpISB+HZpYRD8jR/ZHfSVQJAYr/j+SVktSNVgVe6fg20v3Qu2iLQUz/vuPX8VXN3TYPOrap/MbNcsSR8/yhx4X5fzOWEJ0fvcAoyKn0EPizH85psbg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(36860700010)(1800799021)(82310400023)(376011);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 21:34:19.1631 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 38fb7653-11a4-440f-31f1-08dc949567d1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8488 From: Perry Yuan There are some other drivers also need to use the MSR_K7_HWCR_CPB_DIS_BIT for CPB control bit, so it makes sense to move the definition to a common header file to allow other driver to use it. No intentional functional impact. Suggested-by: Gautham Ranjal Shenoy Signed-off-by: Perry Yuan Acked-by: Rafael J. Wysocki Acked-by: Huang Rui Link: https://lore.kernel.org/r/78b6c75e6cffddce3e950dd543af6ae9f8eeccc3.1718988436.git.perry.yuan@amd.com Signed-off-by: Mario Limonciello --- arch/x86/include/asm/msr-index.h | 2 ++ drivers/cpufreq/acpi-cpufreq.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index e022e6eb766c..384739d592af 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -781,6 +781,8 @@ #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) #define MSR_K7_FID_VID_CTL 0xc0010041 #define MSR_K7_FID_VID_STATUS 0xc0010042 +#define MSR_K7_HWCR_CPB_DIS_BIT 25 +#define MSR_K7_HWCR_CPB_DIS BIT_ULL(MSR_K7_HWCR_CPB_DIS_BIT) /* K6 MSRs */ #define MSR_K6_WHCR 0xc0000082 diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c index 37f1cdf46d29..2fc82831bddd 100644 --- a/drivers/cpufreq/acpi-cpufreq.c +++ b/drivers/cpufreq/acpi-cpufreq.c @@ -50,8 +50,6 @@ enum { #define AMD_MSR_RANGE (0x7) #define HYGON_MSR_RANGE (0x7) -#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) - struct acpi_cpufreq_data { unsigned int resume; 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Mon, 24 Jun 2024 21:34:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH2PEPF00000146.mail.protection.outlook.com (10.167.244.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Mon, 24 Jun 2024 21:34:19 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Jun 2024 16:34:18 -0500 From: Mario Limonciello To: , CC: Linux PM , Perry Yuan , Oleksandr Natalenko , Mario Limonciello Subject: [PATCH v14 2/5] cpufreq: amd-pstate: initialize core precision boost state Date: Mon, 24 Jun 2024 16:33:57 -0500 Message-ID: <20240624213400.67773-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624213400.67773-1-mario.limonciello@amd.com> References: <20240624213400.67773-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|PH0PR12MB8774:EE_ X-MS-Office365-Filtering-Correlation-Id: 259a880d-a234-4039-6a7e-08dc9495680a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|1800799021|82310400023|376011; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 21:34:19.5381 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 259a880d-a234-4039-6a7e-08dc9495680a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8774 From: Perry Yuan The "Core Performance Boost (CPB) feature, when enabled in the BIOS, allows the OS to control the highest performance for each individual core. The active, passive and the guided modes of the amd-pstate driver do support controlling the core frequency boost when this BIOS feature is enabled. Additionally, the amd-pstate driver provides a sysfs interface allowing the user to activate/deactivate this core performance boost feature at runtime. Add support for the set_boost callback in the active mode driver to enable boost control via the cpufreq core. This ensures a consistent boost control interface across all pstate modes, including passive mode, guided mode, and active mode. With this addition, all three pstate modes can support the same boost control interface with unique interface and global CPB control. Each CPU also supports individual boost control, allowing global CPB to change all cores' boost states simultaneously. Specific CPUs can update their boost states separately, ensuring all cores' boost states are synchronized. Cc: Oleksandr Natalenko Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 115 ++++++++++++++++++++++++++++------- drivers/cpufreq/amd-pstate.h | 1 + 2 files changed, 95 insertions(+), 21 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index afcf398574f6..10cce7023208 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -679,43 +679,105 @@ static void amd_pstate_adjust_perf(unsigned int cpu, cpufreq_cpu_put(policy); } -static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) +static int amd_pstate_cpu_boost_update(struct cpufreq_policy *policy, bool on) { struct amd_cpudata *cpudata = policy->driver_data; + struct cppc_perf_ctrls perf_ctrls; + u32 highest_perf, nominal_perf, nominal_freq, max_freq; int ret; - if (!cpudata->boost_supported) { - pr_err("Boost mode is not supported by this processor or SBIOS\n"); - return -EINVAL; + highest_perf = READ_ONCE(cpudata->highest_perf); + nominal_perf = READ_ONCE(cpudata->nominal_perf); + nominal_freq = READ_ONCE(cpudata->nominal_freq); + max_freq = READ_ONCE(cpudata->max_freq); + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 value = READ_ONCE(cpudata->cppc_req_cached); + + value &= ~GENMASK_ULL(7, 0); + value |= on ? highest_perf : nominal_perf; + WRITE_ONCE(cpudata->cppc_req_cached, value); + + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + } else { + perf_ctrls.max_perf = on ? highest_perf : nominal_perf; + ret = cppc_set_perf(cpudata->cpu, &perf_ctrls); + if (ret) { + cpufreq_cpu_release(policy); + pr_debug("Failed to set max perf on CPU:%d. ret:%d\n", + cpudata->cpu, ret); + return ret; + } } - if (state) - policy->cpuinfo.max_freq = cpudata->max_freq; + if (on) + policy->cpuinfo.max_freq = max_freq; else - policy->cpuinfo.max_freq = cpudata->nominal_freq * 1000; + policy->cpuinfo.max_freq = nominal_freq * 1000; policy->max = policy->cpuinfo.max_freq; - ret = freq_qos_update_request(&cpudata->req[1], - policy->cpuinfo.max_freq); - if (ret < 0) - return ret; + if (cppc_state == AMD_PSTATE_PASSIVE) { + ret = freq_qos_update_request(&cpudata->req[1], policy->cpuinfo.max_freq); + if (ret < 0) + pr_debug("Failed to update freq constraint: CPU%d\n", cpudata->cpu); + } - return 0; + return ret < 0 ? ret : 0; } -static void amd_pstate_boost_init(struct amd_cpudata *cpudata) +static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) { - u32 highest_perf, nominal_perf; + struct amd_cpudata *cpudata = policy->driver_data; + int ret; - highest_perf = READ_ONCE(cpudata->highest_perf); - nominal_perf = READ_ONCE(cpudata->nominal_perf); + if (!cpudata->boost_supported) { + pr_err("Boost mode is not supported by this processor or SBIOS\n"); + return -EOPNOTSUPP; + } + mutex_lock(&amd_pstate_driver_lock); + ret = amd_pstate_cpu_boost_update(policy, state); + WRITE_ONCE(cpudata->boost_state, !ret ? state : false); + policy->boost_enabled = !ret ? state : false; + refresh_frequency_limits(policy); + mutex_unlock(&amd_pstate_driver_lock); - if (highest_perf <= nominal_perf) - return; + return ret; +} + +static int amd_pstate_init_boost_support(struct amd_cpudata *cpudata) +{ + u64 boost_val; + int ret = -1; - cpudata->boost_supported = true; + /* + * If platform has no CPB support or disable it, initialize current driver + * boost_enabled state to be false, it is not an error for cpufreq core to handle. + */ + if (!cpu_feature_enabled(X86_FEATURE_CPB)) { + pr_debug_once("Boost CPB capabilities not present in the processor\n"); + ret = 0; + goto exit_err; + } + + /* at least one CPU supports CPB, even if others fail later on to set up */ current_pstate_driver->boost_enabled = true; + + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); + if (ret) { + pr_err_once("failed to read initial CPU boost state!\n"); + ret = -EIO; + goto exit_err; + } + + if (!(boost_val & MSR_K7_HWCR_CPB_DIS)) + cpudata->boost_supported = true; + + return 0; + +exit_err: + cpudata->boost_supported = false; + return ret; } static void amd_perf_ctl_reset(unsigned int cpu) @@ -968,6 +1030,10 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) if (ret) goto free_cpudata1; + ret = amd_pstate_init_boost_support(cpudata); + if (ret) + goto free_cpudata1; + min_freq = READ_ONCE(cpudata->min_freq); max_freq = READ_ONCE(cpudata->max_freq); @@ -980,6 +1046,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) policy->cpuinfo.min_freq = min_freq; policy->cpuinfo.max_freq = max_freq; + policy->boost_enabled = READ_ONCE(cpudata->boost_supported); + /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; @@ -1005,7 +1073,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) policy->driver_data = cpudata; - amd_pstate_boost_init(cpudata); if (!current_pstate_driver->adjust_perf) current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; @@ -1420,6 +1487,10 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) if (ret) goto free_cpudata1; + ret = amd_pstate_init_boost_support(cpudata); + if (ret) + goto free_cpudata1; + min_freq = READ_ONCE(cpudata->min_freq); max_freq = READ_ONCE(cpudata->max_freq); @@ -1435,6 +1506,8 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) policy->min = policy->cpuinfo.min_freq; policy->max = policy->cpuinfo.max_freq; + policy->boost_enabled = READ_ONCE(cpudata->boost_supported); + /* * Set the policy to provide a valid fallback value in case * the default cpufreq governor is neither powersave nor performance. @@ -1456,7 +1529,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) return ret; WRITE_ONCE(cpudata->cppc_cap1_cached, value); } - amd_pstate_boost_init(cpudata); return 0; @@ -1718,6 +1790,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .suspend = amd_pstate_epp_suspend, .resume = amd_pstate_epp_resume, .update_limits = amd_pstate_update_limits, + .set_boost = amd_pstate_set_boost, .name = "amd-pstate-epp", .attr = amd_pstate_epp_attr, }; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 21:34:20.6787 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f7cd158-d994-4e68-3c11-08dc949568bd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7018 From: Perry Yuan When Core Performance Boost is disabled by the user, the CPPC_REQ.max_perf should not exceed the nominal_perf since by definition the frequencies between nominal_perf and the highest_perf are in the boost range. Fix this in amd_pstate_update() Acked-by: Huang Rui Reviewed-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Link: https://lore.kernel.org/r/66f55232be01092c423f0523f68b82b80c293943.1718988436.git.perry.yuan@amd.com Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 10cce7023208..6992f6169919 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -514,6 +514,7 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, unsigned long max_freq; struct cpufreq_policy *policy = cpufreq_cpu_get(cpudata->cpu); u64 prev = READ_ONCE(cpudata->cppc_req_cached); + u32 nominal_perf = READ_ONCE(cpudata->nominal_perf); u64 value = prev; min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, @@ -536,6 +537,10 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, value &= ~AMD_CPPC_DES_PERF(~0L); value |= AMD_CPPC_DES_PERF(des_perf); + /* limit the max perf when core performance boost feature is disabled */ + if (!cpudata->boost_supported) + max_perf = min_t(unsigned long, nominal_perf, max_perf); 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X-Microsoft-Antispam-Message-Info: xe1LFl5KRvU3sIyqGWxlHZLY5Jglq6lRhTdKqMTwXNL9MJqipbmtF4tESM3W0LzvSRWcmHvJu7yWfK7WxLQZPY/5g72uRJr4yxwLMxG/5GEF1LbrVLrADI7olYn7x7X3vGG+lrNDc1Z5zok+rpfXZJUofiK0bHstBgSjmhW89e1gmVKv1u68pPM6alLRNiwGNUswlPmSlGpiSZmRN0s6k7KiKICt/xMuXJUAiaRf4uSnBWXKA0M+2l/horS0UlxKa8p1tJQzpxfXXM93Qs51cccHwZb6HP3W90cwY9S0Sq4VhJWGwSh8xpglUXldje0TNjPfcb0f398WaPVj4uEC7BHu/QFKOg1VEoLfIfcSz8C0ZYXbHb/m/0gPaZgCDF+Viy71euAKBB/01BPekrpxTO4SPsVYAY4lXRnRMU65iA8FUa+ybR87mvcT8G9z6kflhtprUV7OfOz6NogXwSwwfvqrm14QwR3aWzCBbxzXMYDk08SlVYxNnkUK+bN2LqpqHLhfDluPkWb5wvxQO8VDzGi5i7zlCix6uWniPimytCwRfr4arENsuX3HYzsBcPyuPdQ6O+XJyT9VD6rrJiS+KPIvwIgemDMRqRdKMbu/vqbebgsj33ws5873Yc6pD3pa4qOceVLnVP2wpTJ1aaD248WvyrlrJjsAK20GVqXHsWSRonoi7psWdha73ERmdcrvgSO61VWfsiWMbHKdld/Fm86GxLgrM5aTOYmSLwgjVwIb2NV3XoZ5nb3yRMSONTxHVaUwTyV85Oz1vCfnXHOmNs4bYaVB6Ry72y6lqaMYd8fv3LSK78ooNSQ01rj6Gjd/HmpEzismNcnmlEwMlJEeapKykxMM7SaIhtsS+OssmBRLHElsbeSW0e3KtwmbIOdFhC63zkqIct3SweeGFLLPqYyGQOfkMD4Keahau0jlkqQfGRJoKyJC/weEuYcHJI6ML0pXcRgmq3qLfIBAUMYREpVAW34CEpIABAC8LKlEt3j/5kwThNHHjQxalUd0ELOfENk0Yv95okn/jkIxMzpYjJ2npizJvFJ1L0TnKngnqrcuMv1hB2DMKiyEN7w+0YjmSwQ9UQ84aV78+yRmot0qaP9erax/v4PRAT4P3a9vFs+vULOfO5xdgJAfXDMhQYLe9+242E0LD0HvfY3I+cj+UIaGZuQvWDPxEEqHMeXpruvy0TTnHHLinHzOuz3nIhZoYNycGec9VytVnoV6s06BR3JZPcodXBw5u58EnFtVcebgON+LhascVlD1qy6u6sp+JlAKeSy0f1lIpiADLL0/otYlsDwI6wkYuTlxIcwzyLjlSmEePhc/ZHvDl0Q6Ph3y7Crw94XHJPpbacruKZayJWnOCOPiWCSZNlfLgABevL7UN9BIgSkJ8JnEJbwJvtzPQBZQLRGFZIY0DcwH326fAQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(36860700010)(1800799021)(376011)(82310400023);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 21:34:21.7256 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9c31f58b-b9ef-4553-349d-08dc94956958 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8527 From: Perry Yuan Updates the documentation in `amd-pstate.rst` to include information about the per CPU boost control feature. Users can now enable or disable the Core Performance Boost (CPB) feature on individual CPUs using the `boost` sysfs attribute. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- Documentation/admin-guide/pm/amd-pstate.rst | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index f5ee81419a93..d0324d44f548 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -281,6 +281,22 @@ integer values defined between 0 to 255 when EPP feature is enabled by platform firmware, if EPP feature is disabled, driver will ignore the written value This attribute is read-write. +``boost`` +The `boost` sysfs attribute provides control over the CPU core +performance boost, allowing users to manage the maximum frequency limitation +of the CPU. This attribute can be used to enable or disable the boost feature +on individual CPUs. + +When the boost feature is enabled, the CPU can dynamically increase its frequency +beyond the base frequency, providing enhanced performance for demanding workloads. +On the other hand, disabling the boost feature restricts the CPU to operate at the +base frequency, which may be desirable in certain scenarios to prioritize power +efficiency or manage temperature. + +To manipulate the `boost` attribute, users can write a value of `0` to disable the +boost or `1` to enable it, for the respective CPU using the sysfs path +`/sys/devices/system/cpu/cpuX/cpufreq/boost`, where `X` represents the CPU number. + Other performance and frequency values can be read back from ``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`. 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Wysocki" Subject: [PATCH v14 5/5] cpufreq: Only disable boost during cpu online when using frequency tables Date: Mon, 24 Jun 2024 16:34:00 -0500 Message-ID: <20240624213400.67773-6-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624213400.67773-1-mario.limonciello@amd.com> References: <20240624213400.67773-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|SA1PR12MB7246:EE_ X-MS-Office365-Filtering-Correlation-Id: 8f2339e0-38cf-4d9b-bb50-08dc9495699f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|376011|36860700010|82310400023|1800799021; X-Microsoft-Antispam-Message-Info: ev0BvDMRvflU/fwr2FQdT0oBI9jYhQIMNzXttgHGlCk/y3F1vIfW6mNl7d9ye8sQmrZ09/udkVpggNNIVeebnJVkqkDPX6EJnagz3iBcUKWewRKTidNBiK8Uu//oB761ChGKdAyCGFbE6/QdFVJ4giF4UGJZQJQhGGYsKJieNvAw6fUi1a0peYZ6rNx/aUrIWb5k4w2G9zlaob60IrnxegupfYwu8dx6vtSPYwmXL8+oBhkLUalyiam2zL2E4WveGlAx14O3T5Uy0DU+KLP2QO73pRXECUA8aioLQANeIXDyDgEGmBmSZ4FH/G5AVgvMvMdgCY/PGfW136EnliJsecSmcc6uKchjNYqPqmlO+jv+nZ8z8TNHRqza0LVwf8dsffA/9CR/iaDYxMVUFH/TKVysQKcijV6z4JpbaKPlpbsYL2hNg92tGhtSR8EV/OpVkY3HzSm/zT2t8Zq1X+lj5WeT9DOMYodfojTcCQmgnnoolXDszGN2wKi38IUA+FePjyK6/6bnayXTO6A/Ivy8bCjye9zlBL0QKxiNLm4IS0mbG5sTfgHU/jrZGRwh/DevP9EJ/0B2c+iKbvWWa0wiuihUs5wVxvoNT75RVXsP5IPquQXdZsyc54TphXEMxCHa6vKNdBVhKjWxyOXv25RumQOupC4ocaY8DNfdpEe1cd/rhTjfwS9w/9POwI/XWOrJYNDRnCJi7jRiGC16659HwUpnfARMs1w79g/L8aoJYE1Gy0TQFsSpa4O0Opy/zu2+O8UzdDro+SjT2Km0/3G7ft6Qw64oscAI5AOMLIjv0xaPJqysq2oH+O3OXA7giKeNhKih4kBpWeLb7ZX2Vqf2R4x0C55dwz1EUTkZmWtLK+5DoAAPEixoiAC3Y1357T4+RBQCHXacVwnMB14G0cZHb3ncrlBnRgrXngNUKLOTnTSRha7UEU3cJC+v6OEd8+J04XMbax5bL2lzYX1Q5FtRgHD2fB7kuI/mVXdYy1P7IB655belmz5abAtU0QTZSEKxBnnReyC1ExHrZvIx7kJxz+H4jHHpkThPS2EuFBq2i/DCg+I/vOKv2IimiIxiN8DIEHUpBz42FoNajZJATexvcurjypejoOyEakYtbnIE6/KJh4rH7qSHUEXOr54Vh7AIt2u5oUZ0mCikGAg0UJcYls7tbiiDP+iSyPgoNNA1SiPA92W4xZnd+hRCBv9Y0sgEo0E+FWQ5sbSXRtVHuxb7Bs6LnDC6vmeJ4m3pGdbragEyzJBJyZ/9suwkoxa2SDn0U1D7L17SesX8v2JUKHKFFKTkH0ArrjSK0jZnfmXeVRHtIpnOFTDX5U6njUP2iQ5eYJe+d8ufR6+C0KaUW+HonbmeOSxltWuRBRxwSgr/1wUDn5naPXXKI3u5e5EhOmvcwCqQs4xjPZImcp+Nya8UkQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(376011)(36860700010)(82310400023)(1800799021);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 21:34:22.1944 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f2339e0-38cf-4d9b-bb50-08dc9495699f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7246 The behavior introduced in commit f37a4d6b4a2c ("cpufreq: Fix per-policy boost behavior on SoCs using cpufreq_boost_set_sw()") sets up the boost policy incorrectly when boost has been enabled by the platform firmware initially even if a driver sets the policy up. This is because there are no discrete entries in the frequency table. Update that code to only run when a frequency table is present. Fixes: f37a4d6b4a2c ("cpufreq: Fix per-policy boost behavior on SoCs using cpufreq_boost_set_sw()") Signed-off-by: Mario Limonciello --- Cc: Sibi Sankar Cc: Dietmar Eggemann Cc: Viresh Kumar Cc: Dhruva Gole Cc: Yipeng Zou Cc: Rafael J. Wysocki drivers/cpufreq/cpufreq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 1fdabb660231..32c119614710 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -1430,7 +1430,8 @@ static int cpufreq_online(unsigned int cpu) } /* Let the per-policy boost flag mirror the cpufreq_driver boost during init */ - policy->boost_enabled = cpufreq_boost_enabled() && policy_has_boost_freq(policy); + if (policy->freq_table) + policy->boost_enabled = cpufreq_boost_enabled() && policy_has_boost_freq(policy); /* * The initialization has succeeded and the policy is online.