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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 1/2] mlxsw: pci: Store number of scatter/gather entries for maximum packet size Date: Tue, 25 Jun 2024 15:47:34 +0200 Message-ID: <98c3e3adb7e727e571ac538faf67cef262cec4fc.1719321422.git.petrm@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013B:EE_|BY5PR12MB4211:EE_ X-MS-Office365-Filtering-Correlation-Id: dc59554f-2625-4a11-02de-08dc951d771a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|82310400023|1800799021|36860700010|376011; X-Microsoft-Antispam-Message-Info: Y/a6YB6u7tGW6KQo6o4aMSJazK9iS2Ch8I10SQXK1pus4UkZ/BSzAn/fWxD3iGBDWLVpApuJamf2F/EuGIU5bDZ4Ts8eZGem9EuNBP7gHAabWero5z1tH5fIz+3PnXGGU9PVFst6elt0hiico34ZIAYGP+ax/aVuLMAsF20dMV1fsU3kUhJGa6o7OWbAjSqjnywgJtZXDq3hQn1gP133U1US3VSKhDE6aUUuvanJmdpu3X+FdWwV2I4pROGRwxClvHWfs6/J9vDxbfTD5KGSNesNe5THO9cQTnL/iy9pRTllQM2ai7KN6TEk/pr+cbDjiS+GwWvly5cQ9RpfQbfIg1XhNPKUFCEcFRShMJqrEP7KyyHKtBHaMw5xNhbwIbhE4SgVhnW32Wbgz6f/iphuf8J2U1Yva9edCiPOzwHYPaU6o9Ptp6Z4HRVjgdjmiGuGmYFmiMbrAH3U5T3u/P0R6P3cGTmC6fnw1cySOb7uLntJeUhy6wYhIxWABAD1/lC0KIZwr3CzZBkxL99bhlURCtp5gXiySRwYORiRRt5fKMjAxj/clQIUCM58npYLUYm3fqHeB7Jbixz1Ow3XJE7eTjd2uehDKxRejCRqieJEEOnc6CjDj7/SGrLQDM9Mn14NYNll+Eki34g5ZYdD5k4vYILpr3UDhM/o3IkaQs3yjoLQJO5A1SLQgSC8/dHMeL8qBw5AdVbdYq4UPts6s6LhL3Rfgl0OMTN6rIz/l2vjxHq02/AECVH2nGAwYFNIdb9aUjaaeMN44+ONtDPXgSrlw4fRQujWwAI7azyDVD95iO2+rZpx0UXZ8GWUtfDM7vRYK+zQOhG/CuiCzGvn6gQmOvK2UdRVN8mIRb5ou/ppG9VvkjqahoNXjctEBmDWqGyOMXjQNPcp1tUNvWO/ISwv/rGCIQ/B3DxhYJPDoG35Xu5jMpn769Q8yqsOcQEo1VImwrqGnYUMUCKC/D3P8CM+CjQCJ37ILVbrauxtfLJZPE7D8yFeoxiXnLwMcB521Uz3CCvS/wglWLVaIfM9+H10EdsDO9dygfwlUgrbzXhr4U77VJ5FfaUqx2z9acSGSng1YybdH1R4h08a14/zMqiMSnPpXV9g0KaliTYQxY4BNr1ct3UYyUXMUvS1Fskv+8CJ9kvIMCb61WvRLh/PNuq99H/0dTDj2zqXGvQkf5m9xJ0wYyU5lmjvG/A2v3DP3tgzbxRpa9QoPNlMRQJEPaiNIp/FlGDFt1PLyYSjWsIpg5k2Vnns1Kaf9EZB77kv7b9n4GFwuc8v07k8FY4mBMzdHpki39ziHHF5csEk9WLpDIJ1Qmm3UIzaEC8wXk6wy0bshdcg0q3xE+dc4QVHT7imVozxcuaaeCon+dTK467eO6joklqzlnTz3dngQaC+RZLFA7YxXJY69j+xqGVkLL00tA== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230037)(82310400023)(1800799021)(36860700010)(376011);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jun 2024 13:48:16.2988 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dc59554f-2625-4a11-02de-08dc951d771a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4211 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen A previous patch-set used page pool for Rx buffers allocations. To simplify the change, we first used page pool for one allocation per packet - one continuous buffer is allocated for each packet. This can be improved by using fragmented buffers, then memory consumption will be significantly reduced. WQE (Work Queue Element) includes up to 3 scatter/gather entries for data. As preparation for fragmented buffer usage, calculate number of scatter/gather entries which are required for packet according to maximum MTU and store it for future use. For now use PAGE_SIZE for each entry, which means that maximum buffer size is 3 * PAGE_SIZE. This is enough for the maximum MTU which is supported in the driver now (10K). Warn in an unlikely case of maximum MTU which requires more than 3 pages, for now this warn should not happen with standard page size (>=4K) and maximum MTU (10K). Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 2fe29dba8751..0492013aca18 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -111,6 +111,7 @@ struct mlxsw_pci { bool cff_support; enum mlxsw_cmd_mbox_config_profile_lag_mode lag_mode; enum mlxsw_cmd_mbox_config_profile_flood_mode flood_mode; + u8 num_sg_entries; /* Number of scatter/gather entries for packets. */ struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT]; u32 doorbell_offset; struct mlxsw_core *core; @@ -427,6 +428,12 @@ static void mlxsw_pci_rdq_page_free(struct mlxsw_pci_queue *q, page_pool_put_page(cq->u.cq.page_pool, elem_info->page, -1, false); } +static u8 mlxsw_pci_num_sg_entries_get(u16 byte_count) +{ + return DIV_ROUND_UP(byte_count + MLXSW_PCI_RX_BUF_SW_OVERHEAD, + PAGE_SIZE); +} + static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, struct mlxsw_pci_queue *q) { @@ -1786,6 +1793,17 @@ static void mlxsw_pci_free_irq_vectors(struct mlxsw_pci *mlxsw_pci) pci_free_irq_vectors(mlxsw_pci->pdev); } +static void mlxsw_pci_num_sg_entries_set(struct mlxsw_pci *mlxsw_pci) +{ + u8 num_sg_entries; + + num_sg_entries = mlxsw_pci_num_sg_entries_get(MLXSW_PORT_MAX_MTU); + mlxsw_pci->num_sg_entries = min(num_sg_entries, + MLXSW_PCI_WQE_SG_ENTRIES); + + WARN_ON(num_sg_entries > MLXSW_PCI_WQE_SG_ENTRIES); +} + static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, const struct mlxsw_config_profile *profile, struct mlxsw_res *res) @@ -1908,6 +1926,8 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, if (err) goto err_requery_resources; + mlxsw_pci_num_sg_entries_set(mlxsw_pci); + err = mlxsw_pci_napi_devs_init(mlxsw_pci); if (err) goto err_napi_devs_init; From patchwork Tue Jun 25 13:47:35 2024 Content-Type: text/plain; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 2/2] mlxsw: pci: Use fragmented buffers Date: Tue, 25 Jun 2024 15:47:35 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000141:EE_|DM4PR12MB5940:EE_ X-MS-Office365-Filtering-Correlation-Id: 89f86d61-bc2b-48c6-6bae-08dc951d7b8c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|82310400023|376011|1800799021|36860700010; X-Microsoft-Antispam-Message-Info: kJ4ERcBgVXl7Vl0G97kaokZz+mvP/vnM2UuORq52UiwD57nyYWzPwbMMupzUdK1BqH2S5MdHXi8t9q5bS1s2MuUG9JPPHh/sviEC5MwNGcyenibbF2LxcFkQwh8Xr65P5m/0Rv3jvlFDfBum/Hq4YqScAtcSt4scK9G61NGHK4XFWUiUakqpWidNHydqJfIwZZ6DWp5EfmWZepVajo44IF9994/02siAMklodePALb9nrhTTKcgwsML+CLtI4yrNaiSvqHZMHdwzTOFJtIdleJ4oCrMIdi8Snsdxb9KAB5sTouKO9jTHo3qVTVTRX12mmAVp8Jxw0KeLVx0oLcq/+sLYL20gc1SbR4bzzjR0ejhHeRcgCNaQtk2+rx/0rU+DFT2CFj1nwJiXGvuqxs3WlShAOjv8z5TuyYRj8GOAosjiJo0N+iu65VSkMeXuV4ByQJpoh4qpOve9ahvD6HZ/3SkpEuJ9yzoRMwhkLDLnzGRQNKRWuvaBbNC7y/plEZz3+L2ZTzz1G830KStEy90Taf8IMfO+rmrYZBrN9ceimFGnViVWiQa3te0IZ89c7cOg3wxruvOqxbXvlBqxPE/hVowzj8mWBDB8dj8yY/ZJMyi2az7PWksDFVS9WkTVkQzubZslMOWakvPK7YH+aqORgxsUE7RzvfO+AIoqjVyypOnmaxTMUba2l2ScpNtojkSIaQZ+hrxeMF6VJL1RFQcB8+A2YstTZqT0Hjghh/gi2LPajYUDCzMci6SstYQReN7vgQYA8U/D40WmZD0wvkI4VzYx/ceO99TJB2EqtfERWvRzl7T2F8obu6IVSQCDM1MW+0eXVEQnwORlWHX7obM4FjIxoqhlcu5FQmONJCoHGkhPkIdncBKnn4jwQVedC2BwUnYAt53oGmIGmTOAvJrNwbOM/4f1LT1FMleazRyTW7D0hIGSkCoU3QFZ3oq1HuKD16XE2MWhDuFIwS+9fFH3aC4AKWE2jDyqE5y/C0iXrZr9oB6OJ64xRWMRcs+eySE7i8CVlAvnVggIle0z69vx8cU8I4mFmEke43i4kwXT5k/Xy+CLDSgN4SSMsVWFv6Hs3LHUAqu1E7IV7sbZjIMBCa5+9+s0PcGi1G39Ib25UPHP8G8/iYkHlyUnyABgm8hGbbqCE5RmypVexUJhhX0gF/kuKqaYTl5YopEfXyu2wDWt4ZJxxKtwhuSNZ+s+ZFVDckJ6ZRyiJPJnxmEGa2U2JgZUB68A8bu2XWIBy6g0vkw/YYiZgwgUP017wclQA1/wDUELogE80qteBTCjOdrtY0rrO81wn86fralARRJVW99hfXDJL1ATKzYzXVhbD37v4lD5xliPqkJDra6LrtsJpHty/b7g31ep93SjqXXEKevbcrP/lsk8BjuEqgPI97sAI4nUQlJKzHtE+wwnGarILg== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230037)(82310400023)(376011)(1800799021)(36860700010);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jun 2024 13:48:23.7595 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 89f86d61-bc2b-48c6-6bae-08dc951d7b8c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000141.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5940 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen WQE (Work Queue Element) includes 3 scatter/gather entries for buffers. The buffer can be split into 3 parts, software should set address and byte count of each part. A previous patch-set used page pool to allocate buffers, to simplify the change, we first used one continuous buffer, which was allocated with order > 0. This patch improves page pool usage to allocate the exact number of pages which are required for packet. As part of init, fill WQE.address[x] and WQE.byte_count* with pages which are allocated from the pool. Fill x entries according to number of scatter/gather entries which are required for maximum packet size. When a packet is received, check the actual size and replace only the used pages. Save bytes for software overhead only as part of the first entry. This change also requires using fragmented SKB, till now all the buffer was in the linear part. Note that 'skb->truesize' is decreased for small packets. For now the maximum buffer size is 3 * PAGE_SIZE which is enough, in case that the driver will support larger MTU, we can use 'order' to allocate more than one page per scatter/gather entry. This change significantly reduces memory consumption of mlxsw driver. The footprint is reduced by 26%. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 163 +++++++++++++++++----- 1 file changed, 129 insertions(+), 34 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 0492013aca18..0320dabd1380 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -62,7 +62,7 @@ struct mlxsw_pci_mem_item { }; struct mlxsw_pci_queue_elem_info { - struct page *page; + struct page *pages[MLXSW_PCI_WQE_SG_ENTRIES]; char *elem; /* pointer to actual dma mapped element mem chunk */ struct { struct sk_buff *skb; @@ -350,7 +350,11 @@ mlxsw_pci_wqe_rx_frag_set(struct mlxsw_pci *mlxsw_pci, struct page *page, dma_addr_t mapaddr; mapaddr = page_pool_get_dma_addr(page); - mapaddr += MLXSW_PCI_SKB_HEADROOM; + + if (index == 0) { + mapaddr += MLXSW_PCI_SKB_HEADROOM; + frag_len = frag_len - MLXSW_PCI_RX_BUF_SW_OVERHEAD; + } mlxsw_pci_wqe_address_set(wqe, index, mapaddr); mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len); @@ -385,29 +389,56 @@ static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe, dma_unmap_single(&pdev->dev, mapaddr, frag_len, direction); } -static struct sk_buff *mlxsw_pci_rdq_build_skb(struct page *page, +static struct sk_buff *mlxsw_pci_rdq_build_skb(struct page *pages[], u16 byte_count) { - void *data = page_address(page); - unsigned int allocated_size; + unsigned int linear_data_size; struct sk_buff *skb; + int page_index = 0; + bool linear_only; + void *data; + data = page_address(pages[page_index]); net_prefetch(data); - allocated_size = page_size(page); - skb = napi_build_skb(data, allocated_size); + + skb = napi_build_skb(data, PAGE_SIZE); if (unlikely(!skb)) return ERR_PTR(-ENOMEM); + linear_only = byte_count + MLXSW_PCI_RX_BUF_SW_OVERHEAD <= PAGE_SIZE; + linear_data_size = linear_only ? byte_count : + PAGE_SIZE - + MLXSW_PCI_RX_BUF_SW_OVERHEAD; + skb_reserve(skb, MLXSW_PCI_SKB_HEADROOM); - skb_put(skb, byte_count); + skb_put(skb, linear_data_size); + + if (linear_only) + return skb; + + byte_count -= linear_data_size; + page_index++; + + while (byte_count > 0) { + unsigned int frag_size; + struct page *page; + + page = pages[page_index]; + frag_size = min(byte_count, PAGE_SIZE); + skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, + page, 0, frag_size, PAGE_SIZE); + byte_count -= frag_size; + page_index++; + } + return skb; } static int mlxsw_pci_rdq_page_alloc(struct mlxsw_pci_queue *q, - struct mlxsw_pci_queue_elem_info *elem_info) + struct mlxsw_pci_queue_elem_info *elem_info, + int index) { struct mlxsw_pci_queue *cq = q->u.rdq.cq; - size_t buf_len = MLXSW_PORT_MAX_MTU; char *wqe = elem_info->elem; struct page *page; @@ -415,17 +446,19 @@ static int mlxsw_pci_rdq_page_alloc(struct mlxsw_pci_queue *q, if (unlikely(!page)) return -ENOMEM; - mlxsw_pci_wqe_rx_frag_set(q->pci, page, wqe, 0, buf_len); - elem_info->page = page; + mlxsw_pci_wqe_rx_frag_set(q->pci, page, wqe, index, PAGE_SIZE); + elem_info->pages[index] = page; return 0; } static void mlxsw_pci_rdq_page_free(struct mlxsw_pci_queue *q, - struct mlxsw_pci_queue_elem_info *elem_info) + struct mlxsw_pci_queue_elem_info *elem_info, + int index) { struct mlxsw_pci_queue *cq = q->u.rdq.cq; - page_pool_put_page(cq->u.cq.page_pool, elem_info->page, -1, false); + page_pool_put_page(cq->u.cq.page_pool, elem_info->pages[index], -1, + false); } static u8 mlxsw_pci_num_sg_entries_get(u16 byte_count) @@ -434,6 +467,64 @@ static u8 mlxsw_pci_num_sg_entries_get(u16 byte_count) PAGE_SIZE); } +static int +mlxsw_pci_elem_info_pages_ref_store(const struct mlxsw_pci_queue *q, + const struct mlxsw_pci_queue_elem_info *el, + u16 byte_count, struct page *pages[], + u8 *p_num_sg_entries) +{ + u8 num_sg_entries; + int i; + + num_sg_entries = mlxsw_pci_num_sg_entries_get(byte_count); + if (WARN_ON_ONCE(num_sg_entries > q->pci->num_sg_entries)) + return -EINVAL; + + for (i = 0; i < num_sg_entries; i++) + pages[i] = el->pages[i]; + + *p_num_sg_entries = num_sg_entries; + return 0; +} + +static int +mlxsw_pci_rdq_pages_alloc(struct mlxsw_pci_queue *q, + struct mlxsw_pci_queue_elem_info *elem_info, + u8 num_sg_entries) +{ + struct page *old_pages[MLXSW_PCI_WQE_SG_ENTRIES]; + struct mlxsw_pci_queue *cq = q->u.rdq.cq; + int i, err; + + for (i = 0; i < num_sg_entries; i++) { + old_pages[i] = elem_info->pages[i]; + err = mlxsw_pci_rdq_page_alloc(q, elem_info, i); + if (err) { + dev_err_ratelimited(&q->pci->pdev->dev, "Failed to alloc page\n"); + goto err_page_alloc; + } + } + + return 0; + +err_page_alloc: + for (i--; i >= 0; i--) + page_pool_recycle_direct(cq->u.cq.page_pool, old_pages[i]); + + return err; +} + +static void +mlxsw_pci_rdq_pages_recycle(struct mlxsw_pci_queue *q, struct page *pages[], + u8 num_sg_entries) +{ + struct mlxsw_pci_queue *cq = q->u.rdq.cq; + int i; + + for (i = 0; i < num_sg_entries; i++) + page_pool_recycle_direct(cq->u.cq.page_pool, pages[i]); +} + static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, struct mlxsw_pci_queue *q) { @@ -441,7 +532,7 @@ static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, u8 sdq_count = mlxsw_pci->num_sdqs; struct mlxsw_pci_queue *cq; u8 cq_num; - int i; + int i, j; int err; q->producer_counter = 0; @@ -472,9 +563,12 @@ static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, for (i = 0; i < q->count; i++) { elem_info = mlxsw_pci_queue_elem_info_producer_get(q); BUG_ON(!elem_info); - err = mlxsw_pci_rdq_page_alloc(q, elem_info); - if (err) - goto rollback; + + for (j = 0; j < mlxsw_pci->num_sg_entries; j++) { + err = mlxsw_pci_rdq_page_alloc(q, elem_info, j); + if (err) + goto rollback; + } /* Everything is set up, ring doorbell to pass elem to HW */ q->producer_counter++; mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); @@ -485,7 +579,9 @@ static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, rollback: for (i--; i >= 0; i--) { elem_info = mlxsw_pci_queue_elem_info_get(q, i); - mlxsw_pci_rdq_page_free(q, elem_info); + for (j--; j >= 0; j--) + mlxsw_pci_rdq_page_free(q, elem_info, j); + j = mlxsw_pci->num_sg_entries; } q->u.rdq.cq = NULL; cq->u.cq.dq = NULL; @@ -498,12 +594,13 @@ static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci, struct mlxsw_pci_queue *q) { struct mlxsw_pci_queue_elem_info *elem_info; - int i; + int i, j; mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); for (i = 0; i < q->count; i++) { elem_info = mlxsw_pci_queue_elem_info_get(q, i); - mlxsw_pci_rdq_page_free(q, elem_info); + for (j = 0; j < mlxsw_pci->num_sg_entries; j++) + mlxsw_pci_rdq_page_free(q, elem_info, j); } } @@ -637,11 +734,11 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, enum mlxsw_pci_cqe_v cqe_v, char *cqe) { struct pci_dev *pdev = mlxsw_pci->pdev; + struct page *pages[MLXSW_PCI_WQE_SG_ENTRIES]; struct mlxsw_pci_queue_elem_info *elem_info; - struct mlxsw_pci_queue *cq = q->u.rdq.cq; struct mlxsw_rx_info rx_info = {}; struct sk_buff *skb; - struct page *page; + u8 num_sg_entries; u16 byte_count; int err; @@ -654,18 +751,19 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, if (mlxsw_pci_cqe_crc_get(cqe_v, cqe)) byte_count -= ETH_FCS_LEN; - page = elem_info->page; + err = mlxsw_pci_elem_info_pages_ref_store(q, elem_info, byte_count, + pages, &num_sg_entries); + if (err) + goto out; - err = mlxsw_pci_rdq_page_alloc(q, elem_info); - if (err) { - dev_err_ratelimited(&pdev->dev, "Failed to alloc page\n"); + err = mlxsw_pci_rdq_pages_alloc(q, elem_info, num_sg_entries); + if (err) goto out; - } - skb = mlxsw_pci_rdq_build_skb(page, byte_count); + skb = mlxsw_pci_rdq_build_skb(pages, byte_count); if (IS_ERR(skb)) { dev_err_ratelimited(&pdev->dev, "Failed to build skb for RDQ\n"); - page_pool_recycle_direct(cq->u.cq.page_pool, page); + mlxsw_pci_rdq_pages_recycle(q, pages, num_sg_entries); goto out; } @@ -886,15 +984,12 @@ static int mlxsw_pci_cq_page_pool_init(struct mlxsw_pci_queue *q, struct page_pool_params pp_params = {}; struct mlxsw_pci *mlxsw_pci = q->pci; struct page_pool *page_pool; - u32 max_pkt_size; if (cq_type != MLXSW_PCI_CQ_RDQ) return 0; - max_pkt_size = MLXSW_PORT_MAX_MTU + MLXSW_PCI_RX_BUF_SW_OVERHEAD; - pp_params.order = get_order(max_pkt_size); pp_params.flags = PP_FLAG_DMA_MAP; - pp_params.pool_size = MLXSW_PCI_WQE_COUNT; + pp_params.pool_size = MLXSW_PCI_WQE_COUNT * mlxsw_pci->num_sg_entries; pp_params.nid = dev_to_node(&mlxsw_pci->pdev->dev); pp_params.dev = &mlxsw_pci->pdev->dev; pp_params.napi = &q->u.cq.napi;