From patchwork Tue Jun 25 18:28:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13711804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 194C9C3064D for ; Tue, 25 Jun 2024 18:28:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D8AAA10E712; Tue, 25 Jun 2024 18:28:20 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="VrKTT9mW"; dkim-atps=neutral Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9285710E70C for ; Tue, 25 Jun 2024 18:28:18 +0000 (UTC) Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-57cbc66a0a6so795498a12.1 for ; Tue, 25 Jun 2024 11:28:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719340096; x=1719944896; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+yADUGBbAdhXuD84OjuP9zRnfHxvH4zqLq8CnILlnOI=; b=VrKTT9mWY/BA6bjFlcUXU5klFrtDqQ7U0OGySRvlFAegUyi4tlYaZv7U8miA3e0Tce dGAMGDGETJ2yZYwb/ViYuCwZnoqugvpHiewCFnVKJnwQc7f2FjaQBee5WOl8SVkZbN0V qxyDQ74/nw38lzVZQHU/NKCDj9EjSgqea34Gx0OoRj9PC9ZobqVGUEeWivyhd6npm0ZA cg4Y4zDaM+dgAazJw2C611d5CV7AKQDif6cGDUluvLIYyFDwbFeHwYSksRPQRK6h4Z5n 6Gh8w3kCsVIiR4bsPZGTBqi465Wxed0VduTivhZKkuhlzIxmMo1GDf3oFltIyKiC4Uqs i8zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719340096; x=1719944896; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+yADUGBbAdhXuD84OjuP9zRnfHxvH4zqLq8CnILlnOI=; b=KIEtfALjt517qwVU3ZpB22RnWsmFRe20eHiycsi2PhyqnpjxkAFsCNfmi+yDxsDCq9 BMCHCfsyvl0ZaUQTXqGuWYYlfrGaVfDkCDqA50MaHzCHiDYloLcVdKi5AeaztdAssre8 +st9R5RnN2fhIs0LSxH2CTy/H6bRw3oPNNrYE3X/4hRHe5RKPqF/yltbTUmCgGYTlvZT Q47ykdhYC/3xjemSf9a/4SOkx4oq/MbzvGY1+MyliAl0xbHkIZaTFa+eZyT5gLBL4exy 5OPvI6f213qrD6Sz4GHmO+m+HQuTXQK4rYJWl14cORDNLwca+vDgm8yfcx41ZQhd3Nkm KuMg== X-Forwarded-Encrypted: i=1; AJvYcCXxupUJGUFyCgI5i9RPXWLDp6emblvGwBPUUQjRhcCy+GCtmYX+CRzvFB55XSuduUonR3RVTuNQu8fRY7fHLMyT67zrKN+YLDEoWl5DYNRI X-Gm-Message-State: AOJu0YwjKfjNi6bzCOEAHJn1urPcd6qLDowr5Wq4g1a/W8A5IJU2UeAD tQO4EfDWzmyDA37MgQPW6GoDTVFLPr368efM2myY9DBbrHi+p8BSKUKYrUFQDyosVHcuilJODGE 1tyQ= X-Google-Smtp-Source: AGHT+IH5VYxYSwpjM0Vapx9UDYprAb5dwLcxWqrJwT/uTDdtLO3ybGWR46gNVWskxHlg7YIqFqhZPg== X-Received: by 2002:a05:6402:184b:b0:57c:6b49:aef with SMTP id 4fb4d7f45d1cf-57d4483b0ffmr7550161a12.11.1719340096239; Tue, 25 Jun 2024 11:28:16 -0700 (PDT) Received: from [192.168.215.29] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:15 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jun 2024 20:28:06 +0200 Subject: [PATCH v4 1/5] drm/msm/adreno: Implement SMEM-based speed bin MIME-Version: 1.0 Message-Id: <20240625-topic-smem_speedbin-v4-1-f6f8493ab814@linaro.org> References: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> In-Reply-To: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=5838; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ZXaBkJpkEi6I9lto/tGjByodIdA+A4HUW8SYjctW8+0=; b=7EbrsfA01bwk4JX0dOd021Lq44oCnoz/hsE+x15jRkJm2+pP6b+4RD6RGaveF7IiCeVYhv9SI SWjs8yQ7sFHB8vwYlQX3GdafSYlma2n1DeBvzX4tRAgsx9JkhGEoXpu X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is abstracted through SMEM, instead of being directly available in a fuse. Add support for SMEM-based speed binning, which includes getting "feature code" and "product code" from said source and parsing them to form something that lets us match OPPs against. Due to the product code being ignored in the context of Adreno on production parts (as of SM8650), hardcode it to SOCINFO_PC_UNKNOWN. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 41 +++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++++- 4 files changed, 50 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c98cdb1e9326..8ace096bb68c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2124,13 +2124,15 @@ static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) return UINT_MAX; } -static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) +static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, + struct device *dev, + const struct adreno_info *info) { u32 supp_hw; u32 speedbin; int ret; - ret = adreno_read_speedbin(dev, &speedbin); + ret = adreno_read_speedbin(adreno_gpu, dev, &speedbin); /* * -ENOENT means that the platform doesn't support speedbin which is * fine @@ -2290,7 +2292,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); - ret = a6xx_set_supported_hw(&pdev->dev, config->info); + ret = a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); if (ret) { a6xx_llc_slices_destroy(a6xx_gpu); kfree(a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 1e789ff6945e..e514346088f9 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -6,6 +6,8 @@ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. */ +#include + #include "adreno_gpu.h" bool hang_debug = false; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 1c6626747b98..6ffd02f38499 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -21,6 +21,9 @@ #include "msm_gem.h" #include "msm_mmu.h" +#include +#include + static u64 address_space_size = 0; MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space"); module_param(address_space_size, ullong, 0600); @@ -1061,9 +1064,39 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) adreno_ocmem->hdl); } -int adreno_read_speedbin(struct device *dev, u32 *speedbin) +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *fuse) { - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + u32 fcode; + int ret; + + /* + * Try reading the speedbin via a nvmem cell first + * -ENOENT means "no nvmem-cells" and essentially means "old DT" or + * "nvmem fuse is irrelevant", simply assume it's fine. + */ + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", fuse); + if (!ret) + return 0; + else if (ret != -ENOENT) + return dev_err_probe(dev, ret, "Couldn't read the speed bin fuse value\n"); + +#ifdef CONFIG_QCOM_SMEM + /* + * Only check the feature code - the product code only matters for + * proto SoCs unavailable outside Qualcomm labs, as far as GPU bin + * matching is concerned. + * + * Ignore EOPNOTSUPP, as not all SoCs expose this info through SMEM. + */ + ret = qcom_smem_get_feature_code(&fcode); + if (!ret) + *fuse = ADRENO_SKU_ID(fcode); + else if (ret != -EOPNOTSUPP) + return dev_err_probe(dev, ret, "Couldn't get feature code from SMEM\n"); +#endif + + return 0; } int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, @@ -1102,9 +1135,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) + if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) speedbin = 0xffff; - adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); + adreno_gpu->speedbin = speedbin; gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index cff8ce541d2c..563c08b44624 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -79,6 +79,10 @@ struct adreno_reglist { struct adreno_speedbin { uint16_t fuse; +/* As of SM8650, PCODE on production SoCs is meaningless wrt the GPU bin */ +#define ADRENO_SKU_ID_FCODE GENMASK(15, 0) +#define ADRENO_SKU_ID(fcode) (fcode) + uint16_t speedbin; }; @@ -545,7 +549,8 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); -int adreno_read_speedbin(struct device *dev, u32 *speedbin); +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *speedbin); /* * For a5xx and a6xx targets load the zap shader that is used to pull the GPU From patchwork Tue Jun 25 18:28:07 2024 Content-Type: text/plain; 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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:17 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jun 2024 20:28:07 +0200 Subject: [PATCH v4 2/5] drm/msm/adreno: Add speedbin data for SM8550 / A740 MIME-Version: 1.0 Message-Id: <20240625-topic-smem_speedbin-v4-2-f6f8493ab814@linaro.org> References: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> In-Reply-To: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=1481; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=pgXB3ku76GP+Ynds4TGlmCZD8EhfvV2JMzgzNC6TMuc=; b=4pAQCD48WMIG4yPsA0ws8Nht+e2p4Y2ez7R8+XZVKTh1CmihZSf2KTi89K6tp6SMOv2htCcc3 eDOPlXUrflcDo3HEbFZc5BtkIKqfE7vvJ9frwICe6+2ScwBiA3Jwcrx X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add speebin data for A740, as found on SM8550 and derivative SoCs. For non-development SoCs it seems that "everything except FC_AC, FC_AF should be speedbin 1", but what the values are for said "everything" are not known, so that's an exercise left to the user.. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 53e33ff78411..8f280d69ba71 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -11,6 +11,9 @@ #include "a6xx.xml.h" #include "a6xx_gmu.xml.h" +#include +#include + static const struct adreno_reglist a612_hwcg[] = { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, @@ -1208,6 +1211,11 @@ static const struct adreno_info a7xx_gpus[] = { .protect = &a730_protect, }, .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + { ADRENO_SKU_ID(SOCINFO_FC_AC), 0 }, + { ADRENO_SKU_ID(SOCINFO_FC_AF), 0 }, + /* Other feature codes (on prod SoCs) should match to speedbin 1 */ + ), }, { .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ .family = ADRENO_7XX_GEN3, From patchwork Tue Jun 25 18:28:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13711806 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88FE4C30658 for ; Tue, 25 Jun 2024 18:28:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1793F10E71B; Tue, 25 Jun 2024 18:28:27 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="JXYKhq6y"; dkim-atps=neutral Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7275D10E714 for ; Tue, 25 Jun 2024 18:28:22 +0000 (UTC) Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-57cb9a370ddso6878037a12.1 for ; Tue, 25 Jun 2024 11:28:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719340100; x=1719944900; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xNl1LGe+OUBjKkWza/syUNm4iRQsXOqi9TzG6uI03xo=; b=JXYKhq6yHiLwRq5IbWI65o2jhf753Wznjw8G5Nbyxjt9YRwvWErrTC26i0R4EOQRcR Jzk/4gqUezFYdzzO6q/oWWxF8BGLkp7aquh//KjTZXF3kGQsI6UMoqLpatyscmUToTeD UxDGy4cBtWQEyQVL0CY+NKaBbMAc5Hg4YIiiJrCnURdsBePkuM9Ix7Ow94aIfxncjJWJ q0B9ZLhixPTYArOiU9AsG/VmkjbEaU2aWhwgVuvgH+XJ86Y8eqp+KQk9LSWsRu10CRVM tDD4hnS3Q0BvXjI4PvZYmUrkzD6A5FBNv7/Kci1jV/XPZQDpybRIfdqVlx7THmDuIM94 wRbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719340100; x=1719944900; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xNl1LGe+OUBjKkWza/syUNm4iRQsXOqi9TzG6uI03xo=; b=SuTpzUl6IGi1VUeCkXla0s3EtiQV4Zi4V8xJEpONqAJTe2789lDzYbkClrSPzIkDjo uJDfooVZ6rIbhCsqT10XRsIT7Rg87Nj4luOY8kFny2/lQoSRilKwIjWG+yM2XG5fWo5B 7F41QG/5i3B7iwBbL5/sH5PqB11daS0aONysEc+Hub2EPmiBCsva0z8Cru4g3p4yFqcy d8IRiqM+q1taEKE9O4dI+vWQJG4gVU1Uz6sOBU/qQ6xFta5Q2W7opkBphlnGFXWM3Sx5 fyJd42MpM2yQvFgvrW6Bs7AfjLMpYpRw623UBaqBWCY2ujbXHKe+b4Q/brp53TTIY6cd PS4A== X-Forwarded-Encrypted: i=1; AJvYcCWZ40os8uE5VQxahtjq4GQZuuY57QD+xfUGsn6VpeY8v/3JYA0UG7ZnFAnZNcmT0FapDS7TEAxAXBVe1ncwTIhZhKUsXTYcB8v/yDxSv9ur X-Gm-Message-State: AOJu0YzmKJRiNk3bKBnsYIwG0KSR8ld0QT+e3eRhmHz4CqPVCTCjvFhz DlPC205VQ9nS7sljzwJzaHeK4LBK6fBm3HOHCYXDseTKjtoAhXw1Re7bvKv1Cd1P9Y6KQQDzjPn k+RE= X-Google-Smtp-Source: AGHT+IFZf75V6EVKFoeMMT86fpiVICPajQFEHJC9qNUtbTjyoSjlwEE+EJZ1PD+TboCYI1SSsb8bUw== X-Received: by 2002:aa7:d393:0:b0:57d:5600:2c94 with SMTP id 4fb4d7f45d1cf-57d56003448mr5183567a12.0.1719340100400; Tue, 25 Jun 2024 11:28:20 -0700 (PDT) Received: from [192.168.215.29] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:20 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jun 2024 20:28:08 +0200 Subject: [PATCH v4 3/5] drm/msm/adreno: Define A530 speed bins explicitly MIME-Version: 1.0 Message-Id: <20240625-topic-smem_speedbin-v4-3-f6f8493ab814@linaro.org> References: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> In-Reply-To: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=874; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hlAsvCKJeJlsvCjk6T4iu/SvTfq4qoydQ2dHeLtqkkA=; b=IRMR1HRLN2YRjxVqz6xKwmuxF680eWYXDX4vQzB+gFNVfylWuVcDos2bQwzKA7wmZ4U3gJ32x gg7nzrlgLmLBSFRvmSiO2FyHkPwIZb+ULPTqUvjdw9Y1u9Ob9HaCm+V X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In preparation for commonizing the speedbin handling code. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c index 455a953dee67..c98ad4ea558c 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c @@ -116,6 +116,12 @@ static const struct adreno_info a5xx_gpus[] = { ADRENO_QUIRK_FAULT_DETECT_MASK, .init = a5xx_gpu_init, .zapfw = "a530_zap.mdt", + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + { 2, 2 }, + { 3, 3 }, + ), }, { .chip_ids = ADRENO_CHIP_IDS(0x05040001), .family = ADRENO_5XX, From patchwork Tue Jun 25 18:28:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13711808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B157C3064D for ; Tue, 25 Jun 2024 18:28:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2FBE010E720; Tue, 25 Jun 2024 18:28:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="jo05gKK2"; dkim-atps=neutral Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4A03B10E71D for ; Tue, 25 Jun 2024 18:28:24 +0000 (UTC) Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-57d106e69a2so766421a12.0 for ; Tue, 25 Jun 2024 11:28:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719340102; x=1719944902; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ICbp0JfVRMLkS3xURaXu0M0XpmVLimtiYC+UR97idFU=; b=jo05gKK2M06LKhqlFX1gBlFkOuHkUiunfro5wM9VjWEyf6Mi2fwfK8UKLkGwjoXb6H tApdFn57Uvdlqqb40uMPdORhVgHmAHeD8NfXnrVXZJy7COGyCYMO3cZDXiDj6Llashpw eajJ0OTQ7Txll/7cMRTBboLWndHYynrSczmfk0zYb9d9qL95m3fpFO0ng2vbPzwlOVGm 0udAzzn+aXI+tOq0RVFdCbCzbRiYZOIh7yNBSDAWCj/SdSo8xOQtOJBu+2cC0v+fgL+Z t7UHGexth0yGjxHqPqBZWEayy3lJ2m95fBtvoYqnT4MHvqn1s+6w7bcNE7clPXy1iSS4 TmcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719340102; x=1719944902; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ICbp0JfVRMLkS3xURaXu0M0XpmVLimtiYC+UR97idFU=; b=WhxAgCNrheL82c6MVtuQV0YHwsKhHoI5UbGy7LZPgBOXSRU8/yRvtKog1Cj/365JPj W84AqNImD/QoEaBULt7miAQK5Ld6VDx4EvhqnteJcSmJK9IxwmrNCQHh+n6weJUkb91F /BbYl5rc0Zmv6JeczDEe2xM8nGh1agmzk/cvsNEFaBAxXS3bJ0HGVczc+J8aOJ54VCOF C+ZX/8cHEwxuZWi40eiW8/VWjj6kJFs89LK+FvOWaimIoktNz2oyqn1LMOlBFXcmrp3a 897ZUECsJbxPNjZZKJtNGIqI4B/6LKkiEUAyQGSNxzMj21eegO9pd6RrSF5P6UUwdTWu vQqg== X-Forwarded-Encrypted: i=1; AJvYcCVEyJxC5hOSgjCGBJ5aYznWGIemI7xb2nGoDSkTS3KhloKTPmaPP1niKggRIn1nDeb0cAcUMsBXnTb3k2XH9eSK1euNivXd8NswGy/Qy03I X-Gm-Message-State: AOJu0YwlQLKQfDw/cSHsGBljjXX1kk9amKdLPWPACskwRvTsCdKmezvV NDYYNKOyFScQQa2FPzFyOEWlMRaK4mqxjUQ/6PET0ngE2cBUrZ/G1zt14pICCUvsKBrr3FEf4hh 4qM4= X-Google-Smtp-Source: AGHT+IEup2qBc5JcOlhxwWSxCRUG0VZjYJJ5OJmMrT6P7/hUolkL818OjgSFrl9/U6AvA2SIUaakbw== X-Received: by 2002:a50:c004:0:b0:57c:b82e:884b with SMTP id 4fb4d7f45d1cf-57d70231a13mr2763887a12.19.1719340101898; Tue, 25 Jun 2024 11:28:21 -0700 (PDT) Received: from [192.168.215.29] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:21 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jun 2024 20:28:09 +0200 Subject: [PATCH v4 4/5] drm/msm/adreno: Redo the speedbin assignment MIME-Version: 1.0 Message-Id: <20240625-topic-smem_speedbin-v4-4-f6f8493ab814@linaro.org> References: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> In-Reply-To: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=7850; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Ry862n+FpOLTGn5MkJgx2cTKUCkA2znjulWGMtUKONA=; b=2LmKQAnmlokuLtndRqTr2Z3i2J0lqsGeDMaZsU18gChXDudlcRZx15ncjbOib6T6l7AtVtPZ1 TMErj+zPijiDgD+q/z7JuXbZCMBias3Xv48gCqRY7CtMehIxctR1B5S X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" There is no need to reinvent the wheel for simple read-match-set logic. Make speedbin discovery and assignment generation independent. This implicitly removes the bogus 0x80 / BIT(7) speed bin on A5xx, which has no representation in hardware whatshowever. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 34 -------------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56 --------------------------------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 51 ++++++++++++++++++++++++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 -- 4 files changed, 45 insertions(+), 99 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index c003f970189b..eed6a2eb1731 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1704,38 +1704,6 @@ static const struct adreno_gpu_funcs funcs = { .get_timestamp = a5xx_get_timestamp, }; -static void check_speed_bin(struct device *dev) -{ - struct nvmem_cell *cell; - u32 val; - - /* - * If the OPP table specifies a opp-supported-hw property then we have - * to set something with dev_pm_opp_set_supported_hw() or the table - * doesn't get populated so pick an arbitrary value that should - * ensure the default frequencies are selected but not conflict with any - * actual bins - */ - val = 0x80; - - cell = nvmem_cell_get(dev, "speed_bin"); - - if (!IS_ERR(cell)) { - void *buf = nvmem_cell_read(cell, NULL); - - if (!IS_ERR(buf)) { - u8 bin = *((u8 *) buf); - - val = (1 << bin); - kfree(buf); - } - - nvmem_cell_put(cell); - } - - devm_pm_opp_set_supported_hw(dev, &val, 1); -} - struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv = dev->dev_private; @@ -1763,8 +1731,6 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) a5xx_gpu->lm_leakage = 0x4E001A; - check_speed_bin(&pdev->dev); - nr_rings = 4; if (config->info->revn == 510) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 8ace096bb68c..f038e5f1fe59 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2112,55 +2112,6 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return progress; } -static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) -{ - if (!info->speedbins) - return UINT_MAX; - - for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) - if (info->speedbins[i].fuse == fuse) - return BIT(info->speedbins[i].speedbin); - - return UINT_MAX; -} - -static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, - struct device *dev, - const struct adreno_info *info) -{ - u32 supp_hw; - u32 speedbin; - int ret; - - ret = adreno_read_speedbin(adreno_gpu, dev, &speedbin); - /* - * -ENOENT means that the platform doesn't support speedbin which is - * fine - */ - if (ret == -ENOENT) { - return 0; - } else if (ret) { - dev_err_probe(dev, ret, - "failed to read speed-bin. Some OPPs may not be supported by hardware\n"); - return ret; - } - - supp_hw = fuse_to_supp_hw(info, speedbin); - - if (supp_hw == UINT_MAX) { - DRM_DEV_ERROR(dev, - "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", - speedbin); - supp_hw = BIT(0); /* Default */ - } - - ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); - if (ret) - return ret; - - return 0; -} - static const struct adreno_gpu_funcs funcs = { .base = { .get_param = adreno_get_param, @@ -2292,13 +2243,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); - ret = a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); - if (ret) { - a6xx_llc_slices_destroy(a6xx_gpu); - kfree(a6xx_gpu); - return ERR_PTR(ret); - } - if (is_a7xx) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); else if (adreno_has_gmu_wrapper(adreno_gpu)) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 6ffd02f38499..5b4205b76cdf 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1064,8 +1064,8 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) adreno_ocmem->hdl); } -int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, - struct device *dev, u32 *fuse) +static int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *fuse) { u32 fcode; int ret; @@ -1099,6 +1099,46 @@ int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, return 0; } +#define ADRENO_SPEEDBIN_FUSE_NODATA 0xFFFF /* Made-up large value, expected by mesa */ +static int adreno_set_speedbin(struct adreno_gpu *adreno_gpu, struct device *dev) +{ + const struct adreno_info *info = adreno_gpu->info; + u32 fuse = ADRENO_SPEEDBIN_FUSE_NODATA; + u32 supp_hw = UINT_MAX; + int ret; + + /* No speedbins defined for this GPU SKU => allow all defined OPPs */ + if (!info->speedbins) { + adreno_gpu->speedbin = ADRENO_SPEEDBIN_FUSE_NODATA; + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + + /* + * If a real error (not counting older devicetrees having no nvmem references) + * occurs when trying to get the fuse value, bail out. + */ + ret = adreno_read_speedbin(adreno_gpu, dev, &fuse); + if (ret) { + return ret; + } else if (fuse == ADRENO_SPEEDBIN_FUSE_NODATA) { + /* The info struct has speedbin data, but the DT is too old => allow all OPPs */ + DRM_DEV_INFO(dev, "No GPU speed bin fuse, please update your device tree\n"); + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + + adreno_gpu->speedbin = fuse; + + /* Traverse the known speedbins */ + for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) { + if (info->speedbins[i].fuse == fuse) { + supp_hw = BIT(info->speedbins[i].speedbin); + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + } + + return dev_err_probe(dev, -EINVAL, "Unknown speed bin fuse value: 0x%x\n", fuse); +} + int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs, int nr_rings) @@ -1108,7 +1148,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu_config adreno_gpu_config = { 0 }; struct msm_gpu *gpu = &adreno_gpu->base; const char *gpu_name; - u32 speedbin; int ret; adreno_gpu->funcs = funcs; @@ -1135,9 +1174,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) - speedbin = 0xffff; - adreno_gpu->speedbin = speedbin; + ret = adreno_set_speedbin(adreno_gpu, dev); + if (ret) + return ret; gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 563c08b44624..dc579f7afdc7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -549,9 +549,6 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); -int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, - struct device *dev, u32 *speedbin); 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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:23 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jun 2024 20:28:10 +0200 Subject: [PATCH v4 5/5] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs MIME-Version: 1.0 Message-Id: <20240625-topic-smem_speedbin-v4-5-f6f8493ab814@linaro.org> References: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> In-Reply-To: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=2474; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Il2UvibnuII6pAMEt7ZcsOO48MoDeeFboVabC36fJtY=; b=BlXBbM1o+PokhijSw+a2fl1gngXBbq3ayq9OQmI+TCgtGvPpsbaOQBkdjIvAjvDF7aXjlDpJH esr8rfv+fDKDgRA+7vpMkcyhgkuyqJI/f62VXU0kMJnbmcR074FZ4FI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the speedbin masks to ensure only the desired OPPs are available on chips of a given bin. Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 4c9820adcf52..c1e3cec1540a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2119,48 +2119,67 @@ zap-shader { memory-region = <&gpu_micro_code_mem>; }; - /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; + opp-719000000 { + opp-hz = /bits/ 64 <719000000>; + opp-level = ; + opp-supported-hw = <0x1>; + }; + opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-615000000 { opp-hz = /bits/ 64 <615000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-475000000 { opp-hz = /bits/ 64 <475000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-401000000 { opp-hz = /bits/ 64 <401000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-295000000 { opp-hz = /bits/ 64 <295000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-220000000 { opp-hz = /bits/ 64 <220000000>; opp-level = ; + opp-supported-hw = <0x3>; + }; + + opp-124800000 { + opp-hz = /bits/ 64 <124800000>; + opp-level = ; + opp-supported-hw = <0x3>; }; }; };