From patchwork Tue Jun 25 20:03:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Barker X-Patchwork-Id: 13711994 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 71DC717D36B; Tue, 25 Jun 2024 20:03:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719345819; cv=none; b=X8nPiiDPPpqP+/xK13s+N7V9KTnstH7Gq+aviJ8Q9ekFmDtRI6jtL7mVVB7PMwTkYNslxDJzky36VylyGLvRVzlvLLSDaJDX80AnW9k3A6jyPrk6ieQIKcaPcF2NQMiYsB3EF7RSkJiGipBzbLsbPNuTIx3r7kfInleu2fO8BEs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719345819; c=relaxed/simple; bh=aWT94ex/zXwt0FgX4IXzVUR1qQ5Kf0OhrKcsoCtg+kA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=s08fWSWGfeUluI2K8CSySpYarEFPZoOLGg4Fl+bRWeVVYW8Uae6DYbdn7AszSszIJnOoaTrLPx9H1cv0KsEpx7arkLLxa2jwKOi4DaLZGZ46JvY9iy8HyHThhFk4ONKtHiGdyscSaHSN08edH5ZL336WTrrU8iA4KbmqcDH3Q+M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.08,264,1712588400"; d="scan'208";a="209263959" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 26 Jun 2024 05:03:36 +0900 Received: from renesas-deb12.mshome.net (unknown [10.226.92.125]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 09789400C4E6; Wed, 26 Jun 2024 05:03:31 +0900 (JST) From: Paul Barker To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Lad Prabhakar Cc: Paul Barker , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/9] pinctrl: renesas: rzg2l: Clarify OEN read/write support Date: Tue, 25 Jun 2024 21:03:08 +0100 Message-Id: <20240625200316.4282-2-paul.barker.ct@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> References: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 We currently support OEN read/write for the RZ/G3S SoC but not the RZ/G2L SoC family (consisting of RZ/G2L, RZ/G2LC, RZ/G2UL, RZ/V2L & RZ/Five). The appropriate functions are renamed to clarify this and to match the callback names. We should also only set the oen_read and oen_write function pointers for the devices which support these operations. This requires us to check that these function pointers are valid before calling them. Signed-off-by: Paul Barker Reviewed-by: Geert Uytterhoeven Acked-by: Linus Walleij --- Changes v2->v3: * Picked up Linus W's Acked-by tag & Geert's Reviewed-by tag. * Renamed rzg3s oen functions to match the callback names. Changes v1->v2: * New patch to clarify function names. drivers/pinctrl/renesas/pinctrl-rzg2l.c | 28 ++++++++++++------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 32945d4c8dc0..a2a395fd34c1 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -994,7 +994,7 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, return false; } -static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin) +static bool rzg3s_oen_is_supported(u32 caps, u8 pin, u8 max_pin) { if (!(caps & PIN_CFG_OEN)) return false; @@ -1005,7 +1005,7 @@ static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin) return true; } -static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port) +static u8 rzg3s_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port) { if (pin) pin *= 2; @@ -1016,31 +1016,31 @@ static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port) return pin; } -static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin) +static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin) { u8 max_port = pctrl->data->hwcfg->oen_max_port; u8 max_pin = pctrl->data->hwcfg->oen_max_pin; u8 bit; - if (!rzg2l_oen_is_supported(caps, pin, max_pin)) + if (!rzg3s_oen_is_supported(caps, pin, max_pin)) return 0; - bit = rzg2l_pin_to_oen_bit(offset, pin, max_port); + bit = rzg3s_pin_to_oen_bit(offset, pin, max_port); return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); } -static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen) +static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen) { u8 max_port = pctrl->data->hwcfg->oen_max_port; u8 max_pin = pctrl->data->hwcfg->oen_max_pin; unsigned long flags; u8 val, bit; - if (!rzg2l_oen_is_supported(caps, pin, max_pin)) + if (!rzg3s_oen_is_supported(caps, pin, max_pin)) return -EINVAL; - bit = rzg2l_pin_to_oen_bit(offset, pin, max_port); + bit = rzg3s_pin_to_oen_bit(offset, pin, max_port); spin_lock_irqsave(&pctrl->lock, flags); val = readb(pctrl->base + ETH_MODE); @@ -1215,6 +1215,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_OUTPUT_ENABLE: + if (!pctrl->data->oen_read) + return -EOPNOTSUPP; arg = pctrl->data->oen_read(pctrl, cfg, _pin, bit); if (!arg) return -EINVAL; @@ -1354,6 +1356,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, case PIN_CONFIG_OUTPUT_ENABLE: arg = pinconf_to_config_argument(_configs[i]); + if (!pctrl->data->oen_write) + return -EOPNOTSUPP; ret = pctrl->data->oen_write(pctrl, cfg, _pin, bit, !!arg); if (ret) return ret; @@ -3065,8 +3069,6 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { #endif .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb = &rzg2l_pmc_writeb, - .oen_read = &rzg2l_read_oen, - .oen_write = &rzg2l_write_oen, .hw_to_bias_param = &rzg2l_hw_to_bias_param, .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; @@ -3082,8 +3084,6 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .hwcfg = &rzg2l_hwcfg, .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb = &rzg2l_pmc_writeb, - .oen_read = &rzg2l_read_oen, - .oen_write = &rzg2l_write_oen, .hw_to_bias_param = &rzg2l_hw_to_bias_param, .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; @@ -3098,8 +3098,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { .hwcfg = &rzg3s_hwcfg, .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb = &rzg2l_pmc_writeb, - .oen_read = &rzg2l_read_oen, - .oen_write = &rzg2l_write_oen, + .oen_read = &rzg3s_oen_read, + .oen_write = &rzg3s_oen_write, .hw_to_bias_param = &rzg2l_hw_to_bias_param, .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; From patchwork Tue Jun 25 20:03:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Barker X-Patchwork-Id: 13711995 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2E73117DE0C; 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dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.08,264,1712588400"; d="scan'208";a="209263964" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 26 Jun 2024 05:03:40 +0900 Received: from renesas-deb12.mshome.net (unknown [10.226.92.125]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id C86C6400C4E6; Wed, 26 Jun 2024 05:03:36 +0900 (JST) From: Paul Barker To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Lad Prabhakar Cc: Paul Barker , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/9] pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions Date: Tue, 25 Jun 2024 21:03:09 +0100 Message-Id: <20240625200316.4282-3-paul.barker.ct@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> References: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The variable naming in the various OEN functions has been confusing. We were passing the _pin & bit variables from rzg2l_pinctrl_pinconf_get() and rzg2l_pinctrl_pinconf_set() as the offset & pin argument to the oen_read() and oen_write() functions. This doesn't make sense, the first of these isn't actually an offset and the second is not needed for RZ/V2H but leads to confusion with the bit variable used within these functions. To tidy this up, instead pass the _pin variable directly to the oen_read() and oen_write() functions with consistent naming. Then rzg3s_read_oen() and rzg3s_write_oen() can use macros to get the port and pin numbers it needs. Instead of passing the pin capabilities into oen_read() and oen_write(), we can check that the pin supports OEN before calling these functions. Also, merge rzg3s_oen_is_supported() into rzg3s_pin_to_oen_bit() to give a single translation function which returns an error if the pin doesn't support OEN. While we're here, remove an unnecessary branch and clarify the variable naming. Lastly, check that we are not dealing with a dedicated pin before calling RZG2L_PIN_ID_TO_{PORT,PIN}(). Signed-off-by: Paul Barker Acked-by: Linus Walleij --- Changes v2->v3: * Picked up Linus W's Acked-by tag. * Skipped Geert's Reviewed-by tag as I've made a few changes here and want another review. * Check pin caps before calling oen_{read,write}() so we can drop the caps argument to those functions. * Simplify arguments to rzg3s_pin_to_oen_bit() and decode pin_data/port/pin inside this function. * Check for dedicated pin before calling RZG2L_PIN_ID_TO_{PORT,PIN}(). Changes v1->v2: * Merged patches 1 & 2 from the previous series, updated to be compatible with recent patches adding RZ/V2H support. drivers/pinctrl/renesas/pinctrl-rzg2l.c | 95 +++++++++++-------------- 1 file changed, 42 insertions(+), 53 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index a2a395fd34c1..737d8d0064c4 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -289,8 +289,8 @@ struct rzg2l_pinctrl_data { #endif void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock); void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset); - u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin); - int (*oen_write)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen); + u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); + int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen); int (*hw_to_bias_param)(unsigned int val); int (*bias_param_to_hw)(enum pin_config_param param); }; @@ -994,53 +994,48 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, return false; } -static bool rzg3s_oen_is_supported(u32 caps, u8 pin, u8 max_pin) -{ - if (!(caps & PIN_CFG_OEN)) - return false; - - if (pin > max_pin) - return false; - - return true; -} - -static u8 rzg3s_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port) -{ - if (pin) - pin *= 2; - - if (offset / RZG2L_PINS_PER_PORT == max_port) - pin += 1; - - return pin; -} - -static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin) +static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { + u64 *pin_data = pctrl->desc.pins[_pin].drv_data; u8 max_port = pctrl->data->hwcfg->oen_max_port; u8 max_pin = pctrl->data->hwcfg->oen_max_pin; - u8 bit; + u8 port, pin, bit; - if (!rzg3s_oen_is_supported(caps, pin, max_pin)) - return 0; + if (*pin_data & RZG2L_SINGLE_PIN) + return -EINVAL; - bit = rzg3s_pin_to_oen_bit(offset, pin, max_port); + port = RZG2L_PIN_ID_TO_PORT(_pin); + pin = RZG2L_PIN_ID_TO_PIN(_pin); + if (pin > max_pin) + return -EINVAL; + + bit = pin * 2; + if (port == max_port) + bit += 1; + + return bit; +} + +static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) +{ + int bit; + + bit = rzg3s_pin_to_oen_bit(pctrl, _pin); + if (bit < 0) + return bit; return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); } -static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen) +static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) { - u8 max_port = pctrl->data->hwcfg->oen_max_port; - u8 max_pin = pctrl->data->hwcfg->oen_max_pin; unsigned long flags; - u8 val, bit; + int bit; + u8 val; - if (!rzg3s_oen_is_supported(caps, pin, max_pin)) - return -EINVAL; - - bit = rzg3s_pin_to_oen_bit(offset, pin, max_port); + bit = rzg3s_pin_to_oen_bit(pctrl, _pin); + if (bit < 0) + return bit; spin_lock_irqsave(&pctrl->lock, flags); val = readb(pctrl->base + ETH_MODE); @@ -1119,12 +1114,12 @@ static int rzv2h_bias_param_to_hw(enum pin_config_param param) return -EINVAL; } -static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset) +static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK", "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKN", "XSPI0_CKP" }; - const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin]; unsigned int i; for (i = 0; i < ARRAY_SIZE(pin_names); i++) { @@ -1136,19 +1131,16 @@ static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset) return 0; } -static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin) +static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { u8 bit; - if (!(caps & PIN_CFG_OEN)) - return 0; - - bit = rzv2h_pin_to_oen_bit(pctrl, offset); + bit = rzv2h_pin_to_oen_bit(pctrl, _pin); return !(readb(pctrl->base + PFC_OEN) & BIT(bit)); } -static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen) +static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) { const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs = &hwcfg->regs; @@ -1156,10 +1148,7 @@ static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 u8 val, bit; u8 pwpr; - if (!(caps & PIN_CFG_OEN)) - return -EINVAL; - - bit = rzv2h_pin_to_oen_bit(pctrl, offset); + bit = rzv2h_pin_to_oen_bit(pctrl, _pin); spin_lock_irqsave(&pctrl->lock, flags); val = readb(pctrl->base + PFC_OEN); if (oen) @@ -1215,9 +1204,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_OUTPUT_ENABLE: - if (!pctrl->data->oen_read) + if (!pctrl->data->oen_read || !(cfg & PIN_CFG_OEN)) return -EOPNOTSUPP; - arg = pctrl->data->oen_read(pctrl, cfg, _pin, bit); + arg = pctrl->data->oen_read(pctrl, _pin); if (!arg) return -EINVAL; break; @@ -1356,9 +1345,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, case PIN_CONFIG_OUTPUT_ENABLE: arg = pinconf_to_config_argument(_configs[i]); - if (!pctrl->data->oen_write) + if (!pctrl->data->oen_write || !(cfg & PIN_CFG_OEN)) return -EOPNOTSUPP; - ret = pctrl->data->oen_write(pctrl, cfg, _pin, bit, !!arg); + ret = pctrl->data->oen_write(pctrl, _pin, !!arg); if (ret) return ret; break; From patchwork Tue Jun 25 20:03:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Barker X-Patchwork-Id: 13711996 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3C71117D37B; Tue, 25 Jun 2024 20:03:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="213220620" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 26 Jun 2024 05:03:45 +0900 Received: from renesas-deb12.mshome.net (unknown [10.226.92.125]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 8516740078B4; Wed, 26 Jun 2024 05:03:41 +0900 (JST) From: Paul Barker To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Lad Prabhakar Cc: Paul Barker , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/9] pinctrl: renesas: rzg2l: Support output enable on RZ/G2L Date: Tue, 25 Jun 2024 21:03:10 +0100 Message-Id: <20240625200316.4282-4-paul.barker.ct@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> References: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK signal is selectable to support an Ethernet PHY operating in either MII or RGMII mode. By default, the signal is configured as an input and MII mode is supported. The ETH_MODE register can be modified to configure this signal as an output to support RGMII mode. As this signal is by default an input, and can optionally be switched to an output, it maps neatly onto an `output-enable` property in the device tree. Signed-off-by: Paul Barker Reviewed-by: Geert Uytterhoeven Acked-by: Linus Walleij --- Changes v2->v3: * Picked up Linus W's Acked-by tag & Geert's Reviewed-by tag. * Simplify arguments to rzg2l_pin_to_oen_bit() and decode pin/caps inside this function. No check is needed for dedicated pins as no dedicated pins support OEN in the RZ/G2L family. Changes v1->v2: * Use oen_read and oen_write function pointers to be compatible with recent patches adding RZ/V2H support. drivers/pinctrl/renesas/pinctrl-rzg2l.c | 68 +++++++++++++++++++++++-- 1 file changed, 64 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 737d8d0064c4..b7d1cfb023b2 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -994,6 +994,61 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, return false; } +static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) +{ + u64 *pin_data = pctrl->desc.pins[_pin].drv_data; + u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data); + u8 max_pin = pctrl->data->hwcfg->oen_max_pin; + u8 pin = RZG2L_PIN_ID_TO_PIN(_pin); + + if (pin > max_pin) + return -EINVAL; + + /* + * We can determine which Ethernet interface we're dealing with from + * the caps. + */ + if (caps & PIN_CFG_IO_VMC_ETH0) + return 0; + if (caps & PIN_CFG_IO_VMC_ETH1) + return 1; + + return -EINVAL; +} + +static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) +{ + int bit; + + bit = rzg2l_pin_to_oen_bit(pctrl, _pin); + if (bit < 0) + return 0; + + return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); +} + +static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) +{ + unsigned long flags; + int bit; + u8 val; + + bit = rzg2l_pin_to_oen_bit(pctrl, _pin); + if (bit < 0) + return bit; + + spin_lock_irqsave(&pctrl->lock, flags); + val = readb(pctrl->base + ETH_MODE); + if (oen) + val &= ~BIT(bit); + else + val |= BIT(bit); + writeb(val, pctrl->base + ETH_MODE); + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { u64 *pin_data = pctrl->desc.pins[_pin].drv_data; @@ -1772,7 +1827,7 @@ static const u64 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), @@ -1781,7 +1836,7 @@ static const u64 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), @@ -1805,13 +1860,13 @@ static const u64 r9a07g044_gpio_configs[] = { static const u64 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), @@ -3004,6 +3059,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000, }, .iolh_groupb_oi = { 100, 66, 50, 33, }, + .oen_max_pin = 0, }; static const struct rzg2l_hwcfg rzg3s_hwcfg = { @@ -3058,6 +3114,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { #endif .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb = &rzg2l_pmc_writeb, + .oen_read = &rzg2l_read_oen, + .oen_write = &rzg2l_write_oen, .hw_to_bias_param = &rzg2l_hw_to_bias_param, .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; @@ -3073,6 +3131,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .hwcfg = &rzg2l_hwcfg, .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb = &rzg2l_pmc_writeb, + .oen_read = &rzg2l_read_oen, + .oen_write = &rzg2l_write_oen, .hw_to_bias_param = &rzg2l_hw_to_bias_param, .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; From patchwork Tue Jun 25 20:03:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Barker X-Patchwork-Id: 13711997 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9983117E46C; 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dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.08,264,1712588400"; d="scan'208";a="213220628" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 26 Jun 2024 05:03:50 +0900 Received: from renesas-deb12.mshome.net (unknown [10.226.92.125]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 42BB8400C4E6; Wed, 26 Jun 2024 05:03:45 +0900 (JST) From: Paul Barker To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Lad Prabhakar Cc: Paul Barker , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/9] arm64: dts: renesas: rzg2l: Enable Ethernet TXC output Date: Tue, 25 Jun 2024 21:03:11 +0100 Message-Id: <20240625200316.4282-5-paul.barker.ct@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> References: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Configure ET0_TXC and ET1_TXC as outputs on the Renesas RZ/[GV]2L SMARC SoMs, as per RGMII specification. Signed-off-by: Paul Barker Reviewed-by: Geert Uytterhoeven Acked-by: Linus Walleij --- Changes v2->v3: * Picked up Linus W's Acked-by tag. Changes v1->v2: * Picked up Geert's Reviewed-by tag. .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 76 +++++++++++-------- 1 file changed, 44 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 4409c47239b9..2b5e037ea9fa 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -180,41 +180,53 @@ adc_pins: adc { }; eth0_pins: eth0 { - pinmux = , /* ET0_LINKSTA */ - , /* ET0_MDC */ - , /* ET0_MDIO */ - , /* ET0_TXC */ - , /* ET0_TX_CTL */ - , /* ET0_TXD0 */ - , /* ET0_TXD1 */ - , /* ET0_TXD2 */ - , /* ET0_TXD3 */ - , /* ET0_RXC */ - , /* ET0_RX_CTL */ - , /* ET0_RXD0 */ - , /* ET0_RXD1 */ - , /* ET0_RXD2 */ - , /* ET0_RXD3 */ - ; /* IRQ2 */ + txc { + pinmux = ; /* ET0_TXC */ + output-enable; + }; + + mux { + pinmux = , /* ET0_LINKSTA */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + , /* ET0_RXD3 */ + ; /* IRQ2 */ + }; }; eth1_pins: eth1 { - pinmux = , /* ET1_LINKSTA */ - , /* ET1_MDC */ - , /* ET1_MDIO */ - , /* ET1_TXC */ - , /* ET1_TX_CTL */ - , /* ET1_TXD0 */ - , /* ET1_TXD1 */ - , /* ET1_TXD2 */ - , /* ET1_TXD3 */ - , /* ET1_RXC */ - , /* ET1_RX_CTL */ - , /* ET1_RXD0 */ - , /* ET1_RXD1 */ - , /* ET1_RXD2 */ - , /* ET1_RXD3 */ - ; /* IRQ3 */ + txc { + pinmux = ; /* ET1_TXC */ + output-enable; + }; + + mux { + pinmux = , /* ET1_LINKSTA */ + , /* ET1_MDC */ + , /* ET1_MDIO */ + , /* ET1_TX_CTL */ + , /* ET1_TXD0 */ + , /* ET1_TXD1 */ + , /* ET1_TXD2 */ + , /* ET1_TXD3 */ + , /* ET1_RXC */ + , /* ET1_RX_CTL */ + , /* ET1_RXD0 */ + , /* ET1_RXD1 */ + , /* ET1_RXD2 */ + , /* ET1_RXD3 */ + ; /* IRQ3 */ + }; }; gpio-sd0-pwr-en-hog { From patchwork Tue Jun 25 20:03:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Barker X-Patchwork-Id: 13711998 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4C7BD17DE17; Tue, 25 Jun 2024 20:03:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719345838; cv=none; b=GaBCVYLYIqHE9Io2y8gqa5BsNOg7V66c3qMPussNACbQFG66Bny3WgnffLpOjVm3RzJsoqXwvdX+zwlEb1A++nt2eWkplvOgq3L2s5X+DUlY5bZF+G/AzOdv9SKibm1t3oOmOKsQ2B1IyTSpLVsp0H96ewndsD8RA5kfjmJ4C3M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719345838; c=relaxed/simple; bh=IHTD3Ly7Xevyu3XTOQjbSNBcLFMiOjRt71XjlcWTHiA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SGK+P60hEpv4BbqN4tS47YOASqccu4TeDYSJODC+5N3FZsykTuszByLrGPc43T4GIpmXgu7WfvqQpcdLDA11l/jGcpOcLW0wdpI4YNQsNkdDOl1k8KcN/JA7JJgfCJGiZQxOV9kZgXT0305VUG4DG16m1IhIlRK0ANjr0B4iLvE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.08,264,1712588400"; d="scan'208";a="209263979" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 26 Jun 2024 05:03:55 +0900 Received: from renesas-deb12.mshome.net (unknown [10.226.92.125]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 054D840078B4; Wed, 26 Jun 2024 05:03:50 +0900 (JST) From: Paul Barker To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Lad Prabhakar Cc: Paul Barker , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/9] arm64: dts: renesas: rzg2lc: Enable Ethernet TXC output Date: Tue, 25 Jun 2024 21:03:12 +0100 Message-Id: <20240625200316.4282-6-paul.barker.ct@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> References: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Configure ET0_TXC and ET1_TXC as outputs on the Renesas RZ/G2LC SMARC SoM, as per RGMII specification. Signed-off-by: Paul Barker Reviewed-by: Geert Uytterhoeven Acked-by: Linus Walleij --- Changes v2->v3: * Picked up Linus W's Acked-by tag. Changes v1->v2: * Picked up Geert's Reviewed-by tag. .../boot/dts/renesas/rzg2lc-smarc-som.dtsi | 38 +++++++++++-------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 5e4209d6fb42..664311fd2098 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -128,22 +128,28 @@ &ostm2 { &pinctrl { eth0_pins: eth0 { - pinmux = , /* ET0_LINKSTA */ - , /* ET0_MDC */ - , /* ET0_MDIO */ - , /* ET0_TXC */ - , /* ET0_TX_CTL */ - , /* ET0_TXD0 */ - , /* ET0_TXD1 */ - , /* ET0_TXD2 */ - , /* ET0_TXD3 */ - , /* ET0_RXC */ - , /* ET0_RX_CTL */ - , /* ET0_RXD0 */ - , /* ET0_RXD1 */ - , /* ET0_RXD2 */ - , /* ET0_RXD3 */ - ; /* IRQ0 */ + txc { + pinmux = ; /* ET0_TXC */ + output-enable; + }; + + mux { + pinmux = , /* ET0_LINKSTA */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + , /* ET0_RXD3 */ + ; /* IRQ0 */ + }; }; gpio-sd0-pwr-en-hog { From patchwork Tue Jun 25 20:03:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Barker X-Patchwork-Id: 13711999 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 550BA17DE17; Tue, 25 Jun 2024 20:04:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719345842; cv=none; b=IPlrno48L5nAVu0kiJv0kK6fEpM57+e5TrvRlZzrld+UWQut6uZjiTz2/z00Vc8Ivrn7TBxK2qtTrFCTDRKxDNQqzFZyOXP9hetQLlW4BpGQX0oEMoo59q67LWivb37WPL1QNt0TTC/bAGheNQo9BWu70ExH5MqaR5wTZVT19vM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719345842; c=relaxed/simple; bh=hyPn9Hpc1mnmwTnKVBl4grzNni7qFyDaEHMo5fOLvDo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=u9Bf+4CS7pIdhykCD4q0PS8g9W2GOdthcHKCk0sOd8y0/BPKjQ/9TOqM3+YCZWHAZYrj9M2UhlWUwAZFt/dBGtFu4J+waHNW6IJI9GJrmCprzCeuHe+rQgei9a6qtm8xOFBdUiPQNh1ywhoSkDbA8XFLkRJAAzF58C9VOtHgIMo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.08,264,1712588400"; d="scan'208";a="209263984" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 26 Jun 2024 05:04:00 +0900 Received: from renesas-deb12.mshome.net (unknown [10.226.92.125]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id B58DD400C4E6; Wed, 26 Jun 2024 05:03:55 +0900 (JST) From: Paul Barker To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Lad Prabhakar Cc: Paul Barker , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/9] arm64: dts: renesas: rzg2ul: Enable Ethernet TXC output Date: Tue, 25 Jun 2024 21:03:13 +0100 Message-Id: <20240625200316.4282-7-paul.barker.ct@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> References: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Configure ET0_TXC and ET1_TXC as outputs on the Renesas RZ/G2UL and RZ/Five SMARC SoMs, as per RGMII specification. Signed-off-by: Paul Barker Reviewed-by: Geert Uytterhoeven Acked-by: Linus Walleij --- Changes v2->v3: * Picked up Linus W's Acked-by tag. Changes v1->v2: * Clarified that this patch also affects RZ/Five. * Picked up Geert's Reviewed-by tag. .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 76 +++++++++++-------- 1 file changed, 44 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 97cdad2a12e2..417f49090b15 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -142,41 +142,53 @@ adc_pins: adc { }; eth0_pins: eth0 { - pinmux = , /* ET0_LINKSTA */ - , /* ET0_MDC */ - , /* ET0_MDIO */ - , /* ET0_TXC */ - , /* ET0_TX_CTL */ - , /* ET0_TXD0 */ - , /* ET0_TXD1 */ - , /* ET0_TXD2 */ - , /* ET0_TXD3 */ - , /* ET0_RXC */ - , /* ET0_RX_CTL */ - , /* ET0_RXD0 */ - , /* ET0_RXD1 */ - , /* ET0_RXD2 */ - , /* ET0_RXD3 */ - ; /* IRQ2 */ + txc { + pinmux = ; /* ET0_TXC */ + output-enable; + }; + + mux { + pinmux = , /* ET0_LINKSTA */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + , /* ET0_RXD3 */ + ; /* IRQ2 */ + }; }; eth1_pins: eth1 { - pinmux = , /* ET1_LINKSTA */ - , /* ET1_MDC */ - , /* ET1_MDIO */ - , /* ET1_TXC */ - , /* ET1_TX_CTL */ - , /* ET1_TXD0 */ - , /* ET1_TXD1 */ - , /* ET1_TXD2 */ - , /* ET1_TXD3 */ - , /* ET1_RXC */ - , /* ET1_RX_CTL */ - , /* ET1_RXD0 */ - , /* ET1_RXD1 */ - , /* ET1_RXD2 */ - , /* ET1_RXD3 */ - ; /* IRQ7 */ + txc { + pinmux = ; /* ET1_TXC */ + output-enable; + }; + + mux { + pinmux = , /* ET1_LINKSTA */ + , /* ET1_MDC */ + , /* ET1_MDIO */ + , /* ET1_TX_CTL */ + , /* ET1_TXD0 */ + , /* ET1_TXD1 */ + , /* ET1_TXD2 */ + , /* ET1_TXD3 */ + , /* ET1_RXC */ + , /* ET1_RX_CTL */ + , /* ET1_RXD0 */ + , /* ET1_RXD1 */ + , /* ET1_RXD2 */ + , /* ET1_RXD3 */ + ; /* IRQ7 */ + }; }; sdhi0_emmc_pins: sd0emmc { From patchwork Tue Jun 25 20:03:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Barker X-Patchwork-Id: 13712000 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1082517D36B; Tue, 25 Jun 2024 20:04:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719345848; cv=none; b=GJZuDUQ390utBv5HCY+CXRh58ptINF/P+NIyj8COQqzA6yPICE+xPVT7pR67vha1IRcUDUyrJae18MdTDq3NQisIEx/tFtaErUrQL/umaJ2EdSVop6v5joVymJJvxo07WXefl6mIXBp+x+aAy0enjUutoN+V2ylaSmyqmMNgvKg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719345848; c=relaxed/simple; bh=7H59c5LVJ7O00WD7YuQ1ZZjkdh3fTNiqX7vFrKedAlM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HBnykpBdujALWolvZsbPF1FRJJemXDP1/FvLqhRZYr//sDRzML0XagPk3YhP+hbbCethRRNYMGVuNafCR5Equdc5clNLrK4wG/dc44HzUDMWJyLvlzKdG5Gma5GUdXTHNm9ucI0nM4vZvK/si9zArceDbFIhblUGJzCpec3l2co= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.08,264,1712588400"; d="scan'208";a="213220643" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 26 Jun 2024 05:04:04 +0900 Received: from renesas-deb12.mshome.net (unknown [10.226.92.125]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id AD5AC40078B4; Wed, 26 Jun 2024 05:04:00 +0900 (JST) From: Paul Barker To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Lad Prabhakar Cc: Paul Barker , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 7/9] arm64: dts: renesas: rzg2l: Set Ethernet PVDD to 1.8V Date: Tue, 25 Jun 2024 21:03:14 +0100 Message-Id: <20240625200316.4282-8-paul.barker.ct@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> References: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On the RZ/G2L & RZ/V2L SMARC SOMs, the RGMII interface between the SoC and the Ethernet PHY operates at 1.8V. The power supply for this interface may be correctly configured in u-boot, but the kernel should not be relying on this. Now that the RZ/G2L pinctrl driver supports configuring the Ethernet power supply voltage, we can simply specify the desired voltage in the device tree. Signed-off-by: Paul Barker Reviewed-by: Geert Uytterhoeven Acked-by: Linus Walleij --- Changes v2->v3: * Picked up Linus W's Acked-by tag. Changes v1->v2: * Picked up Geert's Reviewed-by tag. .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 2b5e037ea9fa..83f5642d0d35 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -182,6 +182,7 @@ adc_pins: adc { eth0_pins: eth0 { txc { pinmux = ; /* ET0_TXC */ + power-source = <1800>; output-enable; }; @@ -199,14 +200,19 @@ mux { , /* ET0_RXD0 */ , /* ET0_RXD1 */ , /* ET0_RXD2 */ - , /* ET0_RXD3 */ - ; /* IRQ2 */ + ; /* ET0_RXD3 */ + power-source = <1800>; + }; + + irq { + pinmux = ; /* IRQ2 */ }; }; eth1_pins: eth1 { txc { pinmux = ; /* ET1_TXC */ + power-source = <1800>; output-enable; }; @@ -224,8 +230,12 @@ mux { , /* ET1_RXD0 */ , /* ET1_RXD1 */ , /* ET1_RXD2 */ - , /* ET1_RXD3 */ - ; /* IRQ3 */ + ; /* ET1_RXD3 */ + power-source = <1800>; + }; + + irq { + pinmux = ; /* IRQ3 */ }; }; From patchwork Tue Jun 25 20:03:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Barker X-Patchwork-Id: 13712001 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D974C17E445; Tue, 25 Jun 2024 20:04:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719345852; cv=none; b=sTDrFC4unUcU/k4/0M1bEWYqO735gDT1sDqeEFoVu50XCaG04ySIgIDbLFTifECScywgBh+dGR7yZ9fZ6Tb+mOEtSrewM6zn/rGu4RdCnzlPMgx3vubz2UP72LjGDjg1k2K6aSG/g1qZ8HU91h/stY9ia1gB784FhSXDsFohZq4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719345852; c=relaxed/simple; bh=+fkc24+0B8xzt1iEyPKkVNZoIEHtBh0VYdQq0tm9i2w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=n3OZKyX4kGQn0UEoaNsED3C4UtIPgNLwaxJrP5xN31g70kxB2PKyw24TNA0f3iYEhjqCDBoqlqxfBfX0H5tND+nx+Apl8taOJyd+Kd2Ljsu+JMMnRguioqx6oNz9YVZqurqKljz0qStlTwlL9PVW5IVA28Re87o8ro1bD2EEv2U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.08,264,1712588400"; d="scan'208";a="209263996" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 26 Jun 2024 05:04:09 +0900 Received: from renesas-deb12.mshome.net (unknown [10.226.92.125]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 6C29540078B4; Wed, 26 Jun 2024 05:04:05 +0900 (JST) From: Paul Barker To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Lad Prabhakar Cc: Paul Barker , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 8/9] arm64: dts: renesas: rzg2lc: Set Ethernet PVDD to 1.8V Date: Tue, 25 Jun 2024 21:03:15 +0100 Message-Id: <20240625200316.4282-9-paul.barker.ct@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> References: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On the RZ/G2LC SMARC SOM, the RGMII interface between the SoC and the Ethernet PHY operates at 1.8V. The power supply for this interface may be correctly configured in u-boot, but the kernel should not be relying on this. Now that the RZ/G2L pinctrl driver supports configuring the Ethernet power supply voltage, we can simply specify the desired voltage in the device tree. Signed-off-by: Paul Barker Reviewed-by: Geert Uytterhoeven Acked-by: Linus Walleij --- Changes v2->v3: * Picked up Linus W's Acked-by tag. Changes v1->v2: * Picked up Geert's Reviewed-by tag. arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 664311fd2098..b4ef5ea8a9e3 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -130,6 +130,7 @@ &pinctrl { eth0_pins: eth0 { txc { pinmux = ; /* ET0_TXC */ + power-source = <1800>; output-enable; }; @@ -147,8 +148,12 @@ mux { , /* ET0_RXD0 */ , /* ET0_RXD1 */ , /* ET0_RXD2 */ - , /* ET0_RXD3 */ - ; /* IRQ0 */ + ; /* ET0_RXD3 */ + power-source = <1800>; + }; + + irq { + pinmux = ; /* IRQ0 */ }; }; From patchwork Tue Jun 25 20:03:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Barker X-Patchwork-Id: 13712002 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2B41217E451; Tue, 25 Jun 2024 20:04:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719345857; cv=none; b=JuCHS/cKSJHpEnuxhtMq7rdRsfwzoyqGH7LlvJn0HtBZlDSd8ktP1zmTwk8I4WY94XwNFkVFazncPqOvMeVMuVA1+1/kLXXmEvRoKPzvgTGCN6XWhGVZi0g5Pt7D9ufghbq79cMB0bT3nhAfW/ZZXCfbodNHCNEnSLG/VMN6CgI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719345857; c=relaxed/simple; bh=+Eb/FCHx6HNPOulvBM4lYjiuUFxkpho+JK7wwDQc/ZU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MsFMtSN81p1HY1mQH2JoHkE4I6oJahmKPkay0xUBqGjnG6nuGUjAdlPYP5Wnx+YG7z57oMFKbbgSkzyI7LK968y7Z7lzh9UzbVksP4dQWNSTIgguOUxPxVvlqOjZu0vyD4nQgPP5br5PhL7dnfEBvWfnafwZrKhfynvIwCKcr3Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.08,264,1712588400"; d="scan'208";a="213220656" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 26 Jun 2024 05:04:14 +0900 Received: from renesas-deb12.mshome.net (unknown [10.226.92.125]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 27A8C400C4E6; Wed, 26 Jun 2024 05:04:09 +0900 (JST) From: Paul Barker To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Lad Prabhakar Cc: Paul Barker , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 9/9] arm64: dts: renesas: rzg2ul: Set Ethernet PVDD to 1.8V Date: Tue, 25 Jun 2024 21:03:16 +0100 Message-Id: <20240625200316.4282-10-paul.barker.ct@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> References: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On the RZ/G2UL & RZ/Five SMARC SOMs, the RGMII interface between the SoC and the Ethernet PHY operates at 1.8V. The power supply for this interface may be correctly configured in u-boot, but the kernel should not be relying on this. Now that the RZ/G2L pinctrl driver supports configuring the Ethernet power supply voltage, we can simply specify the desired voltage in the device tree. Signed-off-by: Paul Barker Reviewed-by: Geert Uytterhoeven Acked-by: Linus Walleij --- Changes v2->v3: * Picked up Linus W's Acked-by tag. Changes v1->v2: * Picked up Geert's Reviewed-by tag. .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 417f49090b15..79443fb3f581 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -144,6 +144,7 @@ adc_pins: adc { eth0_pins: eth0 { txc { pinmux = ; /* ET0_TXC */ + power-source = <1800>; output-enable; }; @@ -161,14 +162,19 @@ mux { , /* ET0_RXD0 */ , /* ET0_RXD1 */ , /* ET0_RXD2 */ - , /* ET0_RXD3 */ - ; /* IRQ2 */ + ; /* ET0_RXD3 */ + power-source = <1800>; + }; + + irq { + pinmux = ; /* IRQ2 */ }; }; eth1_pins: eth1 { txc { pinmux = ; /* ET1_TXC */ + power-source = <1800>; output-enable; }; @@ -186,8 +192,12 @@ mux { , /* ET1_RXD0 */ , /* ET1_RXD1 */ , /* ET1_RXD2 */ - , /* ET1_RXD3 */ - ; /* IRQ7 */ + ; /* ET1_RXD3 */ + power-source = <1800>; + }; + + irq { + pinmux = ; /* IRQ7 */ }; };