From patchwork Wed Jun 26 10:39:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13712621 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65DFA17A922; Wed, 26 Jun 2024 10:40:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719398454; cv=none; b=Z/4pXF3nvuntilzYX8O5IFcWjPgP0veUslJV+oiroHMT3LCms0X2zCPM7v4TCUw4iZBdzPB/dycRBeFtvPFsFgSSDfMEOGDxw3jQuW+ZjRtBtxe7hF5xLEli+h/QEqHvFxeUPzgstVWN5XLa+h6foOHDokSF5fBXv4XNu4u0yz4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719398454; c=relaxed/simple; bh=hyLAnLHHaqi+vBvo7zCHnj7HR41sEtAWCc2PJsn5SsU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g854IoS+kJLWegE8I2u1JiK8g/jOvmKYZ7IWOgFYCvckyx94U2u7aWxkZ6AXy7GJ83Z+I4igbw26S4j4BRcpueHcAeI67gO/ANtkmdVrXbG9+/y0dxDqYO1T8gDOrMvjvyoWVQUW7a9dCPyS92kNaxiMLly7rWc44E3cGP9EbBo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=PeYLUL+V; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="PeYLUL+V" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45Q7mbx3031370; Wed, 26 Jun 2024 10:40:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= mVIV1bNkbYIen8b7ZWVpzP0mrFRirI+uiVayxAO3oCk=; b=PeYLUL+VVfHEpoA2 zqyBYvq/zjUnn0A8j4c6cYM07NTEzF+m962kY8QM8IjH+FlA7sKGGGx1As+ezvQe pbGRHEafX8xlGUlrq3n8OiN5N0gbowMI0Ym7tTJ++z4SGMLIhajaNWY3DQR6xhm1 dqqqzlEnWUnuYyXtM59F+Nsj+/0gDFAPL94zZmH8pEYg7tEt31TA+K+xIrOU3/Z9 XljToASOAyBZyi7YO57ainbTwZ9S8bM5kRZWObJJXUgbAp5L4MhupKWN5x7qbUhv wRsMm4C3WVzOl3LLhLecPdrWfBmT0MQIztKpgrS7sIrn3qkkctYooyLyu8faNI65 f4XZxw== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ywppv92v3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 10:40:42 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45QAef68029157 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 10:40:41 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 03:40:33 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 1/9] soc: qcom: cpr3: Fix 'acc_desc' usage Date: Wed, 26 Jun 2024 16:09:54 +0530 Message-ID: <20240626104002.420535-2-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240626104002.420535-1-quic_varada@quicinc.com> References: <20240626104002.420535-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ilGCwZTIuqzl_i-MOPFpsaci7NPPh7Cv X-Proofpoint-ORIG-GUID: ilGCwZTIuqzl_i-MOPFpsaci7NPPh7Cv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_05,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 clxscore=1015 priorityscore=1501 mlxlogscore=999 mlxscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260081 cpr3 code assumes that 'acc_desc' is available for SoCs implementing CPR version 4 or less. However, IPQ9574 SoC implements CPRv4 without ACC. This causes NULL pointer accesses resulting in crashes. Hence, check is 'acc_desc' is populated before using it. Signed-off-by: Varadarajan Narayanan --- drivers/pmdomain/qcom/cpr3.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pmdomain/qcom/cpr3.c b/drivers/pmdomain/qcom/cpr3.c index c7790a71e74f..c28028be50d8 100644 --- a/drivers/pmdomain/qcom/cpr3.c +++ b/drivers/pmdomain/qcom/cpr3.c @@ -2399,12 +2399,12 @@ static int cpr_pd_attach_dev(struct generic_pm_domain *domain, if (ret) goto exit; - if (acc_desc->config) + if (acc_desc && acc_desc->config) regmap_multi_reg_write(drv->tcsr, acc_desc->config, acc_desc->num_regs_per_fuse); /* Enable ACC if required */ - if (acc_desc->enable_mask) + if (acc_desc && acc_desc->enable_mask) regmap_update_bits(drv->tcsr, acc_desc->enable_reg, acc_desc->enable_mask, acc_desc->enable_mask); @@ -2676,7 +2676,7 @@ static int cpr_probe(struct platform_device *pdev) desc = data->cpr_desc; /* CPRh disallows MEM-ACC access from the HLOS */ - if (!data->acc_desc && desc->cpr_type < CTRL_TYPE_CPRH) + if (!data->acc_desc && desc->cpr_type < CTRL_TYPE_CPR4) return -EINVAL; drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL); @@ -2703,7 +2703,7 @@ static int cpr_probe(struct platform_device *pdev) mutex_init(&drv->lock); - if (desc->cpr_type < CTRL_TYPE_CPRH) { + if (desc->cpr_type < CTRL_TYPE_CPR4) { np = of_parse_phandle(dev->of_node, "qcom,acc", 0); if (!np) return -ENODEV; From patchwork Wed Jun 26 10:39:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13712622 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 095DC17B405; Wed, 26 Jun 2024 10:40:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719398461; cv=none; b=jGSaJnGWlt24VTKHHHjxQPSe+ein8y1mEms1BxKwxx2Ontr251g/YYUlT158UywVk6v5RG5U6bxsPWcN2tsGJnhQAghH2vHYp10nGHq8k/NDY0nY4ZudegpsA6ubw4Toq7hlXXKJihTmJjyQXo3EbNppGF2u1zwvBoceCz7DT9s= ARC-Message-Signature: i=1; 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Wed, 26 Jun 2024 10:40:48 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 03:40:41 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 2/9] cpufreq: qcom-nvmem: Add genpd names to match_data_kryo Date: Wed, 26 Jun 2024 16:09:55 +0530 Message-ID: <20240626104002.420535-3-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240626104002.420535-1-quic_varada@quicinc.com> References: <20240626104002.420535-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: t3dW5VTpdlXMGJE2hMp-NIgFm9gco2ys X-Proofpoint-GUID: t3dW5VTpdlXMGJE2hMp-NIgFm9gco2ys X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_05,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260081 This is used for tying up the cpu@N nodes with the power domains. Without this, 'cat /sys/kernel/debug/qcom_cpr3/thread0' crashes with NULL pointer access. Signed-off-by: Varadarajan Narayanan --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 939702dfa73f..5e6525c7788c 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -399,6 +399,7 @@ static const char *generic_genpd_names[] = { "perf", NULL }; static const struct qcom_cpufreq_match_data match_data_kryo = { .get_version = qcom_cpufreq_kryo_name_version, + .genpd_names = generic_genpd_names, }; static const struct qcom_cpufreq_match_data match_data_krait = { From patchwork Wed Jun 26 10:39:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13712623 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E830417BB2B; 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Varadarajan Narayanan --- v2: Add Reviewed-by --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 929b7ef9c1bc..e20ba25fa094 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - qcom,ipq9574-rpmpd - qcom,mdm9607-rpmpd - qcom,msm8226-rpmpd - qcom,msm8909-rpmpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 608087fb9a3d..0538370bfbb4 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -402,6 +402,9 @@ #define QCM2290_VDD_LPI_CX 6 #define QCM2290_VDD_LPI_MX 7 +/* IPQ9574 Power Domains */ +#define IPQ9574_VDDAPC 0 + /* RPM SMD Power Domain performance levels */ #define RPM_SMD_LEVEL_RETENTION 16 #define RPM_SMD_LEVEL_RETENTION_PLUS 32 From patchwork Wed Jun 26 10:39:57 2024 Content-Type: text/plain; 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Signed-off-by: Varadarajan Narayanan Reviewed-by: Krzysztof Kozlowski --- v2: Constrained nvmem-cells and the other variant. Removed unnecessary blank line. --- .../bindings/soc/qcom/qcom,cpr3.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml index acf2e294866b..f72addaa0ca2 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml @@ -24,6 +24,7 @@ properties: - const: qcom,cpr4 - items: - enum: + - qcom,ipq9574-cprh - qcom,msm8998-cprh - qcom,sdm630-cprh - const: qcom,cprh @@ -52,9 +53,11 @@ properties: nvmem-cells: description: Cells containing the fuse corners and revision data + minItems: 17 maxItems: 32 nvmem-cell-names: + minItems: 17 maxItems: 32 operating-points-v2: true @@ -74,6 +77,36 @@ required: additionalProperties: false allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9574-cprh + then: + properties: + nvmem-cells: + maxItems: 17 + nvmem-cell-names: + items: + - const: cpr_speed_bin + - const: cpr_fuse_revision + - const: cpr0_quotient1 + - const: cpr0_quotient2 + - const: cpr0_quotient3 + - const: cpr0_quotient4 + - const: cpr0_quotient_offset2 + - const: cpr0_quotient_offset3 + - const: cpr0_quotient_offset4 + - const: cpr0_init_voltage1 + - const: cpr0_init_voltage2 + - const: cpr0_init_voltage3 + - const: cpr0_init_voltage4 + - const: cpr0_ring_osc1 + - const: cpr0_ring_osc2 + - const: cpr0_ring_osc3 + - const: cpr0_ring_osc4 + - if: properties: compatible: @@ -82,6 +115,8 @@ allOf: - qcom,msm8998-cprh then: properties: + nvmem-cells: + minItems: 32 nvmem-cell-names: items: - const: cpr_speed_bin From patchwork Wed Jun 26 10:39:58 2024 Content-Type: text/plain; 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Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan Reviewed-by: Dmitry Baryshkov --- v3: Fix patch author v2: Fix Signed-off-by order --- drivers/pmdomain/qcom/rpmpd.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pmdomain/qcom/rpmpd.c b/drivers/pmdomain/qcom/rpmpd.c index 5e6280b4cf70..947d6a9c3897 100644 --- a/drivers/pmdomain/qcom/rpmpd.c +++ b/drivers/pmdomain/qcom/rpmpd.c @@ -38,6 +38,7 @@ static struct qcom_smd_rpm *rpmpd_smd_rpm; #define KEY_FLOOR_CORNER 0x636676 /* vfc */ #define KEY_FLOOR_LEVEL 0x6c6676 /* vfl */ #define KEY_LEVEL 0x6c766c76 /* vlvl */ +#define RPM_KEY_UV 0x00007675 /* "uv" */ #define MAX_CORNER_RPMPD_STATE 6 @@ -644,6 +645,23 @@ static const struct rpmpd_desc mdm9607_desc = { .max_state = RPM_SMD_LEVEL_TURBO, }; +static struct rpmpd apc_s1_lvl = { + .pd = { .name = "apc", }, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = RPM_KEY_UV, +}; + +static struct rpmpd *ipq9574_rpmpds[] = { + [IPQ9574_VDDAPC] = &apc_s1_lvl, +}; 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Acked-by: Krzysztof Kozlowski Signed-off-by: Varadarajan Narayanan --- v2: Add GCC_RBCPR_CLK_SRC define. Not adding 'Acked-by: Krzysztof Kozlowski' as the file changed. --- include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 52123c5a09fa..4c65de04cb7b 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -220,4 +220,6 @@ #define GCC_PCIE1_PIPE_CLK 211 #define GCC_PCIE2_PIPE_CLK 212 #define GCC_PCIE3_PIPE_CLK 213 +#define GCC_RBCPR_CLK_SRC 214 +#define GCC_RBCPR_CLK 215 #endif From patchwork Wed Jun 26 10:40:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13712647 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C79D2171E7F; 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Wed, 26 Jun 2024 10:41:27 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45QAfQqh008392 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 10:41:26 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 03:41:18 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , , , , CC: Dmitry Baryshkov Subject: [PATCH v3 7/9] clk: qcom: gcc-ipq9574: Add CPR clock definition Date: Wed, 26 Jun 2024 16:10:00 +0530 Message-ID: <20240626104002.420535-8-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240626104002.420535-1-quic_varada@quicinc.com> References: <20240626104002.420535-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: gn8ut9NkqpqYFK8wAi8g4a-_DhoFDBIp X-Proofpoint-GUID: gn8ut9NkqpqYFK8wAi8g4a-_DhoFDBIp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_05,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260081 Add the CPR clock definition needed for enabling access to CPR register space. Reviewed-by: Dmitry Baryshkov Signed-off-by: Varadarajan Narayanan --- drivers/clk/qcom/gcc-ipq9574.c | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index e1dc74d04ed1..eac557937fd3 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -3994,6 +3994,43 @@ static struct clk_branch gcc_xo_div4_clk = { }, }; +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { + F(24000000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 rbcpr_clk_src = { + .cmd_rcgr = 0x48044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_xo_map, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rbcpr_clk_src", + .parent_data = gcc_xo_gpll0_gpll4, + .num_parents = ARRAY_SIZE(gcc_xo_map), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_rbcpr_clk = { + .halt_reg = 0x48008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x48008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rbcpr_clk", + .parent_hws = (const struct clk_hw *[]) { + &rbcpr_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_hw *gcc_ipq9574_hws[] = { &gpll0_out_main_div2.hw, &gcc_xo_div4_clk_src.hw, @@ -4219,6 +4256,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, + [GCC_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, + [GCC_RBCPR_CLK] = &gcc_rbcpr_clk.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = { From patchwork Wed Jun 26 10:40:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13712650 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED0DF181CE5; Wed, 26 Jun 2024 10:41:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan --- v3: Fix patch author Included below information in cover letter v2: Fix Signed-off-by order Depends: [1] https://lore.kernel.org/lkml/20230217-topic-cpr3h-v14-0-9fd23241493d@linaro.org/T/ [2] https://github.com/quic-varada/cpr/commits/konrad/ --- drivers/pmdomain/qcom/cpr3.c | 137 +++++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/drivers/pmdomain/qcom/cpr3.c b/drivers/pmdomain/qcom/cpr3.c index c28028be50d8..66c8a4bd9adc 100644 --- a/drivers/pmdomain/qcom/cpr3.c +++ b/drivers/pmdomain/qcom/cpr3.c @@ -2056,6 +2056,142 @@ static const struct cpr_acc_desc msm8998_cpr_acc_desc = { .cpr_desc = &msm8998_cpr_desc, }; +static const int ipq9574_silver_scaling_factor[][CPR3_RO_COUNT] = { + /* Fuse Corner 0 */ + { + 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949, + 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332 + }, + /* Fuse Corner 1 */ + { + 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949, + 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332 + }, + /* Fuse Corner 2 */ + { + 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949, + 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332 + }, + /* Fuse Corner 3 */ + { + 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949, + 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332 + }, +}; + +static const struct cpr_thread_desc ipq9574_thread_silver = { + .controller_id = 0, + .hw_tid = 0, + .ro_scaling_factor = ipq9574_silver_scaling_factor, + .sensor_range_start = 0, + .sensor_range_end = 6, + .init_voltage_step = 10000, + .init_voltage_width = 6, + .step_quot_init_min = 0, + .step_quot_init_max = 15, + .num_fuse_corners = 4, + .fuse_corner_data = (struct fuse_corner_data[]){ + /* fuse corner 0 */ + { + .ref_uV = 725000, + .max_uV = 725000, + .min_uV = 725000, + .range_uV = 0, + .volt_cloop_adjust = 0, + .volt_oloop_adjust = 0, + .max_volt_scale = 4, + .max_quot_scale = 10, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 1 */ + { + .ref_uV = 862500, + .max_uV = 862500, + .min_uV = 725000, + .range_uV = 0, + .volt_cloop_adjust = 0, + .volt_oloop_adjust = 0, + .max_volt_scale = 500, + .max_quot_scale = 800, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 2 */ + { + .ref_uV = 987500, + .max_uV = 987500, + .min_uV = 787500, + .range_uV = 0, + .volt_cloop_adjust = 0, + .volt_oloop_adjust = 0, + .max_volt_scale = 280, + .max_quot_scale = 650, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + + }, + /* fuse corner 3 */ + { + .ref_uV = 1062500, + .max_uV = 1062500, + .min_uV = 850000, + .range_uV = 0, + .volt_cloop_adjust = 0, + .volt_oloop_adjust = 0, + .max_volt_scale = 430, + .max_quot_scale = 800, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + }, +}; + +static const struct cpr_desc ipq9574_cpr_desc = { + .cpr_type = CTRL_TYPE_CPR4, + .num_threads = 1, + .apm_threshold = 850000, + .apm_crossover = 880000, + .apm_hysteresis = 0, + .cpr_base_voltage = 700000, + .cpr_max_voltage = 1100000, + .timer_delay_us = 5000, + .timer_cons_up = 0, + .timer_cons_down = 0, + .up_threshold = 2, + .down_threshold = 2, + .idle_clocks = 15, + .count_mode = CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN, + .count_repeat = 1, + .gcnt_us = 1, + .vreg_step_fixed = 12500, + .vreg_step_up_limit = 1, + .vreg_step_down_limit = 1, + .vdd_settle_time_us = 34, + .corner_settle_time_us = 6, + .reduce_to_corner_uV = true, + .hw_closed_loop_en = false, + .threads = (const struct cpr_thread_desc *[]) { + &ipq9574_thread_silver, + }, +}; + +static const struct cpr_acc_desc ipq9574_cpr_acc_desc = { + .cpr_desc = &ipq9574_cpr_desc, +}; + static const int sdm630_gold_scaling_factor[][CPR3_RO_COUNT] = { /* Same RO factors for all fuse corners */ { @@ -2828,6 +2964,7 @@ static void cpr_remove(struct platform_device *pdev) } static const struct of_device_id cpr3_match_table[] = { + { .compatible = "qcom,ipq9574-cprh", .data = &ipq9574_cpr_acc_desc }, { .compatible = "qcom,msm8998-cprh", .data = &msm8998_cpr_acc_desc }, { .compatible = "qcom,sdm630-cprh", .data = &sdm630_cpr_acc_desc }, { } From patchwork Wed Jun 26 10:40:02 2024 Content-Type: text/plain; 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Wed, 26 Jun 2024 10:41:40 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 03:41:33 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 9/9] dts: arm64: qcom: ipq9574: Enable CPR Date: Wed, 26 Jun 2024 16:10:02 +0530 Message-ID: <20240626104002.420535-10-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240626104002.420535-1-quic_varada@quicinc.com> References: <20240626104002.420535-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: bDQuRij3OsFfIVjibH7aiY9yKmCQ4N14 X-Proofpoint-ORIG-GUID: bDQuRij3OsFfIVjibH7aiY9yKmCQ4N14 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_05,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 suspectscore=0 phishscore=0 clxscore=1015 spamscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260081 * Add CPR, RPMPD, OPP table nodes as applicable to IPQ9574 to enable CPR functionality on IPQ9574. * Bootloader set frequency 792MHz is added to the OPP table to the avoid unknown frequency warning message at boot time. * Remove 1.2GHz as it is not supported in any of the IPQ9574 SKUs. Signed-off-by: Varadarajan Narayanan --- v2: Update commit log. No code change. --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 269 ++++++++++++++++++++++++-- 1 file changed, 252 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 04ba09a9156c..439ee5accc47 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -42,8 +43,9 @@ CPU0: cpu@0 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq9574_s1>; #cooling-cells = <2>; + power-domains = <&apc_cprh 0>; + power-domain-names = "perf"; }; CPU1: cpu@1 { @@ -55,8 +57,9 @@ CPU1: cpu@1 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq9574_s1>; #cooling-cells = <2>; + power-domains = <&apc_cprh 0>; + power-domain-names = "perf"; }; CPU2: cpu@2 { @@ -68,8 +71,9 @@ CPU2: cpu@2 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq9574_s1>; #cooling-cells = <2>; + power-domains = <&apc_cprh 0>; + power-domain-names = "perf"; }; CPU3: cpu@3 { @@ -81,8 +85,9 @@ CPU3: cpu@3 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq9574_s1>; #cooling-cells = <2>; + power-domains = <&apc_cprh 0>; + power-domain-names = "perf"; }; L2_0: l2-cache { @@ -105,58 +110,111 @@ memory@40000000 { reg = <0x0 0x40000000 0x0 0x0>; }; + cprh_opp_table: opp-table-cprh { + compatible = "operating-points-v2-qcom-level"; + + cprh_opp0: opp-0 { + opp-level = <1>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp1: opp-1 { + opp-level = <2>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp2: opp-2 { + opp-level = <3>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp3: opp-3 { + opp-level = <4>; + qcom,opp-fuse-level = <2>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp4: opp-4 { + opp-level = <5>; + qcom,opp-fuse-level = <2>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp5: opp-5 { + opp-level = <6>; + qcom,opp-fuse-level = <3>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp6: opp-6 { + opp-level = <7>; + qcom,opp-fuse-level = <4>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + }; + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2-kryo-cpu"; opp-shared; nvmem-cells = <&cpu_speed_bin>; + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0>; + clock-latency-ns = <200000>; + required-opps = <&cprh_opp0>; + }; + opp-936000000 { opp-hz = /bits/ 64 <936000000>; - opp-microvolt = <725000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + required-opps = <&cprh_opp1>; }; opp-1104000000 { opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <787500>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <862500>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + required-opps = <&cprh_opp2>; }; opp-1416000000 { opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <862500>; opp-supported-hw = <0x7>; clock-latency-ns = <200000>; + required-opps = <&cprh_opp3>; }; opp-1488000000 { opp-hz = /bits/ 64 <1488000000>; - opp-microvolt = <925000>; opp-supported-hw = <0x7>; clock-latency-ns = <200000>; + required-opps = <&cprh_opp4>; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <987500>; opp-supported-hw = <0x5>; clock-latency-ns = <200000>; + required-opps = <&cprh_opp5>; }; opp-2208000000 { opp-hz = /bits/ 64 <2208000000>; - opp-microvolt = <1062500>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; + required-opps = <&cprh_opp6>; }; }; @@ -182,6 +240,40 @@ glink-edge { rpm_requests: rpm-requests { compatible = "qcom,rpm-ipq9574"; qcom,glink-channels = "rpm_requests"; + + rpmpd: power-controller { + compatible = "qcom,ipq9574-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_svs: opp1 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_nom: opp3 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp4 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp5 { + opp-level = ; + }; + + rpmpd_opp_turbo_high: opp6 { + opp-level = ; + }; + }; + }; }; }; }; @@ -252,6 +344,95 @@ cpu_speed_bin: cpu-speed-bin@15 { reg = <0x15 0x2>; bits = <7 2>; }; + + cpr_efuse_speedbin: speedbin@5 { + reg = <0x5 0x8>; + bits = <0 3>; + }; + + cpr_fuse_revision: cpr-fusing-rev@7 { + reg = <0x7 0x8>; + bits = <1 5>; + }; + + /* CPR Ring Oscillator: Power Cluster */ + cpr_ro_sel0_pwrcl: rosel0-pwrcl@358 { /* ROSEL_SVS */ + reg = <0x358 0x1>; + bits = <4 4>; + }; + + cpr_ro_sel1_pwrcl: rosel1-pwrcl@358 { /* ROSEL_NOM */ + reg = <0x358 0x1>; + bits = <0 4>; + }; + + cpr_ro_sel2_pwrcl: rosel2-pwrcl@350 { /* ROSEL_TUR */ + reg = <0x350 0x1>; + bits = <4 4>; + }; + + cpr_ro_sel3_pwrcl: rosel3-pwrcl@350 { /* ROSEL_STUR */ + reg = <0x350 0x1>; + bits = <0 4>; + }; + + /* CPR Init Voltage: Power Cluster */ + cpr_init_voltage0_pwrcl: ivolt0-pwrcl@343 { /* VOLT_SVS */ + reg = <0x343 0x1>; + bits = <0 6>; + }; + + cpr_init_voltage1_pwrcl: ivolt1-pwrcl@342 { /* VOLT_NOM */ + reg = <0x342 0x1>; + bits = <2 6>; + }; + + cpr_init_voltage2_pwrcl: ivolt2-pwrcl@341 { /* VOLT_TUR */ + reg = <0x341 0x2>; + bits = <4 6>; + }; + + cpr_init_voltage3_pwrcl: ivolt3-pwrcl@340 { /* VOLT_STUR */ + reg = <0x340 0x2>; + bits = <6 6>; + }; + + /* CPR Target Quotients: Power Cluster */ + cpr_quot0_pwrcl: quot0-pwrcl@354 { /* QUOT_VMIN_SVS */ + reg = <0x354 0x2>; + bits = <0 12>; + }; + + cpr_quot1_pwrcl: quot1-pwrcl@352 { /* QUOT_VMIN_NOM */ + reg = <0x352 0x2>; + bits = <4 12>; + }; + + cpr_quot2_pwrcl: quot2-pwrcl@351 { /* QUOT_VMIN_TUR */ + reg = <0x351 0x2>; + bits = <0 12>; + }; + + cpr_quot3_pwrcl: quot3-pwrcl@355 { /* QUOT_VMIN_STUR */ + reg = <0x355 0x2>; + bits = <4 12>; + }; + + /* CPR Quotient Offsets: Power Cluster */ + cpr_quot_offset1_pwrcl: qoff1-pwrcl@34e { /* QUOT_OFFSET_NOM_SVS */ + reg = <0x34e 0x1>; + bits = <0 8>; + }; + + cpr_quot_offset2_pwrcl: qoff2-pwrcl@34d { /* QUOT_OFFSET_TUR_NOM */ + reg = <0x34d 0x1>; + bits = <0 8>; + }; + + cpr_quot_offset3_pwrcl: qoff0-pwrcl@34c { /* QUOT_OFFSET_STUR_TUR */ + reg = <0x34c 0x1>; + bits = <0 8>; + }; }; cryptobam: dma-controller@704000 { @@ -639,6 +820,60 @@ usb_0_dwc3: usb@8a00000 { }; }; + apc_cprh: power-controller@b018000 { + compatible = "qcom,ipq9574-cprh", "qcom,cprh"; + reg = <0x0b018000 0x4000>, + <0x00048000 0x4000>; + + clocks = <&gcc GCC_RBCPR_CLK>; + + interrupts = ; + vdd-supply = <&ipq9574_s1>; + + /* Set the CPR clock here, it needs to match XO */ + assigned-clocks = <&gcc GCC_RBCPR_CLK>; + assigned-clock-rates = <24000000>; + + operating-points-v2 = <&cprh_opp_table>; + power-domains = <&rpmpd IPQ9574_VDDAPC>; + #power-domain-cells = <1>; + + nvmem-cells = <&cpr_efuse_speedbin>, + <&cpr_fuse_revision>, + <&cpr_quot0_pwrcl>, + <&cpr_quot1_pwrcl>, + <&cpr_quot2_pwrcl>, + <&cpr_quot3_pwrcl>, + <&cpr_quot_offset1_pwrcl>, + <&cpr_quot_offset2_pwrcl>, + <&cpr_quot_offset3_pwrcl>, + <&cpr_init_voltage0_pwrcl>, + <&cpr_init_voltage1_pwrcl>, + <&cpr_init_voltage2_pwrcl>, + <&cpr_init_voltage3_pwrcl>, + <&cpr_ro_sel0_pwrcl>, + <&cpr_ro_sel1_pwrcl>, + <&cpr_ro_sel2_pwrcl>, + <&cpr_ro_sel3_pwrcl>; + nvmem-cell-names = "cpr_speed_bin", + "cpr_fuse_revision", + "cpr0_quotient1", + "cpr0_quotient2", + "cpr0_quotient3", + "cpr0_quotient4", + "cpr0_quotient_offset2", + "cpr0_quotient_offset3", + "cpr0_quotient_offset4", + "cpr0_init_voltage1", + "cpr0_init_voltage2", + "cpr0_init_voltage3", + "cpr0_init_voltage4", + "cpr0_ring_osc1", + "cpr0_ring_osc2", + "cpr0_ring_osc3", + "cpr0_ring_osc4"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */