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[95.127.32.72]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42564b65a0fsm26893555e9.16.2024.06.27.05.58.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 27 Jun 2024 05:58:30 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Song Gao , maobibo , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/1] hw/intc/loongson_ipi: Gate MMIO regions creation with property Date: Thu, 27 Jun 2024 14:58:19 +0200 Message-ID: <20240627125819.62779-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240627125819.62779-1-philmd@linaro.org> References: <20240627125819.62779-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Jiaxun Yang Commit 49eba52a52fe ("hw/intc/loongson_ipi: Provide per core MMIO address spaces") implemented per core MMIO spaces for IPI registers. However on LoongArch system emulation with high core count it may exhaust QDEV_MAX_MMIO and trigger assertion. Given that MMIO region is unused for LoongArch system emulation (we do have it on hardware but kernel is in favor of IOCSR), gate MMIO regions creation with "has-mmio" property and only set if for loongson3-virt machine to avoid such limitation on LoongArch. Reported-by: Bibo Mao Signed-off-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- include/hw/intc/loongson_ipi.h | 1 + hw/intc/loongson_ipi.c | 16 ++++++++++------ hw/mips/loongson3_virt.c | 1 + 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 3f795edbf3..0e35674e7a 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -50,6 +50,7 @@ struct LoongsonIPI { MemoryRegion ipi_iocsr_mem; MemoryRegion ipi64_iocsr_mem; uint32_t num_cpu; + bool has_mmio; IPICore *cpu; }; diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index e6a7142480..d1b7a80d7b 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -307,13 +307,16 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) for (i = 0; i < s->num_cpu; i++) { s->cpu[i].ipi = s; - s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1); - g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); - memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), - &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); - sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); - qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); + + if (s->has_mmio) { + g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); + s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1); + memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), + &loongson_ipi_core_ops, &s->cpu[i], + name, 0x48); + sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); + } } } @@ -344,6 +347,7 @@ static const VMStateDescription vmstate_loongson_ipi = { static Property ipi_properties[] = { DEFINE_PROP_UINT32("num-cpu", LoongsonIPI, num_cpu, 1), + DEFINE_PROP_BOOL("has-mmio", LoongsonIPI, has_mmio, false), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index 4ad36f0c5b..a27b30ab31 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -537,6 +537,7 @@ static void mips_loongson3_virt_init(MachineState *machine) if (!kvm_enabled()) { ipi = qdev_new(TYPE_LOONGSON_IPI); qdev_prop_set_uint32(ipi, "num-cpu", machine->smp.cpus); + qdev_prop_set_bit(ipi, "has-mmio", true); sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); memory_region_add_subregion(iocsr, SMP_IPI_MAILBOX, sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0));